JPH11186353A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and a manufacturing method thereof, which is able to secure a TEG region for a TEG(test element group) with a sufficient area, even with respect to shrinkage of the chip area of a semiconductor wafer. SOLUTION: This semiconductor wafer has a DRAM chip formed of a dynamic memory cell and constituted of a plurality of main body regions 2, where the DRAM chip is formed and a plurality of scribing regions 3 are formed between the regions 2. The wafer is divided by scribing regions 3. The DRAM chip formed on the main body region 2 is divided into individual chips. Especially in the scribing region 3, the indispensable patterns for such advanced process of wafer processing as an inspecting pattern 11 and an matching pattern 12 used in the process before the formation of this patter are formed at the lower layer 10 for TEG, connected to a TEG 8 that is formed at each layer via a TEG wiring 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern arrangement technology for a semiconductor integrated circuit device, and more particularly to an arrangement of a pattern necessary only in a pre-process in a wafer processing step of a semiconductor wafer and a TEG (Test Element Group) pattern. The present invention relates to a semiconductor integrated circuit device suitable for effective use of the area of a pattern in a shot and a technique effective when applied to a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, a wafer processing step of a semiconductor wafer generally includes repetition of processes such as thin film formation, oxidation, doping, annealing, resist processing, exposure, etching, and cleaning. ,
For example, in the projection exposure process, it is considered that a stepper for repeatedly exposing a semiconductor wafer to a projection image of a mask pattern and exposing the semiconductor wafer is used.

In a projection exposure process using this stepper, an alignment pattern (target) formed on a mask is used for alignment, and positioning using this alignment pattern has already been performed on a semiconductor wafer in a previous step. This is performed by aligning with the formed inspection pattern (vernier).

[0004] The wafer processing steps including such projection exposure processing are described in, for example, "LSI Handbook" P253 to P364, published by Ohm Co., Ltd., edited by the Institute of Electronics and Communication Engineers on November 30, 1984. And the techniques described in the literature.

[0005]

In the projection exposure processing technology using a stepper as described above, with the recent reduction in the area of a chip, which is the main region of a semiconductor wafer, the pattern of a target or the like which is not scaled is reduced. The area occupied in the chip shot becomes larger, and the present inventors have found the following examination results.

FIG. 1 shows a schematic layout of a main region 2 and a scribe region 3 of a semiconductor wafer 1.
2 will be described. In FIG. 12, an example in which a TEG for wafer inspection and a pattern indispensable for a pre-process of wafer processing are arranged in a scribe region 3 between the main regions 2 of the chips as shown in FIG. Is shown.

(1) As shown in FIG. 12 (b), the number of wafer inspection TEGs must be reduced from the current number as the chip area in the main body region 2 is reduced. become unable.

(2) As shown in FIG. 12 (c), along with the further reduction of the area of the chip in the main body region 2, a pattern such as a target pattern, which is indispensable for the pre-process, cannot be placed within the current scribe width. Arranging this pattern leads to an increase in the scribe area 3.

Therefore, the inventor of the present invention has proposed that the target pattern and the like are necessary only for the pre-process, and after the completion of the wafer, they need a large area, although they are not necessary. In order to reduce the area of the TEG, attention has been paid to the fact that the area for arranging the TEG is reduced, and the reduction in the area of the TEG is problematic as the chip area is reduced.

That is, in the relationship between the target pattern used only in the pre-process and the TEG region including the TEG pad, the pad is used on the pattern necessary for the pre-process only. The present inventor has found that an area can be reserved for TEG.

Therefore, an object of the present invention is to arrange a pad or a wiring in a layer above a pattern used only in a pre-process, thereby reducing the area of a chip which is a main body region of a semiconductor wafer. TE including pad for
An object of the present invention is to provide a semiconductor integrated circuit device capable of securing a G region with a sufficient area and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device according to the present invention is applied to a semiconductor wafer in which an integrated circuit is formed in a main body region and a TEG is formed in a scribe region.
In the lower layer of the TEG pattern formed in the scribe region, for example, the TEG pad and the TEG wiring, a pattern necessary only in the pre-process by repeating the wafer processing process of the semiconductor wafer, for example, the inspection pattern, the vernier, the alignment pattern, It is configured by forming a target pattern.

In another semiconductor integrated circuit device according to the present invention, an integrated circuit pattern formed in a main body region, for example, a bonding pad, a probe inspection pad, a power supply wiring, and a lower layer of a semiconductor wafer are formed in a lower layer. A required pattern is formed only in the pre-process by repetition.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a pattern necessary only in a pre-process by repeating a wafer processing step in a scribe region, and a step of forming a pattern in the scribe region after the formation of the pattern in the scribe region Forming a TEG pattern in an upper layer of the pattern.

Further, another method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a pattern required only in a pre-process by repeating a wafer processing step in a main body region, and a step of forming a pattern on the main body region. Forming a pattern for an integrated circuit on this pattern after the formation.

That is, according to the semiconductor integrated circuit device and the method of manufacturing the same, as shown in the conceptual diagram of FIG. 1 showing a schematic layout of the main region 2 and the scribe region 3 of the semiconductor wafer 1, TEG as in (a)
A pattern used only for the pre-process is arranged below the pattern for use, and as a second step, the TEG having an area sufficient for reducing the chip area in the main body region as shown in FIG.
As a third step, as shown in (c), in order to further reduce the area of the chip as shown in FIG. Thus, it is possible to effectively use the area of the pattern inside.

Therefore, by effectively utilizing the area of the pattern in the shot, a pattern indispensable for the pre-process is arranged even when the area of the chip which is the main region of the semiconductor wafer is reduced, and the TEG for wafer inspection is arranged. Can be secured in a sufficient area, and a detailed process monitor can be performed by the TEG having the sufficient area.

Further, since the shot area (scribe width) can be reduced and the shot area can be suppressed from increasing as a product, it is possible to increase the number of obtained chips.

Further, by disposing a pattern indispensable for the pre-process in the lower layer of the bonding pad and the probe inspection pad which is the center of the shot, the alignment accuracy in the exposure step can be improved.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1) FIGS. 2A and 2B are schematic layout diagrams showing a semiconductor wafer and a semiconductor chip in the semiconductor integrated circuit device according to Embodiment 1 of the present invention. 3 (a) and 3 (b) are schematic layout diagrams showing pattern examples of the scribe area in the first embodiment.
6 to 6 are flow charts showing a wafer processing step of a semiconductor wafer, and corresponding sectional views and plan views of the semiconductor wafer. FIGS. 7 (a) and 7 (b) and FIGS. 8 (a) and 8 (b) show the present embodiment. Form 1
FIG. 14 is a schematic layout diagram showing an example of a pattern of a scribe area according to a modified example of FIG.

First, a schematic configuration of a semiconductor wafer and a semiconductor chip in the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIG.

The semiconductor wafer in the semiconductor integrated circuit device of the first embodiment is, for example, a semiconductor wafer 1 on which a DRAM chip is formed by dynamic memory cells, and a plurality of main regions 2 on which the DRAM chip is formed.
And a plurality of scribe areas 3 formed between these main areas 2.
The DRAM chips formed in the main body region 2 by cutting are divided into individual chips.

In each of the body regions 2, a circuit region 4 in which an integrated circuit of a DRAM chip is formed, a terminal region 5 in which bonding pads and probe inspection pads are arranged, and a power supply from the terminal region 5 to the circuit region 4. A power supply wiring area 6 in which a power supply wiring for supply is formed is provided, and a memory array and its peripheral circuits are formed in the integrated circuit in the circuit area 4.

An arbitrary scribe area 3 is provided with a circuit area 7 in which a TEG for wafer inspection is formed. This TEG is used for starting a new manufacturing process, before changing a process, and so on, for evaluating circuit characteristics and process characteristics. This is a test element group formed on the semiconductor wafer 1 for evaluation.

In the semiconductor wafer 1 configured as described above, in particular, in order to effectively use the area of the pattern in the shot even when the area of the DRAM chip is reduced,
A pattern required only for the pre-process is formed below the pattern in a predetermined range of the scribe area 3 and the main body area 2.

For example, as shown in FIG. 3, in an arbitrary scribe region 3, a TEG 8 is formed in each layer.
EG8 is connected to TE in any layer via TEG wiring 9.
The test pattern 11 (vernier), the alignment pattern 12 (target), and the like, which are connected to the G pad 10 and are used in a process before the pattern is formed, are formed below the pattern on which the TEG pad 10 is formed. A pattern indispensable for a pre-process of wafer processing is formed. Here, an example of a KLA pattern with a square frame is shown.

Next, the operation of the first embodiment will be described with reference to FIGS. In FIGS. 4 to 6, the center diagrams are cross-sectional views (top) and plan views (bottom) of the inspection pattern portion corresponding to the flow on the left side, and the right diagrams are cross-sectional views (top) of the circuit portion corresponding to the flow. ) And a plan view (bottom).

(1) In forming an element formation region (step 401), for example, a circuit portion on a silicon substrate 13
An element formation region separated by the field oxide film 14 is formed. This circuit section is formed in the circuit area 4 of the main body area 2, and the inspection pattern section is formed in the scribe area 3. It is assumed that a MOS transistor is formed in the circuit section, for example.

(2) In forming the gate electrode (step 402), for example, after forming a polysilicon film 15 for forming a gate electrode in an element formation region of a circuit portion,
The semiconductor layer 16 serving as a source and a drain is formed by implanting ions. When the gate electrode is formed, the inspection pattern 11 is formed in the inspection pattern portion by a square frame on the underlying layer of the polysilicon film 15.

(3) In forming an opening in the resist (step 403), after forming an insulating film 17 on the circuit portion, a resist 18 is applied, and the resist 18 is exposed for each shot using a mask. Then, an opening 19 for forming a source electrode and a drain electrode is formed. Since the alignment pattern 12 is formed on this mask, the inspection pattern 1
1 and exposure is performed so that the alignment pattern 12 of the mask is positioned inside. As a result, the resist 1 on the mating layer of the insulating film 17 is also provided in the inspection pattern portion.
8, the opening 19 of the pattern 12 is formed.

(4) In forming a contact hole (step 404), the circuit portion is etched using the exposure pattern of the resist 18 as a mask, and the contact hole 20 for forming a source electrode and a drain electrode in the insulating film 17 is formed. Open. At this time, a contact hole 20 of the matching pattern 12 is opened also in the inspection pattern portion with the matching layer of the insulating film 17.

(5) In forming the wiring of the source electrode and the drain electrode (step 405),
The contact hole 20 of the insulating film 17 is filled with a wiring material, and a wiring 21 of a source electrode and a drain electrode connected thereto is formed. When filling the wiring material, the wiring material is also filled into the contact holes 20 of the matching layer formed by the insulating film 17 in the inspection pattern portion.

(6) In forming the bonding pads for the gate electrode, the source electrode and the drain electrode (step 406), steps such as resist application, exposure, and etching are repeated on the circuit portion to form the insulating film 17 and the wiring 2
Then, bonding pads 22 for the gate electrode, the source electrode, and the drain electrode are formed. At this time, the TEG pad 1
0 is formed. The TEG pad 10 is connected to the TEG 8 formed in each layer in each step via the TEG wiring 9.

Through the above-described wafer processing steps, the probe inspection pad 23 can be formed on the uppermost layer of the circuit portion together with the bonding electrode 22 for the gate electrode, the source electrode, and the drain electrode. 3, a TEG pad 10 that is not restricted in processing even if this pattern is present in a lower layer is placed on the upper layer of a pattern necessary only for the pre-process such as the inspection pattern 11 and the alignment pattern 12. It can be formed in the upper layer.

After the wafer processing step is completed, in a wafer inspection step, a test needle is applied to the TEG pad 10 to perform an electrical characteristic test, whereby circuit characteristics and process characteristics of the semiconductor wafer 1 can be evaluated. it can. Further, thereafter, in the probe inspection, a function inspection for selecting a non-defective / defective product for each DRAM chip is performed by applying a probe needle to the probe inspection pad 23.

The DRAM chips selected as non-defective products in the wafer processing process are subjected to processes such as dicing, die bonding, wire bonding, molding, lead molding, and marking in a post-assembly process, and are then integrated into a semiconductor structure having a package structure. A circuit device, in this case a DRAM semiconductor memory, can be manufactured.

Therefore, according to the semiconductor integrated circuit device of the first embodiment, the TEG pad 10 in the scribe region 3
Inspection pattern 1 required only for the pre-process in the lower layer
1. By arranging the matching pattern 12 and the like, the area of the pattern in the shot can be effectively used, and the DRA
In order to reduce the area of the M chip, it is possible to arrange a pattern indispensable for the pre-process and arrange a TEG 8 for wafer inspection with a sufficient area. As a result, a detailed process monitor can be performed by the TEG 8 having a sufficient area.

Further, the shot area (scribe width) can be reduced by effectively utilizing the area of the pattern in the shot, and the increase in the shot area as a product can be suppressed. As a result, an increase in the number of obtained chips can be realized.

In the case of the first embodiment,
For example, as shown in FIG. 7, the scribe region 3 can be divided into a region where a TEG 8 for wafer inspection is arranged and a region where a pattern necessary only for the pre-process is arranged. Also TEG pad 1
By arranging the inspection pattern 11, the alignment pattern 12, and the like in the lower layer of 0, it is possible to effectively use the area of the pattern in the shot as in the arrangement of FIG.

Further, when the TEG 8 and the pattern of the pre-process are not arranged in the scribe region 3 but are arranged as shown in FIG.
In the lower layer of the TEG wiring 9 connecting the EG 8 and the TEG pad 10, a pattern such as the inspection pattern 11 and the alignment pattern 12, which is necessary only for the pre-process, can be arranged. Also in this case, it is possible to make effective use of the area of the pattern in the shot as in the arrangement of FIG.

(Embodiment 2) FIGS. 9A, 9B, and 9C are schematic layout diagrams showing pattern examples of a main body region in a semiconductor integrated circuit device according to Embodiment 2 of the present invention.
FIGS. 11A and 11B are schematic layout diagrams showing shot units of the main body region according to the second embodiment, and FIGS. 11A, 11B and 11C are main body regions according to a modification of the second embodiment. FIG. 5 is a schematic layout diagram showing an example of the pattern.

The semiconductor wafer in the semiconductor integrated circuit device of the second embodiment has the same structure as that of the first embodiment.
It is composed of a plurality of main areas 2 on which AM chips are formed and a plurality of scribe areas 3 formed between these main areas 2. The difference from the first embodiment is not the scribe area 3 but the scribe area 3. In addition, a pattern required only for the pre-process is formed below a predetermined range of the main body region 2.

That is, in the second embodiment, as shown in FIG. 9, for example, in order to effectively use the area of the pattern in the shot even when the area of the DRAM chip is reduced, an arbitrary part of the main body region 2 is used. Bonding pad 2
2. In the lower layer of the pattern of the probe inspection pad 23, it is indispensable for the pre-process of the wafer processing such as the inspection pattern 11 (vernier) and the alignment pattern 12 (target) used in the process before this pattern is formed. Pattern is formed. In FIG. 9, (c)
FIG. 4B is a cross-sectional view taken along the line cc ′ of FIG.

Therefore, also in the second embodiment, after the wafer processing step, the terminal area 5 of the main body area 2 is placed on the upper layer of the pattern such as the inspection pattern 11 and the alignment pattern 12 which is necessary only for the pre-process. Even if this pattern exists in the lower layer, it is possible to form the bonding pad 22 and the probe inspection pad 23 which are not restricted in processing.

Therefore, according to the semiconductor integrated circuit device of the second embodiment, the bonding pads 2
2. In the lower layer of the probe inspection pad 23, the inspection pattern 11 and the alignment pattern 12 necessary only for the pre-process.
By arranging the TEG 8 and the like, the area of the pattern in the shot is effectively used similarly to the first embodiment.
By ensuring a sufficient area, it is possible to perform a detailed process monitor, and further, it is possible to suppress an increase in the shot area (scribe width) and increase the number of obtained chips.

In the case of the second embodiment,
For example, as shown in FIG.
To the bonding pad 22, the probe inspection pad 2
3, that is, immediately below the pad which is the center of the shot, the misalignment can be reduced as compared with the case where the shot is located away from the center of the shot as shown in FIG. The alignment accuracy can be improved.

In the case of the second embodiment,
For example, as shown in FIG. 11, it is also possible to arrange a pattern necessary only for the pre-process in the lower layer of power supply wiring region 6 in main body region 2. Pattern 11, Matching pattern 12
By arranging, for example, it is possible to effectively use the area of the pattern in the shot in the same manner as in the arrangement of FIG.

The invention made by the inventor has been specifically described based on the first and second embodiments.
The present invention is not limited to the above embodiment, and it goes without saying that various changes can be made without departing from the spirit of the present invention.

For example, in the above-described embodiment, the inspection pattern and the alignment pattern have been described as examples of the KLA pattern using a rectangular frame. However, the present invention can be applied to a wide variety of patterns of other shapes, In the process, any shape may be used as long as it can be aligned in a subsequent process following the previous process.

In the above description, the case where the invention made mainly by the present inventors is applied to a semiconductor integrated circuit device using a DRAM semiconductor memory, which is a technical field to which the invention belongs, has been described. However, the present invention is not limited to this.
SRAM, RAM, ROM, PROM, EPROM, E
The present invention can be widely applied to other semiconductor memories such as an EPROM and semiconductor integrated circuit devices such as a microprocessor.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By forming a pattern necessary only for the pre-process in the lower layer of the TEG pattern formed in the scribe area of the semiconductor wafer, and by effectively utilizing the area of the pattern in the shot, In order to reduce the chip area, it is possible to place a pattern indispensable to the pre-process and to secure a sufficient area to place the TEG for wafer inspection, enabling detailed process monitoring. Become.

(2) According to the above (1), the shot area (scribe width) can be reduced by effectively utilizing the area of the pattern in the shot, and the increase in the shot area as a product can be suppressed. It is possible to increase the number of obtained chips.

(3) In the case where a pattern required only in the pre-process is formed below the integrated circuit pattern formed in the main body region of the semiconductor wafer, the area of the pattern in the shot is further reduced. Since a sufficient area of the TEG can be ensured, a detailed process monitor can be performed, and an increase in shot area (scribe width) can be suppressed to increase the number of obtained chips. It becomes possible.

(4) In the above (3), the alignment required in the exposure process can be improved by arranging the necessary pattern only in the pre-process in the lower layer of the bonding pad and the probe inspection pad which is the center of the shot. Becomes possible.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are conceptual diagrams showing an example of pattern arrangement accompanying a reduction in the area of a semiconductor chip in a semiconductor integrated circuit device of the present invention.

FIGS. 2A and 2B are schematic layout diagrams showing a semiconductor wafer and a semiconductor chip in the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIGS. 3 (a) and 3 (b) are schematic layout diagrams showing a pattern example of a scribe area according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a wafer processing step of a semiconductor wafer according to the first embodiment of the present invention, and a sectional view and a plan view of the corresponding semiconductor wafer.

FIG. 5 is a flow chart showing a wafer processing step of the semiconductor wafer following FIG. 4 in the first embodiment of the present invention, and a cross-sectional view and a plan view of the corresponding semiconductor wafer.

6A and 6B are a flow chart showing a wafer processing step of the semiconductor wafer subsequent to FIG. 5 in the first embodiment of the present invention, and a sectional view and a plan view of the corresponding semiconductor wafer.

FIGS. 7A and 7B are schematic layout diagrams showing a pattern example of a scribe area according to a modification of the first embodiment of the present invention; FIGS.

FIGS. 8A and 8B are schematic layout diagrams illustrating examples of patterns of a scribe area according to another modification in the first embodiment of the present invention. FIGS.

FIGS. 9A, 9B, and 9C are schematic layout diagrams illustrating examples of patterns of a main body region in a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIGS. 10A and 10B are schematic layout diagrams showing shot units in a main body region according to the second embodiment of the present invention.

FIGS. 11A, 11B, and 11C are schematic layout diagrams illustrating pattern examples of a main body region according to a modification of the second embodiment of the present invention. FIGS.

FIGS. 12A, 12B, and 12C are conceptual diagrams showing an example of pattern arrangement accompanying a reduction in the area of a semiconductor chip in a semiconductor integrated circuit device on which the present invention is based;

[Explanation of symbols]

 Reference Signs List 1 semiconductor wafer 2 main body region 3 scribe region 4 circuit region 5 terminal region 6 power supply wiring region 7 circuit region 8 TEG 9 TEG wiring 10 TEG pad 11 inspection pattern 12 matching pattern 13 silicon substrate 14 field oxide film 15 polysilicon film 16 Semiconductor layer 17 Insulating film 18 Resist 19 Opening 20 Contact hole 21 Wiring 22 Bonding pad 23 Probe inspection pad 24 Power supply wiring

 ──────────────────────────────────────────────────の Continued on front page (72) Inventor Hiroyuki Miyano 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Yoshiro Toshiho 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the center (72) Inventor Chisa Makimura 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Hidetoshi Iwai 2326 Imai, Imai, Tokyo, Japan Device Development Center, Hitachi, Ltd

Claims (7)

[Claims] 1. A semiconductor integrated circuit device in which an integrated circuit is formed in a chip unit on a semiconductor wafer and a TEG is formed in a scribe region excluding a main body region in which the integrated circuit is formed, wherein the scribe region is provided. A semiconductor integrated circuit device, wherein a pattern required only in a pre-process by repetition of a wafer processing step of the semiconductor wafer is formed in a lower layer of the TEG pattern formed in step (a). 2. The semiconductor integrated circuit device according to claim 1, wherein the TEG pattern is a TEG pad, TE
A semiconductor integrated circuit device, which is a G wiring. 3. A semiconductor integrated circuit device wherein an integrated circuit is formed on a semiconductor wafer in chip units, and a TEG is formed in a scribe area excluding a main body area where the integrated circuit is formed, wherein the main body area is formed. A semiconductor integrated circuit device, wherein a pattern required only in a pre-process by repeating a wafer processing step of the semiconductor wafer is formed in a lower layer of the integrated circuit pattern formed in the above. 4. The semiconductor integrated circuit device according to claim 3, wherein said integrated circuit pattern is a bonding pad, a probe inspection pad, and a power supply wiring. 5. The semiconductor integrated circuit device according to claim 1, wherein the patterns required only in the pre-process include an inspection pattern, a vernier, an alignment pattern, and a target pattern. Integrated circuit device. 6. A method of manufacturing a semiconductor integrated circuit device including at least a wafer processing step of forming an integrated circuit in a chip unit on a semiconductor wafer and forming a TEG in a scribe area excluding a main body area in which the integrated circuit is formed. Forming a pattern required only in a pre-process by repeating the wafer processing step in the scribe area; and forming a TEG pattern on an upper layer of the pattern after the pattern is formed in the scribe area. And a method of manufacturing a semiconductor integrated circuit device. 7. A method of manufacturing a semiconductor integrated circuit device, the method including at least a wafer processing step of forming an integrated circuit in a chip unit on a semiconductor wafer and forming a TEG in a scribe region excluding a main body region where the integrated circuit is formed. Forming a pattern required only in a pre-process by repeating the wafer processing step in the main body region, and forming an integrated circuit pattern on an upper layer of the pattern after forming the pattern in the main body region. A method of manufacturing a semiconductor integrated circuit device.