JP2004239760A - Self erase/write device of semiconductor memory and self burn-in test method for semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a burn-in test, severe and flexible, even when a rewritable nonvolatile semiconductor memory is tested. <P>SOLUTION: A control circuit 12 shifts an internal state to a self erase/write mode or self burn-in mode, and outputs an address signal and a high-voltage control signal in each internal state. Accordingly, a write property and an erase property are investigated after write/erase operations are repeated a predetermined number of times, and a precise and severe self burn-in test of a nonvolatile semiconductor memory cell array 1 can be performed. In an erasable/rewritable nonvolatile memory 13, the number of repetition of erase/write operations when repeated, and test data etc. obtained when write operation is performed are stored. Accordingly, the number of repetition, test data, etc. can be rewritten, and a flexible test can be performed responding to a request for a burn-in test which complies with multi-valuing, or a burn-in test which classifies specifications separately depending on their ranks. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory self-erase / write device and a semiconductor memory self-burn-in test method.
[0002]
[Prior art]
Generally, a burn-in test is performed in order to strain an initial failure of a semiconductor memory chip within a short time (for example, see Patent Document 1). In the burn-in test, a read-write operation is repeatedly performed on the semiconductor memory chip by applying a higher voltage and temperature than normal operation to the semiconductor memory chip by a burn-in test device, and the semiconductor memory chip The test is performed under stress. By doing so, an initial defective chip can be eliminated.
[0003]
In order to test a large number of semiconductor memory chips at once, a self-burn-in circuit which is a simplified version of the burn-in test device is provided inside the memory chip, so that various control signals, addresses, test data and the like necessary for the burn-in test are provided. It is a general tendency to generate the inside of a chip.
[0004]
In the self-burn-in circuit for such a burn-in test, when the burn-in detecting section detects that a predetermined burn-in test condition is satisfied, a predetermined control signal, an address signal and a predetermined signal for performing the burn-in test are obtained. Test data is generated. Then, based on the control signal, the test data is read / written from / to a memory cell selected according to the address signal, and the burn-in test is performed.
[0005]
As described above, by incorporating the self-burn-in circuit inside the memory chip, the control signal, the address, the test data, and the like can be stored in a state where the semiconductor memory chip is connected to the burn-in test device as in a normal burn-in test. There is no need to supply the memory chip. Therefore, it is not necessary to provide a burn-in test board provided with a line for supplying the control signal, the address signal, the test data, and the like in the self-burn-in circuit, and the self-burn-in circuit can be simplified. Therefore, the limitation on the number of chips that can be tested at one time can be relaxed.
[0006]
[Patent Document 1]
JP-A-9-219099
[0007]
[Problems to be solved by the invention]
However, the conventional self-burn-in circuit has the following problems.
[0008]
That is, in the case of a burn-in test for a semiconductor memory such as a DRAM (Dynamic Random Access Memory) with a built-in capacitor or an SRAM (Static Random Access Memory) with a built-in latch circuit, a pure read / write is required. , It is only necessary to test the state of holding electric charge in the built-in capacitor and the state of holding the latch of the latch circuit.
[0009]
However, in the case of a flash memory which is a rewritable nonvolatile semiconductor memory, electrons are injected or extracted by a tunnel effect between a channel region and a floating gate through a tunnel oxide film. Since it is necessary to apply a program voltage (write voltage) and an erase voltage (erase voltage), the write characteristics and erase characteristics after repeating write / erase a predetermined number of times are examined, and the characteristic change when the device is used in accordance with the specification is examined. It is necessary to make predictions. Therefore, the test items are very severe.
[0010]
Further, when performing a burn-in test corresponding to the future multi-value, it is necessary to further test the writing characteristics and erasing characteristics severely. Therefore, in a test in which all lines are simply selected to check whether data is "1" or "0", or to check whether or not the data is the inverted data, a chip failure occurs. Good products cannot be excluded.
[0011]
In some cases, the specification of the access time is classified according to the rank (high-speed type, low-speed type) from the results of the write characteristics and the erase characteristics to obtain a good product. To cope with such a case, various types of test items and flexible tests are required.
[0012]
However, in the above-described conventional self-burn-in circuit, the test procedure, test data, and the like for each test item are preset and stored and fixed. Therefore, for a rewritable nonvolatile semiconductor memory such as a flash memory, a test item, a test procedure, and test data are changed according to a purpose, and a rank of a non-defective product is changed to provide a flexible burn-in. There is a problem that cannot be tested.
[0013]
Therefore, in order to cope with such a flexible burn-in test or a severe burn-in test, it is necessary to set and store a test procedure and test data for every test item in advance. There is a problem that storage capacity is required.
[0014]
An object of the present invention is to provide a self-erasing / writing device for a semiconductor memory capable of performing a severe and flexible burn-in test on a rewritable nonvolatile semiconductor memory, and a self-burn-in test for a semiconductor memory. It is to provide a method.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory self-erase / write device according to the present invention detects a semiconductor memory cell array in which semiconductor memory cells are arranged in a matrix and detects that a predetermined self-burn-in test condition is satisfied. Test information that includes a burn-in sensor that outputs a burn-in signal to the semiconductor memory cell array, a number of repetitions of the erase-write operation when the erase-write operation is performed on the semiconductor memory cell array, and test data written to the memory cells during the write operation. And a high-voltage control signal required for the erase / write operation based on the test information stored in the rewritable nonvolatile memory when the burn-in signal is input. And control signals including address signals A control unit for selecting a memory cell in an area corresponding to the address signal in the semiconductor memory cell array based on the control signal, and performing an erase / write operation based on the test data on the selected memory cell by the number of repetitions It has a self-erase / write operation unit for performing.
[0016]
According to the configuration, when the self-burn-in test condition is satisfied from the outside, the self-erase / write operation for the semiconductor memory cell array is automatically performed. Therefore, by reading the test data from each memory cell after the erase / write operation has been completed, it is possible to examine write characteristics and erase characteristics after repeated writing / erasing with respect to the semiconductor memory cell array. become. That is, it is possible to predict a change in characteristics when the semiconductor memory cell array is used according to specifications, and to perform an accurate and severe self-burn-in test on a rewritable nonvolatile semiconductor memory.
[0017]
In the self-erasing / writing device for a semiconductor memory according to one embodiment, the control section enables the internal state to transit from the self-erasing / writing mode to the self-burn-in mode. In the self-burn-in mode, a high-voltage control signal and an address signal required for a read operation on the semiconductor memory cell array after the erase / write operation are completed are output. The control signal is output.
[0018]
According to this embodiment, after the erase / write operation on the semiconductor memory cell array is completed, the read operation on the semiconductor memory cell array is automatically performed. Thus, the self-burn-in test for the rewritable nonvolatile semiconductor memory cell array is automatically and accurately performed.
[0019]
Further, in the semiconductor memory self-erase / write device according to one embodiment, the rewritable nonvolatile memory is used to control the stored test information by external control only when the self-burn-in test condition is not satisfied. It is rewritable based on information, addresses and test data.
[0020]
According to this embodiment, in the normal operation mode, by inputting control information, an address and test data to the semiconductor memory chip from the outside, the number of repetitions and the test stored in the rewritable nonvolatile memory can be improved. Test information including data and the like is rewritten based on the above-mentioned external control information, addresses, and test data. Therefore, by rewriting the test information in accordance with the burn-in test corresponding to the multi-value and the burn-in test in which the specifications are classified by rank, it is possible to perform a flexible test according to the purpose.
[0021]
Furthermore, by rewriting the test information in the rewritable nonvolatile memory for each test item, various tests can be realized with a small memory capacity.
[0022]
In one embodiment of the present invention, the semiconductor memory cell array is composed of rewritable nonvolatile memory cells, and the cell structure of the rewritable nonvolatile memory is changed to the cell of the semiconductor memory cell array. The structure is the same.
[0023]
According to this embodiment, it is possible to prevent the semiconductor memory chip manufacturing process from being complicated due to the provision of the rewritable nonvolatile memory.
[0024]
In addition, the self-burn-in test method for a semiconductor memory according to the present invention includes the steps of: erasing the erase-write operation when performing the erase-write operation on the semiconductor memory cell array; And test data including test data to be written to the memory. When a predetermined self-burn-in test condition is satisfied, a burn-in signal is generated. When the burn-in signal is generated, the test data is stored in the rewritable nonvolatile memory. On the basis of the test information, a control signal including a high voltage control signal and an address signal required for the erase / write operation is generated. Based on the control signal, a control signal for an area corresponding to the address signal in the semiconductor memory cell array is generated. Select a memory cell and select a memory cell Te done many times repeated above the erase-write operation according to the above test data, it is to read out the results of the above erase-write operation.
[0025]
According to the above configuration, if the self-burn-in test condition is satisfied from the outside, the self-burn-in test for checking the write characteristics and the erase characteristics after repeatedly writing / erasing the semiconductor memory cell array a plurality of times is automatically performed. Is executed. Therefore, it is possible to predict a change in characteristics when the semiconductor memory cell array is used in accordance with specifications, and to perform an accurate and severe self-burn-in test on a rewritable nonvolatile semiconductor memory.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram showing a configuration of a semiconductor memory self-erase / write device according to the present embodiment. This self-erasing / writing device can effectively perform a self-burn-in test on a rewritable nonvolatile semiconductor memory such as a flash memory.
[0027]
As shown in FIG. 1, the self-erase / write device of the present semiconductor memory is schematically composed of a memory cell array 1, a burn-in control unit 2, an address buffer 3, and a high voltage control circuit 4.
[0028]
The memory cell array 1 is configured such that rewritable nonvolatile semiconductor memory cells are arranged in a matrix and is an area for storing normal data and the like. The burn-in control unit 2 detects a state in which the external voltage has been boosted to a predetermined level or more, and outputs a high-voltage control signal and an address signal for the burn-in operation. The address buffer 3 buffers an address signal from the burn-in control unit 2 and outputs the buffered signal to the X decoder 5 and the Y decoder 6 of the memory cell array 1. In addition, the high voltage control circuit 4 responds to the high voltage control signal from the burn-in control unit 2 to control the memory cell array 1 via the X-decoder 5 and the Y-decoder 6 to perform a high-level operation necessary for an erase operation, a write operation, and a read operation. A voltage (for example, a negative voltage such as a write voltage of 10 V and an erase voltage of −8 V) is output.
[0029]
That is, the X decoder 5 decodes an address signal input from the address buffer 3, selects a word line of the memory cell array 1, and outputs an output from the high voltage control circuit 4 to the selected word line. The Y decoder 6 decodes the address signal to select a bit line of the memory cell array 1 and outputs an output from the high voltage control circuit 4 to the selected bit line. As described above, in this embodiment, the address buffer 3, the high voltage control circuit 4, the X decoder 5, and the Y decoder 6 constitute the self-erasing / writing operation section.
[0030]
Although not shown, the Y decoder 6 is provided with a sense amplifier connected to a bit line of the memory cell array 1, and data (data) read from a memory cell of the memory cell array 1 by this sense amplifier is provided. Voltage). The data read from this memory cell is compared by a comparator (not shown) with test data (voltage) stored in the rewritable nonvolatile memory 13 constituting the burn-in control unit 2. , The quality of the memory cell array 1 is determined. Then, the result of the pass / fail judgment is output to the outside of the semiconductor memory chip. Alternatively, the data read from the memory cell may be directly output to the outside of the semiconductor memory chip, and the quality of the memory cell array 1 may be determined by an external tester.
[0031]
Next, the configuration of the burn-in control unit 2 will be described. The burn-in control unit 2 is roughly composed of a burn-in sensor 11 as the burn-in sensor, a control circuit 12 as the control unit, and a rewritable nonvolatile memory 13.
[0032]
The burn-in sensor 11 detects that the power supply voltage Vcc supplied from outside the semiconductor memory chip is equal to or higher than the predetermined level, determines that the self-burn-in test condition is satisfied, and Output a signal. In the rewritable nonvolatile memory 13, the number of repetitions of the erase / write operation for alternately performing the erase operation and the write operation on the memory cell array 1 and the test data written to the memory cells of the memory cell array 1 during the write operation are stored. And other test information are stored. Only when the self-burn-in test condition is not satisfied, that is, only in the normal operation mode, when the control information, the address, the test data, and the like are externally provided (input) to the semiconductor memory chip, the stored data is stored. The repetition count and test data can be rewritten according to the external control information, address, test data, and the like. When the burn-in signal is input from the burn-in sensor 11, the control circuit 12 selects a selected memory on the memory cell array 1 according to the number of repetitions read from the rewritable nonvolatile memory 13 and the test data. A control signal including the address signal designating a cell and a high voltage control signal is output.
[0033]
Next, the cell burn-in test executed by the burn-in control unit 2 having the above configuration will be described in detail. FIG. 2 is a flowchart of the cell burn-in processing operation.
[0034]
In step S1, the power supply voltage Vcc supplied from the outside is acquired by the burn-in sensor 11. In step S2, the burn-in sensor 11 determines whether or not the acquired power supply voltage Vcc is equal to or higher than a predetermined level, thereby determining whether or not the burn-in mode for the burn-in operation. As a result, if the mode is the burn-in mode, the process proceeds to step S3. Otherwise, the mode is determined to be the normal operation mode, and the operation shifts to the normal operation. Since the normal operation is not directly related to the present invention, the description is omitted.
[0035]
In step S3, the operation related to the burn-in is started. First, the burn-in sensor 11 outputs a burn-in signal to the control circuit 12. In step S4, the internal state is changed by the control circuit 12 to enter the self-erase / write mode. In step S5, the control circuit 12 reads, from the rewritable nonvolatile memory 13, the number of repetitions of the erase / write operation and test information such as test data written to the memory cells at the time of the write operation.
[0036]
In step S6, the control circuit 12 performs a full chip erase operation. That is, based on the read test information, a high-voltage control signal and an address signal for performing a full-chip erase operation are generated, and output to the address buffer 3 and the high-voltage control circuit 4. Then, the full chip erase operation is executed by the address buffer 3 and the high voltage control circuit 4 as described above. In general, batch erasing is performed in a flash memory or the like, and erasing is performed in block units in the above-described full chip erasing. In step S7, a write operation is performed by the control circuit 12. That is, a high-voltage control signal and an address signal for writing the test data read in step S4 to the memory cell at the corresponding address are generated and output to the address buffer 3 and the high-voltage control circuit 4. Then, the write operation is executed by the address buffer 3 and the high voltage control circuit 4. After that, the number of erase / write operations is counted.
[0037]
In step S8, the control circuit 12 determines whether or not the number of erase / write operations counted is equal to or greater than the number of read repetitions. Thus, it is determined whether or not to end the self-erase / write mode. If the operation is completed, the process proceeds to step S9. If not, the process returns to step S6 to shift to the next full chip erase operation. Thereafter, the erase operation and the write operation are alternately repeated. If it is determined in step S8 that the erase / write operation has been completed a predetermined number of times, the process proceeds to step S9.
[0038]
In step S9, the control circuit 12 changes the internal state from the self-erase / write mode to the self-burn-in mode. In step S10, the control circuit 12 performs a self-burn-in operation. That is, a high-voltage control signal and an address signal for reading the test data written in the memory cell are generated and output to the address buffer 3 and the high-voltage control circuit 4. Then, the read operation is executed by the address buffer 3 and the high voltage control circuit 4. Here, the power supply voltage Vcc and the temperature in the self burn-in mode are the same as those in the self erase / write mode. However, in the self-erase / write mode, test data (write data) is erased / written to the memory cells, whereas in the self-burn-in mode, the self-burn-in mode in which write data is read from the memory cells. The action is performed. After that, the cell burn-in processing operation ends.
[0039]
As described above, in the present embodiment, the burn-in control unit 2 causes the internal state to transit between the self-erase / write mode and the self-burn-in mode, and in each state, selects the selected memory cell on the memory cell array 1. A control circuit 12 for outputting a designated address signal and a high voltage control signal is provided. Therefore, by examining the write characteristics and the erase characteristics after writing / erasing is repeated a predetermined number of times with respect to the memory cell, it is possible to predict a change in characteristics when the memory cell array 1 is used in accordance with the specifications. That is, according to the present embodiment, an accurate and severe self-burn-in test can be performed on the memory cell array 1 including rewritable nonvolatile semiconductor memory cells.
[0040]
Further, the burn-in control unit 2 is provided with a rewritable nonvolatile memory 13 in which test information such as the number of repetitions of the erase / write operation for the memory cell array 1 and test data to be written in the memory cell during the write operation is stored. ing. As described above, since the repetition count and test data are stored in the electrically erasable and rewritable nonvolatile memory, various test information including the repetition count and test data can be rewritten in the normal operation mode. Can be. Therefore, by rewriting the test data in accordance with the burn-in test corresponding to the multi-value and the burn-in test in which the specifications are classified according to the rank, it is possible to perform a flexible test according to the purpose.
[0041]
Further, in that case, test data in the rewritable nonvolatile memory 13 may be rewritten for each test item, and various tests can be realized with a small memory capacity.
[0042]
Further, the memory cell structure of the rewritable nonvolatile memory 13 can be the same as the cell structure of the memory cell array 1. In this case, it is possible to prevent the memory chip manufacturing process from becoming complicated due to the provision of the rewritable nonvolatile memory 13. Further, it can be used as a rescue area for relieving a line defect that often occurs in a flash memory. For example, a defective line storage unit for storing the address of the defective line is provided in an external tester or inside the chip. After completion of the burn-in test, the test data stored in the rewritable nonvolatile memory 13 is erased, and the erased test data storage area is used as a repair area for the defective line based on the address of the defective line. is there.
[0043]
The present embodiment can be applied to a rewritable nonvolatile memory such as the flash memory and the ferroelectric memory (FeRAM). Of course, it is needless to say that the present invention can be applied to the above-mentioned DRAM and SRAM.
[0044]
【The invention's effect】
As is apparent from the above, the semiconductor memory self-erase / write device of the present invention stores test information including the number of repetitions of the erase / write operation and test data at the time of the write operation in the rewritable nonvolatile memory, When the burn-in sensor detects that the self-burn-in test condition is satisfied, the control unit outputs a control signal required for the erase / write operation based on the test information of the rewritable nonvolatile memory, and performs a self-erase / write operation. The operation unit performs the erase / write operation on the selected memory cell in the semiconductor memory cell array according to the address signal of the control signal as many times as the number of repetitions. Semiconductor memory It is possible to perform the self-erase-write test for Ruarei.
[0045]
That is, if the test data is read from each memory cell after the erase / write operation has been completed, it is possible to examine the write characteristics and the erase characteristics after repeatedly writing / erasing the semiconductor memory cell array, It is possible to predict a change in characteristics when the semiconductor memory cell array is used according to specifications. Therefore, an accurate and severe self-burn-in test can be performed on the rewritable nonvolatile semiconductor memory cell array, and the test process can be simplified. Further, the number of semiconductor memory chips that can be tested at one time can be increased.
[0046]
Further, according to the self-burn-in test method for a semiconductor memory of the present invention, test information including the number of repetitions of the erase / write operation and test data at the time of the write operation is stored in the rewritable nonvolatile memory, and the self-burn-in test condition Then, a control signal required for the erase / write operation is generated based on the test information of the rewritable nonvolatile memory, and the selected memory cell in the semiconductor memory cell array corresponding to the address signal of the control signal is erased.・ Since the write operation is repeated the number of times and the result of the erase / write operation is read, the self-burn-in test is automatically performed on the semiconductor memory cell array if the self-burn-in test condition is externally satisfied. be able to.
[0047]
Therefore, it is possible to predict a change in characteristics when the semiconductor memory cell array is used in accordance with specifications, and to perform an accurate and severe self-burn-in test on a rewritable nonvolatile semiconductor memory cell array.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a self-erase write circuit of a semiconductor memory according to the present invention.
FIG. 2 is a flowchart of a cell burn-in processing operation executed by a burn-in control unit in FIG. 1;
[Explanation of symbols]
1. Memory cell array,
2. Burn-in control unit
3 ... address buffer,
4. High voltage control circuit
5 ... X decoder,
6 ... Y decoder,
11 ... burn-in detector,
12 ... Control circuit,
13: Rewritable nonvolatile memory.

Claims (5)

A semiconductor memory cell array in which semiconductor memory cells are arranged in a matrix,
A burn-in sensor that detects that a predetermined self-burn-in test condition is satisfied and outputs a burn-in signal;
A test including the number of repetitions of the erase / write operation when performing the erase / write operation in which the erase operation and the write operation for the semiconductor memory cell array are alternately repeated, and test data written to the memory cell at the time of the write operation A rewritable nonvolatile memory for storing information;
When the burn-in signal is input, a control for outputting a control signal including a high-voltage control signal and an address signal required for the erase / write operation based on the test information stored in the rewritable nonvolatile memory. Department and
A memory cell in an area corresponding to the address signal in the semiconductor memory cell array is selected based on the control signal, and a self-erase operation for performing the erase / write operation by the test data for the selected memory cell by the repetition number is performed. A self-erasing write device for a semiconductor memory, comprising a write operation section. 2. The self-erase write device for a semiconductor memory according to claim 1,
The control unit is capable of transitioning an internal state from a self-erase / write mode to a self-burn-in mode. In the self-erase / write mode, a control including a high-voltage control signal and an address signal necessary for the erase / write operation is performed. And outputting a control signal including a high voltage control signal and an address signal necessary for a read operation on the semiconductor memory cell array after the erase / write operation is completed in the self burn-in mode. Characteristic self-erasing and writing device for semiconductor memory. 3. The self-erasing write device for a semiconductor memory according to claim 2,
The rewritable nonvolatile memory can rewrite the stored test information based on external control information, addresses and test data only when the self-burn-in test condition is not satisfied. A self-erasing write device for a semiconductor memory. 2. The self-erase write device for a semiconductor memory according to claim 1,
The semiconductor memory cells constituting the semiconductor memory cell array are rewritable nonvolatile memory cells,
The cell structure of the rewritable nonvolatile memory is the same as the cell structure of the semiconductor memory cell array. In the rewritable nonvolatile memory, the number of repetitions of the erase / write operation at the time of performing the erase / write operation in which the erase operation and the write operation for the semiconductor memory cell array are alternately repeated, Store test information including test data to be written,
When a predetermined self-burn-in test condition is satisfied, a burn-in signal is generated,
When the burn-in signal is generated, a control signal including a high-voltage control signal and an address signal necessary for the erase / write operation is generated based on the test information stored in the rewritable nonvolatile memory,
Based on the control signal, select a memory cell in an area corresponding to the address signal in the semiconductor memory cell array, perform an erase / write operation by the test data on the selected memory cell by the number of repetitions,
A self-burn-in test method for a semiconductor memory, wherein a result of the erase / write operation is read.

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