KR20100013954A

KR20100013954A - Method of testing a semiconductor memory device

Info

Publication number: KR20100013954A
Application number: KR1020080075718A
Authority: KR
Inventors: 최원열
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-08-01
Filing date: 2008-08-01
Publication date: 2010-02-10

Abstract

PURPOSE: A method for testing a semiconductor memory device is provided to improve the screening method of a bit line stress measurement test by using an erase voltage for erasing operation of the semiconductor memory device. CONSTITUTION: The word line of a memory cell array(100), a source selection line and a drain selection line are floated. An erase voltage is applied to the memory cell array. A first voltage is transmitted to bit lines(BLe, BLo) of the memory cell array. The erase voltage is applied to a common source line(CSL). A second voltage is applied to a selected bit line from the bit lines. The first voltage is discharged. A voltage difference between the bit line and the common source line is measured. A voltage difference between non-selected bit lines is measured.

Description

Method of testing a semiconductor memory device

The present invention relates to a test method of a semiconductor memory device, and more particularly, to a test method of a semiconductor memory device capable of testing the leakage current of the bit line using a high voltage.

The flash memory device of the semiconductor memory device is a nonvolatile memory that can store data when the power is cut off. The flash memory device can be programmed and erased electrically and refreshes data at regular intervals. refresh) A device that does not require a function. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of erasing data from a memory. Such flash memory devices are largely divided into NOR and NAND flash according to the cell structure and operating conditions. Noah-type flash memory is a source of each memory cell transistor is connected to the ground terminal (VSS) can be programmed and erased to any address, it is mainly used in applications requiring high-speed operation. NAND flash memory, on the other hand, is a structure in which a plurality of memory cell transistors are connected in series to form a string, and a string is connected to a source and a drain, and is mainly used in highly integrated data storage applications.

A method of measuring stress applied to bit lines constituting a memory cell array in the test mode of the flash memory device described above is as follows.

1 is a circuit diagram illustrating a bit line stress measuring method of a flash memory device according to the prior art.

Referring to FIG. 1, a bias voltage VIRPWR may be set by using the bit line selector 21 of the page buffer 20 to measure the stress of the bit lines BLe and BLo connected to the page buffer 20. Applied to a bit line (e.g., an odd bit line BLo). At this time, the other bit line (for example, the even bit line BLe) is discharged to the OV through the register unit 23. Thereafter, a test voltage (about 3.8V) is applied to the common source line of the memory cell array 10.

Subsequently, the voltage difference between the even bit line BLe and the common source line CSL and the voltage difference between the even bit line BLe and the odd bit line BLo is measured using a probe to determine the bit lines BLe and BLo. The bit line leakage current caused by problems such as the bridge phenomenon, the junction bridge phenomenon, and the open failure of the memory cell can be found.

However, the test method described above does not apply the bias voltage VIRPWR to a predetermined voltage or more. This is because the general transistors formed in the peripheral circuit region are formed as low voltage transistors, and when the high voltage is applied, the degradation of the gate oxide film and the degeneration of the junction are caused. This is because a date phenomenon occurs. When the test is performed using the bias voltage VIRPWR below the constant voltage, the measured voltage is small, thereby reducing the reliability of the data and increasing the test time.

The technical problem to be achieved by the present invention is to precharge any one of the pair of bit line to the erase voltage level by using the erase voltage used in the erase operation of the semiconductor memory device to measure and compare with the other bit line, A semiconductor capable of protecting the low voltage transistors in the peripheral circuit area while maximizing the screening method of the bit line stress measurement test and reducing the test time by applying an erase voltage to the common source line and measuring it compared with the other bit line. The present invention provides a test method of a memory device.

According to an embodiment of the present disclosure, a method of testing a semiconductor memory device may include plotting a word line, a source select line, and a drain select line of a memory cell array, and applying an erase voltage to the memory cell array to provide a memory cell array. Transmitting the first voltage to bit lines, applying the erase voltage to a common source line, and applying the second voltage to a selected bit line among the bit lines to discharge the first voltage. And measuring a voltage difference between the common source line and the selected bit line, and measuring a voltage difference between the selected bit line and an unselected bit line among the bit lines.

The first voltage is a voltage obtained by subtracting the erase voltage by a forward bias value between a well of a memory cell array and a junction region to which the bit lines are connected.

In the applying of the second voltage to the selected one of the bit lines, the second voltage is applied using a page buffer connected to the memory cell array.

The page buffer transfers the ground voltage to the selected bit line using the bias voltage of the ground level as the second voltage.

According to an embodiment of the present invention, by using an erase voltage used in an erase operation of a semiconductor memory device, precharge one bit line of a pair of bit lines to an erase voltage level and compare the measured bit line with another bit line. By applying an erase voltage to the common source line and measuring it in comparison with the other bit line, the screen method of the bit line stress measurement test can be maximized and the test time can be reduced while protecting the low voltage transistors in the peripheral circuit area. .

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a circuit diagram of a device for explaining a test method of a flash memory device according to an embodiment of the present invention.

3 is a waveform diagram illustrating potentials of nodes for explaining a test method of a flash memory device according to an exemplary embodiment.

Table 1 is a table showing voltages applied during a test operation of a flash memory device according to an exemplary embodiment.

Selection block Unselected block Select wordline 0 V Floating Unselected wordlines 0 V Floating GDSL 0 V 0 V GSSL 0 V 0 V DSL Floating Floating SSL Floating Floating CSL Floating Floating TP-Well Clear voltage (19V) Clear voltage (19V) Select Bitline (BLo) Floating (close to 19V) Floating (close to 19V) Unselected Bitline (BLe) Floating Floating Bias Voltage (VIRPWR) Vcc Vcc DISCHe 0 V 0 V DISCHo 0 V 0 V BSLe 0 V 0 V BSLo 0 V 0 V

A test method of a flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2, 3, and Table 1 as follows.

Preferably, the test operation of the present invention is performed using an erase operation of the flash memory device.

First, an erase voltage of about 19 V is applied to the triple well TP-Well of the memory cell array 100 during an erase operation of the flash memory device.

In the erase operation, all of the drain select transistors, the source select transistors, and the word lines of the unselected memory cell blocks except for the word lines of the selected memory cell block are in a floating state. In the present invention, all memory cell blocks are controlled to an unselected state during an erase operation. As a result, the drain select transistor, the source select transistor, and the word lines of the memory cell block are all in a floating state.

When the erase voltage is applied while all the memory cell blocks are unselected, the bit lines BLe and BLo are raised to a voltage adjacent to the erase voltage (drop by a net bias at the erase voltage). The erase voltage applied to the triple well (P type) is applied to the bit line through the junction region (N type), and the voltage dropped by the forward bias of the PN junction is transferred to the bit line. In this case, a voltage equal to the erase voltage is applied to the common source line CSL.

If all memory cell blocks are not selected during the erase operation, only the erase voltage is transferred to the bit line, and electrical damage does not occur to the memory cell.

Thereafter, during the erase voltage discharge operation, the voltage of one bit line (eg, the odd bit line BLo) of the bit lines BLe and BLo is changed through the bit line selector 210 of the page buffer 200. Discharge. This applies the odd discharge signal DISCHo to a high level so that the bias voltage of the ground voltage OV is applied to the odd bit line BLo, thereby discharging the odd bit line BLo to the ground voltage OV.

As a result, a high voltage erase voltage is applied to the common source line CSL, a voltage dropped by a forward bias than the erase voltage is applied to the even bit line BLe, and the odd bit line BLO is applied to the ground voltage OV. Discharged.

Thereafter, the voltage difference between the common source line CSL and the odd bit line BLo is measured using a probe, and the voltage difference between the even bit line BLe and the odd bit line BLo is measured. The leakage current can be tested. In the test operation, the voltage difference is generated by the erase voltage to detect the presence of the correct leakage current, and the test time can be reduced by using the high voltage. In addition, since the erase voltage is not applied to the peripheral circuit region, damage to the low voltage transistor can be prevented.

When the erase operation is completed, the charge precharged in the triple well TP-Well is discharged. At this time, the bias voltage VIRPWR is set to the ground voltage Vss, and the charge is discharged through the bit lines BLe and BLo.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

100: memory cell array 200: page buffer

210: bit line selection unit 220: register unit

Claims

Plotting a word line, a source select line, and a drain select line of the memory cell array;

Applying a erase voltage to the memory cell array to transfer a first voltage to bit lines of the memory cell array;

Applying the erase voltage to a common source line;

Discharging the first voltage by applying a second voltage to a selected one of the bit lines; And

Measuring a voltage difference between the common source line and the selected bit line, and measuring a voltage difference between the selected bit line and an unselected bit line among the bit lines.

The method of claim 1,

And the first voltage is a voltage equal to a difference in a forward bias value between a well of a memory cell array and a junction region to which the bit lines are connected at the erase voltage.

The method of claim 1,

Applying a second voltage to the selected bit line of the bit lines

And applying the second voltage using a page buffer connected to the memory cell array.

The method of claim 3, wherein

And the page buffer transmits the bias voltage of the ground level to the selected bit line using the bias voltage of the ground level as the second voltage.

A leakage current test method of a memory cell array including an even and odd bit lines,

Precharging the even and odd bit lines to a first high voltage by applying an erase voltage to the memory cell array;

Applying a second high voltage of the erase voltage level to a common source line of the memory cell array;

Discharging any one of the even and odd bit lines to a ground level; And

Measuring a voltage difference between the common source line and the even bit line, and measuring a voltage difference between the even and odd bit lines.