KR20090107769A - Semiconductor device and burn-in test method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device and a burn-in test method thereof are provided to steadily remove the micro bridge generated among the wirings while minimizing the degradation of the junction area or the gate insulating layer. CONSTITUTION: A burn-in test method of a semiconductor device is as follows. The acceleration voltage is applied to one wiring between the pair of wirings for testing with burn in. The well(201) is floated or the well voltage which has identical magnitude with the acceleration voltage is applied to the well.

Description

Semiconductor device and its burn-in test method {SEMICONDUCTOR DEVICE AND BURN-IN TEST METHOD THEREOF}

The present invention relates to a test method of a semiconductor device, in particular a test method of a nonvolatile memory device, and more particularly a burn-in test method of a NAND flash memory device.

Semiconductor devices must frequently detect and remove defects that may occur from manufacture to disposal in order to reduce defects and improve yield. To do this, a system must be built to effectively detect and eliminate the defects occurring initially.

In order to remove the initial failure, a test is performed to detect the initial failure by operating the semiconductor device in a separate acceleration environment. One such test is the burn-in test. Here, the acceleration environment is determined by the power supply voltage, temperature and test time. The proper acceleration environment is closely related to the maturity of the process for producing semiconductor devices.

In general, NAND flash memory devices of semiconductor devices perform burn-in tests to remove micro bridges between bit lines. The burn-in test method proceeds by applying burn-in stress, that is, an acceleration voltage to the bit line. At this time, the acceleration voltage is applied to a voltage relatively higher than the voltage applied in the normal operation.

1 is a view illustrating a burn-in test method of a NAND flash memory device according to the related art, and FIG. 2 is a cross-sectional view illustrating a portion of a memory cell array.

The burn-in test method according to the related art will be described with reference to FIGS. 1 and 2 as follows.

DISCHe DISCHo BSLe BSLo VIRPWR L ('0') H ('1') H ('1') L ('0') VSS

First, as shown in Table 1, a corresponding bias is applied to the transistors N1 to N4, respectively. That is, a logic low L corresponding to the ground voltage VSS is applied to the gates of the first and third transistors N1 and N3, and a power supply voltage is applied to the gates of the second and fourth transistors N2 and N4. A logic high (H) corresponding to VDD) is applied. In addition, an acceleration voltage Vstr is applied to the node SO.

Under such a bias condition, the acceleration voltage Vstr applied to the node SO is transferred to the bit line BLe, and the ground voltage VSS is transferred to the bit line Blo. As a result, a voltage difference between the acceleration voltage Vstr and the ground voltage VSS is generated between the neighboring bit lines BLe and BLo, so that the micro bridge formed between the bit lines BLe and BLo is broken.

However, the burn-in test method according to the related art causes a problem in that the junction region (drain region) 102 of the drain select transistor DST is deteriorated. This is because the acceleration voltage Vstr is transferred to the junction region 102 of the drain select transistor DST through the drain contact plug DCT connected to the bit line BLe during the burn-in test operation.

In a test mode including a burn-in test, a ground voltage VSS corresponding to 0V is applied to the well 101 in the same manner as the program and erase operations. In this state, when a relatively high voltage accelerating voltage Vstr is applied to the junction region 102 of the drain select transistor DST through the bit line BLe, a high voltage between the junction region 102 and the well 101 is applied. The problem arises that the junction region 102 is deteriorated by the difference.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and is a burn-in in a semiconductor device employing a burn-in test to remove microbridges between neighboring wirings (bit lines, word lines). An object of the present invention is to provide a burn-in test method capable of preventing deterioration of a device due to an acceleration voltage applied during a test operation, and an apparatus for implementing the same.

According to an aspect of the present invention, there is provided a burn-in test for a semiconductor device including a well, a plurality of junction regions formed in the well, and a plurality of wirings connected to the plurality of junction regions, respectively. A semiconductor, comprising: applying an acceleration voltage to any one of a pair of wirings to be burn-in tested and floating the well or applying a well voltage having the same voltage magnitude as the acceleration voltage to the wells Provides a burn-in test method for the device.

According to another aspect of the present invention, there is provided a semiconductor device including a well formed in a substrate, a plurality of gates formed on the substrate, and a plurality of wirings connected to the plurality of gates, respectively. In the burn-in test method, an acceleration voltage is applied to any one of a pair of wirings to be burn-in tested, and the well is floated or a well having a voltage magnitude equal to the acceleration voltage in the well. A burn-in test method of a semiconductor device applying a voltage is provided.

In addition, the present invention according to another aspect for achieving the above object is a junction of a plurality of strings comprising a plurality of memory cells sharing a well and connected in series with each other, and a first selection transistor each configured in the string In a burn-in test method of a semiconductor device including a plurality of bit lines connected to an area, an acceleration voltage is applied to one of the bit lines of a pair of bit lines to be burn-in tested, and the well is Provided is a burn-in test method for a semiconductor device that floats or applies a well voltage having a voltage magnitude equal to the acceleration voltage to the well.

In addition, according to another aspect of the present invention, a plurality of strings including a plurality of memory cells sharing a well and connected in series between first and second selection transistors, A burn-in test method of a semiconductor device including a plurality of word lines connected to a memory cell gate, respectively, the method comprising: accelerating to any one of a pair of word lines to be burn-in tested among the plurality of word lines Provided is a burn-in test method for a semiconductor device that applies a voltage, floats the well, or applies a well voltage having a voltage magnitude equal to the acceleration voltage to the well.

In addition, the present invention according to another aspect for achieving the above object is a plurality of strings including a plurality of memory cells sharing a well and connected in series between the first and second select transistor, and in the string A semiconductor device comprising a plurality of bit lines connected to a junction region of a first selection transistor, each configured, comprising: an operation mode signal generator configured to generate an operation mode signal for determining a normal operation mode and a burn-in test operation mode; A page buffer for transferring an acceleration voltage to any one of a pair of bit lines to be burn-in tested in the burn-in test operation mode and a first well voltage required in the normal operation mode A first well voltage generator configured to generate a second well voltage having the same magnitude as the acceleration voltage, and the burn-in test When the operation mode in response to the operation mode wherein the signal passes the second well voltage of the wells, or by preventing the delivery wells provides a semiconductor device including the selection of the floating well.

In addition, according to another aspect of the present invention, a plurality of strings including a plurality of memory cells sharing a well and connected in series between first and second selection transistors, A semiconductor device including a plurality of word lines connected to a memory cell gate, the semiconductor device comprising: an operation mode signal generator configured to generate an operation mode signal for determining a normal operation mode and a burn-in test operation mode, and the burn-in test In an operation mode, a page buffer for transferring an acceleration voltage to any one of a pair of word lines to be burn-in tested, and a first well voltage generation for generating a first well voltage required in the normal operation mode. And a second well voltage generator configured to generate a second well voltage having the same magnitude as the acceleration voltage, and the operating mode scene during the burn-in test operation mode. In response to the block of the second well voltage delivered or the wells, the wells transmission provides a semiconductor device including the selection of the floating well.

According to the present invention having the above-described configuration, in order to prevent the junction region or the gate insulating film (tunnel insulating film) from deteriorating due to the voltage difference between the wiring and the well during the burn-in test operation, the wells may be floated or the acceleration voltage may be reduced. By applying the corresponding well voltage to the well, it is possible to stably remove the microbridges generated between the wirings while minimizing deterioration of the junction region or the gate insulating film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals (or reference numerals) throughout the specification represent the same components.

Example 1

3 is a diagram for describing a burn-in test method of a semiconductor device according to example embodiment of the present invention.

Referring to FIG. 3, in the burn-in test method of the semiconductor device according to Embodiment 1 of the present invention, the semiconductor device includes a well 201 and a plurality of junction regions 202-0 through 202 formed in the well 201. -3) and a plurality of wirings ML0 to ML3 connected to the junction regions 202-0 to 202-3, respectively. Here, the number of junction regions 202-0 to 202-3 and the wirings ML0 to ML3 is not limited. In addition, the wirings ML0 to ML3 extend in the direction parallel to each other on the same layer.

Hereinafter, the burn-in test method of the semiconductor device according to Embodiment 1 of the present invention will be described.

An acceleration voltage Vstr is applied to any one of a pair of wirings (for example, ML0 and ML1, ML2 and ML3) to be burn-in test among the wirings ML0 to ML3 to cause a voltage difference between the wirings. Then, the well 201 is floated or a well voltage Vwell corresponding to the acceleration voltage Vstr is applied through the well pick-up region 203. In this case, the well voltage Vwell is determined within a range capable of minimizing degradation of the junction region due to the voltage difference between the junction region and the well 201. Preferably it has the same voltage magnitude as the acceleration voltage (Vstr). In addition, the well 201 may be floated or the well voltage Vwell may be applied before, after, or simultaneously with the acceleration voltage Vstr.

For example, when the pair of wirings to be burn-in tested among the wirings ML0 to ML3 are 'ML0' and 'ML1', an acceleration voltage Vstr is applied to 'ML0', and 'ML1' is an acceleration voltage ( A voltage lower than Vstr) is applied. Here, the acceleration voltage Vstr is 3 to 10V, and a voltage lower than the acceleration voltage Vstr may be a ground voltage VSS corresponding to 0V. Then, the well 201 is floated or the same well voltage Vwell as the acceleration voltage Vstr is applied through the well pick-up region 203.

As described above, the burn-in test method of the semiconductor device according to the first embodiment of the present invention floats the wells or prevents the junction region from deteriorating due to the voltage difference between the wiring and the well during the test operation. The well voltage is applied to the well. This makes it possible to stably remove the microbridges generated between the wirings while minimizing the deterioration of the junction region.

Example 2

FIG. 4 is a diagram illustrating a burn-in test method of a semiconductor device according to example embodiment of the present invention.

Referring to FIG. 4, in the burn-in test method of the semiconductor device according to Embodiment 2 of the present disclosure, the semiconductor device may include a well 301 formed in the substrate 300 and a plurality of gates formed on the substrate 300. 304-0 to 304-3 and a plurality of wirings ML0 to ML3 connected to the gates 304-0 to 304-3, respectively. Here, the number of gates 304-0 to 304-3 and the wirings ML0 to ML3 is not limited. In addition, the gates 304-0 to 304-3 may be gates for transistors or gates for nonvolatile memory cells (including floating gates and control gates). In addition, the wirings ML0 to ML3 are formed in a structure extended in parallel with each other on the same layer.

The burn-in test method of the semiconductor device according to the second embodiment of the present invention having this structure proceeds in the same manner as in the burn-in test method according to the first embodiment of the present invention.

An acceleration voltage Vstr is applied to any one of a pair of wirings (for example, ML0 and ML1, ML2 and ML3) to be burn-in test among the wirings ML0 to ML3 to cause a voltage difference between the wirings. Then, the well 201 is floated or a well voltage Vwell corresponding to the acceleration voltage Vstr is applied through the well pick-up region 203. At this time, the well voltage Vwell is determined within a range capable of minimizing degradation of the gate insulating film 302 due to the voltage difference between the gates 304-0 to 304-3 and the well 201. Preferably it has the same voltage magnitude as the acceleration voltage (Vstr). In addition, the well 201 may be floated or the well voltage Vwell may be applied before, after, or simultaneously with the acceleration voltage Vstr.

As described above, the burn-in test method of the semiconductor device according to the second exemplary embodiment of the present invention may float a well during a test operation, or apply a well voltage corresponding to an acceleration voltage to the well. This can prevent the gate insulating film (or the tunnel insulating film) 302 from deteriorating due to the voltage difference between the wiring and the well during the test operation. Here, deterioration of the gate insulating film 302 means that electrons are trapped in the gate insulating film 302 due to the voltage difference between the wiring and the well by the acceleration voltage Vstr, thereby deteriorating the operation reliability of the device. . For example, in the case of a transistor, the threshold voltage is changed, and in the case of a nonvolatile memory cell, uniformity of the threshold voltage cannot be secured during E / W cycling (Erase / Write cycling) operation.

Example 3

FIG. 5 is a diagram for describing a burn-in test method of a semiconductor device according to example 3 of the present disclosure.

Referring to FIG. 5, in the burn-in test method of the semiconductor device according to Embodiment 3 of the present disclosure, the semiconductor device is a nonvolatile memory device including the configuration of FIG. 1. That is, one well 401 is shared in common and is connected in series between the drain select transistor DST (hereinafter referred to as a first select transistor) and the source select transistor SST (hereinafter referred to as a second select transistor). A junction region of a plurality of strings ST (see FIG. 1) including a plurality of connected memory cells M0 to Mn (where n is a natural number) and a first selection transistor DST respectively configured in the string ST. And a plurality of bit lines BLe and BLo respectively connected to 402. Here, the number of memory cells M0 to Mn and the bit lines BLe and BLo is not limited.

Hereinafter, the burn-in test method of the semiconductor device according to Embodiment 3 of the present invention will be described.

The burn-in test method according to Example 3 of the present invention proceeds in the same manner as in Example 1 of the present invention. For example, an acceleration voltage Vstr is applied to one of the pair of bit lines BLe and BLo to be burn-in test to cause a voltage difference between the bit lines BLe and BLo. Then, the well 401 is floated, or a well voltage Vwell having the same voltage magnitude as the acceleration voltage Vstr is applied through the well pick-up region 403 to thereby separate the voltage difference between the well 401 and the bit line. Minimize. At this time, the ground voltage is applied to the bit line to which the acceleration voltage Vstr is not applied.

As described above, the burn-in test method of the semiconductor device according to the third exemplary embodiment of the present invention may float the well or prevent the junction region from deteriorating due to the voltage difference between the bit line and the well during the test operation. The corresponding well voltage is applied to the well. As a result, the microbridges generated between the bit lines can be removed while minimizing deterioration of the junction region.

Example 4

FIG. 6 is a diagram for describing a burn-in test method of a semiconductor device according to example 4 of the present disclosure.

Referring to FIG. 6, in the burn-in test method of the semiconductor device according to Embodiment 4 of the present disclosure, the semiconductor device is a nonvolatile memory device including the configuration of FIG. 1 as in Embodiment 3. That is, one well 501 is shared in common and includes a plurality of memory cells M0 to Mn (where n is a natural number) connected in series between the first and second selection transistors DST and SST. A plurality of strings ST (see FIG. 1) and a plurality of word lines WL0 to WLn (where n is a natural number) connected to the gates 508 of the memory cells M0 to Mn, respectively. Here, the number of memory cells M0 to Mn and word lines WL0 to WLn is not limited. The memory cell gate 508 also includes a tunnel insulating film 504, a floating gate 505, a dielectric film 506, and a control gate 507.

Hereinafter, the burn-in test method of the semiconductor device according to Embodiment 4 of the present invention will be described.

The burn-in test method according to Example 4 of the present invention proceeds in the same manner as in Example 2 of the present invention. For example, the voltage difference between the word lines WL0 and WL1 is applied by applying an acceleration voltage Vstr to any one of a pair of word lines (for example, WLO and WL1) to be burned-in among the word lines WL0 to WLn. Cause. In addition, the well 501 may be floated, or a well voltage Vwell having a voltage magnitude equal to the acceleration voltage Vstr may be applied through the well pick-up region 503, so that the well 501 and the corresponding memory cell gate ( 508) Minimize the voltage difference between them. In this case, a ground voltage is applied to a word line to which the acceleration voltage Vstr is not applied.

As described above, the burn-in test method of the semiconductor device according to the fourth exemplary embodiment of the present invention may float the wells or prevent the tunnel insulating film from deteriorating due to the voltage difference between the memory cell gate and the wells. The well voltage is applied to the well. As a result, the microbridges generated between the word lines can be removed while minimizing deterioration of the tunnel insulating film.

Example 5

7 is a diagram showing the configuration of a semiconductor device according to the fifth embodiment of the present invention. Here, an example of a nonvolatile memory device in which a memory cell array includes two planes is illustrated. In addition, only one block of the plurality of blocks is illustrated.

Referring to FIG. 7, a semiconductor device according to a fifth exemplary embodiment of the present invention includes a plurality of word lines (WL0 to WLn, n is a natural number), a plurality of bit lines (BL0 to BLm, m is a natural number), and a plurality of memories. A memory cell array 601 in which cells are arranged in a matrix form, and a plurality of page buffer groups 602 that sense data of cells from bit lines BL0 to BLm. As shown in FIG. 1, the memory cell array 601 includes a plurality of strings ST including a plurality of memory cells M0 to Mn connected in series between the first and second selection transistors DST and SST. In this case, the memory cells M0 to Mn share one well in the same plan. The bit lines BLO to BLm are respectively connected to the junction regions of the first select transistor DST configured in the string ST. The word lines WL0 to WLn are connected to the memory cell gates, respectively.

In addition, the semiconductor device according to the fifth exemplary embodiment of the present invention includes an operation mode signal generator 604 for generating an operation mode signal Vopm that determines a normal operation mode and a burn-in test operation mode. In this case, the normal operation mode means write, erase, and read operations.

In addition, the page buffer group 602 includes a plurality of page buffers PB for detecting memory cell data from even-numbered bit lines and odd-numbered bit lines in pairs. The page buffer PB transfers an acceleration voltage to any one of a pair of bit lines to be burn-in tested in the burn-in test operation mode. In this case, the acceleration voltage may be data stored in a latch of the page buffer PB or supplied from an input / output pad.

In addition, the semiconductor device according to the fifth exemplary embodiment of the present invention includes a first well voltage generator 606 for generating a first well voltage Vwell-nor required in a normal operation mode. In this case, the first well voltage Vwell-nor may be 18 to 20V or 0V. For example, the voltage may be about 18 to 20V during the erase operation, and about 0V corresponding to the ground voltage during the write and read operations.

In addition, the semiconductor device according to the fifth exemplary embodiment of the present invention generates a second well voltage Vwell-burn having a voltage level equal to the acceleration voltage, and outputs the second well voltage generator 605 to the selector 603. It includes. At this time, the second well voltage (Vwell-burn) may be about 3 ~ 10V.

In addition, the semiconductor device according to the fifth exemplary embodiment of the present invention selects and transmits one of the first and second well voltages Vwell-nor and Vwell-burn to a well in response to an operation mode signal Vopm. 603). The selector 603 may be turned on by the operation mode signal Vopm to transmit first and second well voltages Vwell-nor and Vwell-burn, respectively, as shown in FIG. 8. It consists of a 2nd switching element. For example, the first switching element may be made of a PMOS transistor P, and the second switching element may be made of an NMOS transistor.

Meanwhile, when a burn-in test operation is performed on a word line instead of a bit line, the semiconductor device according to the fifth exemplary embodiment of the present invention may be a word line of any one pair of word lines to be burn-in tested. It further comprises an X-decoder 600 for delivering an acceleration voltage.

The burn-in test method of the semiconductor device having such a configuration may be performed in the same manner as in Embodiments 3 and 4, and thus a detailed description thereof will be omitted.

In FIG. 7, '607' shows a part of the well pick-up area and is actually formed in the entire memory cell array area.

Meanwhile, in the semiconductor device according to the fifth exemplary embodiment of the present invention, an additional second well voltage generator 605 is configured to generate a second well voltage (Vwell-burn) having the same voltage as the acceleration voltage. This is to apply a voltage having the same magnitude as the acceleration voltage to the well.

As described in Embodiments 1 to 4 of the present invention, when the wells are floated during the burn-in test operation, the second well voltage generator 605 described in Embodiment 5 is not necessary. In addition, the selector 603 also requires only one switching element instead of two. In the normal operation mode, the voltage is turned on by the operation mode signal Vopm to transfer the well voltage generated from the well voltage generator 606, that is, the first well voltage Vwell-nor to the well. In the burn-in test operation mode, the well is turned off by the operation mode signal Vopm.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a diagram illustrating a configuration of a general nonvolatile memory device.

2 is a diagram illustrating a burn-in test method of a nonvolatile memory device according to the related art.

FIG. 3 is a diagram for explaining a burn-in test method for a semiconductor device according to example 1 of the present invention; FIG.

FIG. 4 is a diagram for explaining the burn-in test method of the semiconductor device according to the second embodiment of the present invention; FIG.

FIG. 5 is a diagram for explaining a burn-in test method for a semiconductor device according to Embodiment 3 of the present invention; FIG.

FIG. 6 is a diagram for explaining a burn-in test method for a semiconductor device according to Embodiment 4 of the present invention; FIG.

7 is a diagram for explaining the semiconductor device according to the fifth embodiment of the present invention;

8 is a diagram showing the configuration of the selection unit 603 shown in FIG.

<Explanation of symbols for main parts of drawing>

MCA, 601, 601: Memory Cell Arrays

PB: page buffer

M0 ~ Mn: memory cell

DST: drain select transistor (first select transistor)

SST: source select transistor (second select transistor)

DSL: Drain Select Line

SSL: source selection line

WL0 ~ WLn: Word line

BL0 ~ BLm, BLe, BLo: Bit line

LT: Latch

600: X-decoder

602 page buffer group

603: selection unit

604: operation mode signal generator

605: second well voltage generator

606: First well voltage generator

607: well pick-up area

Vrd1: first read voltage Vrd2: second read voltage

Vrd3: third read voltage PV1: first write area

PV2: second write area PV3: third write area

Claims (10)

A burn-in test method for a semiconductor device comprising a well, a plurality of junction regions formed in the well, and a plurality of wirings connected to the plurality of junction regions, respectively. Burn-in of a semiconductor device which applies an acceleration voltage to one of the pair of wirings to be burn-in tested, floats the well or applies a well voltage having the same voltage magnitude as the acceleration voltage to the well. Test method. A burn-in test method for a semiconductor device comprising a well formed in a substrate, a plurality of gates formed on the substrate, and a plurality of wirings connected to the plurality of gates, respectively. Burn-in of a semiconductor device which applies an acceleration voltage to one of the pair of wirings to be burn-in tested, floats the well or applies a well voltage having the same voltage magnitude as the acceleration voltage to the well. Test method. The method according to claim 1 or 2, Burn-in test method of a semiconductor device for applying a ground voltage to the wiring of the pair of wiring is not applied to the acceleration voltage. A burn-in of a semiconductor device comprising a plurality of strings including a plurality of memory cells sharing a well and connected in series with each other, and a plurality of bit lines respectively connected to a junction region of a first selection transistor respectively configured in the string. In the test method, The semiconductor device is configured to apply an acceleration voltage to any one of a pair of bit lines to be burn-in tested and to float the well or to apply a well voltage having the same voltage magnitude as the acceleration voltage to the well. Burn-in test method. The method of claim 4, wherein And a ground voltage is applied to a bit line of the pair of bit lines to which the acceleration voltage is not applied. The method of claim 4, wherein And the pair of bit lines are connected to the same page buffer. A semiconductor device comprising a plurality of strings including a plurality of memory cells sharing a well and connected in series between first and second select transistors, and a plurality of word lines respectively connected to the plurality of memory cell gates. In the test method Applying an acceleration voltage to any one of a pair of word lines to be burn-in tested among the plurality of word lines, and floating the well or having a voltage level equal to the acceleration voltage in the well Burn-in test method of a semiconductor device applying a voltage. The method of claim 7, wherein And a ground voltage is applied to a word line of the pair of word lines to which the acceleration voltage is not applied. A plurality of strings sharing a well and comprising a plurality of memory cells connected in series between the first and second select transistors, and a plurality of bit lines respectively connected to the junction regions of the first select transistors respectively configured in the string. In a semiconductor device comprising: An operation mode signal generator configured to generate an operation mode signal for determining a normal operation mode and a burn-in test operation mode; A page buffer transferring an acceleration voltage to any one of a pair of bit lines to be burn-in tested in the burn-in test operation mode; A first well voltage generator configured to generate a first well voltage required in the normal operation mode; A second well voltage generator configured to generate a second well voltage having the same magnitude as the acceleration voltage; And A selector configured to transfer the second well voltage to the well in response to the operation mode signal in the burn-in test operation mode, or to float the well by blocking the transfer to the well A semiconductor device comprising a. A semiconductor device comprising a plurality of strings including a plurality of memory cells sharing a well and connected in series between first and second select transistors, and a plurality of word lines respectively connected to the plurality of memory cell gates. , An operation mode signal generator configured to generate an operation mode signal for determining a normal operation mode and a burn-in test operation mode; A page buffer transferring an acceleration voltage to any one of a pair of word lines to be burn-in tested in the burn-in test operation mode; A first well voltage generator configured to generate a first well voltage required in the normal operation mode; A second well voltage generator configured to generate a second well voltage having the same magnitude as the acceleration voltage; And A selector configured to transfer the second well voltage to the well in response to the operation mode signal in the burn-in test operation mode, or to float the well by blocking the transfer to the well A semiconductor device comprising a.

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