KR102090874B1 - Nand flash memory device reducing the number of high voltage transistor - Google Patents

Abstract

Disclosed is a NAND flash memory device for reducing the number of high-voltage transistors. According to the present invention, the NAND flash memory device comprises: even bit lines; odd bit lines; common source lines; and a memory array which comprises an even cell string and an odd cell string, wherein each of the even cell string and the odd cell string comprises a plurality of cell transistors, a source selection transistor and a drain selection transistor, the plurality of cell transistors are configured in the form of NAND strings, the source selection transistor is driven in a manner that one side joint part of the cell transistor arranged at one ends of the plurality of cell transistors are connected with the common source line in response to a source selection signal, and the drain selection transistor is driven in a manner that one side joint part of the cell transistor arranged at the other ends of the plurality of transistors are connected with the corresponding even bit line and the corresponding odd bit line in response to a drain selection signal, an even discharge transistor which is driven so that the even bit line is connected to the common source line in response to an even discharge signal, and an odd discharge transistor which is driven so that the odd bit line is connected to the common source line in response to the odd discharge signal. According to the present invention, the NAND flash memory device reduces the overall required layout area by reducing the number of the required high voltage transistors.

Description

NAND FLASH MEMORY DEVICE REDUCING THE NUMBER OF HIGH VOLTAGE TRANSISTOR to reduce the number of high voltage transistors

The present invention relates to a NAND flash memory device, and more particularly, to a NAND flash memory device capable of reducing the number of high voltage transistors.

The NAND flash memory device can preserve data even when the power is not supplied, and erase of the selected cell transistors of the block can be performed at once.

1 is a view showing a conventional NAND flash memory device. The NAND flash memory device constitutes a string (STRe, STRo) in which a plurality of N-channel cell transistors MC <1: n> including a control gate and a floating gate are connected in series for high integration. In this case, in the strings STRE and STRo, a plurality of cell transistors MC <1: n> are common source lines CSL through source select transistors TRa and drain select transistors TRb disposed on both sides. And electrically connected to the even / od bit line BLe / BLo.

At this time, a typical erase operation of the NAND flash memory device is a high voltage of about 20V while a low or negative voltage is applied to the control gates of the plurality of cell transistors MC <1: n>. (WELL). In this case, the voltage of the even / od bit line BLe / BLo connected to the strings STRE and STRo may also be raised to around 20V. Then, the even / od bit line BLe / BLo after the erase operation is performed is discharged to the bias voltage VBIAS through discharge transistors TRDe and TRDo gated to the discharge signals DISCHe and DISCHo. Is occupied.

On the other hand, in the NAND flash memory device, a large number of transistors have a gate film having the same thickness as the source select transistor TRa and the drain select transistor TRb, and are designed to be controlled by a power supply voltage (VDD) of about 2.3 V at the gate terminal. do. In this case, when the even / ode bit line BLe / BLo, which is raised to about 20V, is directly connected to these transistors, the gate film may be damaged.

Thus, in the conventional NAND flash memory device of FIG. 1, in order to prevent such a gate film from being damaged, discharge transistors TRDe and TRDo connected to the even / od bit line BLe / BLo increase the thickness of the gate film. It consists of one high voltage transistor. For reference, even / odd selection transistors TRSe / TRSo gated by even / odd selection signals BSLe / BSLo are also composed of high voltage transistors.

However, in the case of such a high voltage transistor, the required layout required area becomes very large, which acts as a burden on the high integration of the NAND flash memory device.

Therefore, in the NAND flash memory device, it is required to reduce the number of high voltage transistors used.

Publication Patent No. 10-2002-0069092, Publication Date August 29, 2002

An object of the present invention is to provide a NAND flash memory device that reduces the number of high voltage transistors required and reduces the layout area as a whole.

One aspect of the present invention for achieving the above object relates to a NAND flash memory device. The NAND flash memory device of the present invention includes an even bit line; Odd bit line; Common source line; A memory array including an even cell string and an odd cell string, wherein each of the even cell string and the odd cell string includes a plurality of cell transistors, a source select transistor and a drain select transistor, and the plurality of cell transistors are NAND strings. The source select transistor is driven to connect one side junction of the cell transistor disposed at one end of the plurality of cell transistors to the common source line in response to a source select signal, and the drain select transistor is drain. The memory array driven to connect one side junction of the cell transistor disposed at the other end of the plurality of cell transistors to the corresponding even bit line and odd bit line in response to a selection signal; An even discharge transistor in response to the even discharge signal, wherein one side junction is connected to the even bit line; And an odd discharge transistor in response to the odd discharge signal, wherein one side junction is connected to the odd bit line. At this time, the other side junction of the even discharge transistor and the other side junction of the odd discharge transistor are each connected to the common source line.

In the NAND flash memory device of the present invention having the above structure, the other side junction of discharge transistors is connected to a common source line. Therefore, discharge transistors can be implemented as a low voltage transistor having a gate film of the same thickness as the source / drain select transistors. As a result, according to the NAND flash memory device of the present invention, the number of high voltage transistors required is reduced, and the layout area required as a whole is greatly reduced.

A brief description of each figure used in the present invention is provided.
1 is a view showing a conventional NAND flash memory device.
2 is a diagram illustrating a NAND flash memory device according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining the structure of a MOS transistor used in the NAND flash memory device of FIG. 2.
4 is a timing diagram for explaining voltage levels of main signals and nodes during an erase operation of the NAND flash memory device of FIG. 2.
FIG. 5 is a diagram illustrating a part of the page buffer PB of the NAND flash memory device of FIG. 2.

In order to fully understand the present invention and the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the contents described in the accompanying drawings, which illustrate preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete and that the spirit of the present invention is sufficiently conveyed to those skilled in the art.

Meanwhile, in the present specification, reference numerals are added to <> together with the same reference numerals for components performing the same configuration and operation. At this time, these components are referred to as reference numerals. And, when it is necessary to distinguish them individually, '<>' is added after the reference sign.

In describing the contents of the present invention throughout the specification, the meanings of the terms 'electrically connected', 'connected', and 'connected' between individual components are not only a direct connection, but also a property of a certain degree or more. This includes all connections made through an intermediate medium while being maintained. Terms such as 'transmitted' and 'lead' of each signal include not only the direct meaning but also the indirect meaning through an intermediate medium while maintaining the signal properties to some extent. In addition, terms such as 'applied,' 'applied', and 'input' to which a voltage or signal is applied are also used throughout this specification in the same sense.

In order to fully understand the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the following description and exemplary descriptions of the exemplary embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a NAND flash memory device according to an embodiment of the present invention.

First, before describing an embodiment of the NAND flash memory device of the present invention, the structure of a MOS transistor used in the NAND flash memory device of the present invention will be described.

FIG. 3 is a diagram for explaining the structure of a MOS transistor used in the NAND flash memory device of FIG. 2. For reference, it is understood that thickness and length are enlarged or reduced in order to clearly express various layers (or films) and regions in FIG. 3.

Referring to FIG. 3, the MOS transistor used in the NAND flash memory device of the present invention is largely divided into a low voltage transistor (LVTR) and a high voltage transistor (HVTR).

The low voltage transistor LVTR and the high voltage transistor HVTR are both formed in respective wells, and have respective gate electrodes ELGT1 and ELGT2 and gate films MGT1 and MGT2.

At this time, the gate film MGT1 of the low voltage transistor LVTR is relatively thin, and the gate film MGT2 of the high voltage transistor HVTR is relatively thick.

Here, when the voltage between the channels CHN1 and CHN2 formed in the well WELL and the gate electrodes ELGT1 and ELGT2 is large, the high voltage transistor HVTR has a higher probability of damage to the gate film than the low voltage transistor LVTR. It has the advantage of being very low.

However, the high voltage transistor HVTR has a disadvantage that a layout required area is very large compared to the low voltage transistor LVTR.

Therefore, in order to reduce the overall required area of the NAND flash memory device, it is very important to reduce the number of high voltage transistors used.

Referring to FIG. 2 again, the NAND flash memory device of the present invention includes an even bit line (BLe), an odd bit line (BLo), a common source line (CLS), a memory array (MARR), an even discharge transistor (TRDe), and An odd discharge transistor (TRDo) is provided.

The memory array MARR includes an even cell string STRe and an odd cell string STRo, and each of the even cell string STRe and an odd cell string STRo is arranged on a well WELL of a semiconductor substrate. And a plurality of cell transistors MC <1: n>, a source select transistor TRa, and a drain select transistor TRb.

At this time, the plurality of cell transistors MC <1: n> are arranged in the form of a NAND string, and are controlled by corresponding word lines WL <1: n>. In addition, the source select transistor TRa and the drain select transistor TRb are implemented as a low voltage transistor LVTR having a relatively thin gate film.

The source selection transistor TRa is a one side junction of the cell transistor MC <n> disposed at one end of the plurality of cell transistors MC <1: n> in response to the source selection signal SSL. It is driven to connect to the common source line (CSL). In addition, the drain select transistor TRb is one side of the cell transistor MC <1> disposed at the other end of the plurality of cell transistors MC <1: n> in response to the drain select signal DSL. It is driven to connect the junction to the corresponding even bit line (BLe) and odd bit line (BLo).

The even discharge transistor TRDe is driven to connect the even bit line BLe to the common source line CSL in response to the even discharge signal DISCHe. That is, in the even discharge transistor TRDe, one junction is a MOS transistor connected to the even bit line BLe, and the other junction is connected to the common source line CSL.

In addition, the odd discharge transistor TRDo is driven to connect the odd bit line BLo to the common source line CSL in response to the odd discharge signal DISCHo. That is, one junction of the odd discharge transistor TRDo is connected to the odd bit line BLo, and the other junction is a MOS transistor to the common source line CSL.

Preferably, the NAND flash memory device of the present invention further includes an even select transistor TRSe, an odd select transistor TRSo, and a page buffer PB.

The even select transistor TRSe and the odd select transistor TRSo are driven to selectively transmit any one of the even bit line BLe and the odd bit line BLo to the page buffer PB. .

That is, the even-selection transistor TRSe has one side junction connected to the even-bit line BLe, and is turned on in response to the even-select signal BLSe to transmit the signal of the even-bit line BLe to a common bit line BLCM. ) To the page buffer PB.

In addition, the odd select transistor TRSo has one side connected to the odd bit line BLo, and is turned on in response to the odd select signal BLSo to transmit the signal of the odd bit line BLo to the common bit line ( BLCM) to the page buffer PB.

At this time, the even select transistor TRSe and the odd select transistor TRSo have a relatively thick gate film, that is, a high voltage transistor (HVTR) of a gate film thicker than the source select transistor TRa and the drain select transistor TRb. It is preferably formed. In this case, the phenomenon that the even select transistor TRSe and the odd select transistor TRSo are damaged by the rising voltages of the even bit line BLe and the odd bit line BLo in the erase operation described later. Can be prevented.

The page buffer PB is driven to store signals of the even bit line and the odd bit line BLo transmitted through the even select transistor TRSe and the odd select transistor TRSo.

In the NAND flash memory device having the above structure, the even discharge transistor TRDe and the odd discharge transistor TRDo are relatively thin gate films, that is, the source select transistor TRa and the drain select transistor ( As it can be implemented with a low voltage transistor (LVTR) having a gate film of the same thickness as TRb), it will be continuously described.

FIG. 4 is a timing diagram for explaining voltage levels of main signals and nodes during an erase operation of the NAND flash memory device of FIG. 2.

First, the erase principle of the cell transistors MC <1: n> in the NAND flash memory device of the present invention will be described as follows.

At the erase timing P1 of the erase operation, the word lines WL <1: n> applied to the control gates of the cell transistors MC <1: n> of the cell strings STRe and STRo are '0V. Is controlled by. In addition, an erase voltage Vers (approximately '20V') is applied to the bulk well WELL of the cell transistors MC <1: n>.

Then, the net charge trapped in the floating gate existing between the bulk well WELL of the cell transistors MC <1: n> and the control gate is tunneled to the well WEEL. . Accordingly, the threshold voltage Vt of the cell transistors MC <1: n> is lowered. In addition, when the threshold voltage Vt is sufficiently low, '0V' is applied to the control gate and source of the cell transistor MC <1: n> and a positive voltage is applied to the drain, the cell transistor MC <1: n>) conducts the channel current. The cell transistor MC <1: n> having a low threshold voltage is referred to as an 'erased cell' or an 'erased state' and has a data value of '1'.

In this case, the floating common source line CSL is raised to (Vers-Vt) by electron injection between the wells (see t11, t11).

In addition, the floating source selection signal SSL and the drain selection signal DSL are channels of the source selection transistor TRa and the drain selection transistor TRb through which the voltage of the common source line CSL is conducted. It rises to (α x Vers) by the coupling between (t12, see).

On the other hand, the floating even bit line BLe and the odd bit line BLo also rise to about (Vers-Vt) by electron injection between the wells (see t13, t13). .

Further, the even discharge signal DISCHe and the even discharge signal DISCHe that are floating may include the even discharge transistor TRDe and the odd discharge transistor through which the voltage of the common source line CSL is conducted. TRDo) rises to (α x Vers) by coupling between channels (t14, see).

That is, the voltage between the gate and the channel in the even discharge transistor TRDe and the odd discharge transistor TRDo is between the gate and the channel in the source select transistor TRa and the drain select transistor TRb. Same as voltage.

Therefore, the even discharge transistor TRDe and the odd discharge transistor TRDo can be formed to have a gate film having the same thickness as the relatively thin source select transistor TRa and the drain select transistor TRb. Do.

Then, at the well discharge timing P2 that follows the erase timing P1, the voltage of the well WELL that is the bulk of the cell transistors MC <1: n> is' 0 at the erase voltage Vers. Is controlled again.

Then, due to coupling, the common source line CSL, the source select signal SSL, the drain select signal DSL, the even discharge signal DISCHe and the even discharge signal DISCHe Together, the even bit line BLe and the odd bit line BLo also fall toward the ground voltage VSS.

Meanwhile, in the semiconductor memory device of the present invention, charges that can remain on the even bit line BLe and the odd bit line BLO may be discharged using a page buffer PB or the like.

FIG. 5 is a diagram illustrating a part of the page buffer PB of the NAND flash memory device of FIG. 2.

The page buffer PB includes a sense transistor 10, a precharge transistor 20, and a transfer transistor 30.

In this case, the even bit line (BLe) and the odd bit line (BLo) electrically connected to the page buffer (PB) is a power supply voltage (through the sense transistor 10 and the pre-charge transistor 20) VCC).

Further, the even bit line BLe and the odd bit line BLo that are electrically connected to the page buffer PB are connected to the ground voltage VSS through the sense transistor 10 and the transfer transistor 30. It can be discharged.

The operation of the page buffer PB can be easily implemented by a person skilled in the art. Therefore, in this specification, a detailed description thereof is omitted.

In summary, in the NAND flash memory device of the present invention having the above structure, the even discharge transistor TRDe and the odd discharge transistor TRDo are the source select transistor TRa and the drain select transistor TRb. It can be implemented as a low-voltage transistor having a gate film of the same thickness.

Accordingly, according to the NAND flash memory device of the present invention, the number of high voltage transistors required is significantly reduced. As a result, according to the NAND flash memory device of the present invention, the layout area required as a whole is significantly reduced.

The present invention has been described with reference to one embodiment shown in the drawings, but this is merely exemplary, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims (4)

As a NAND flash memory device,
Even bit line;
Odd bit line;
Common source line;
A memory array including an even cell string and an odd cell string, wherein each of the even cell string and the odd cell string includes a plurality of cell transistors, a source select transistor and a drain select transistor, and the plurality of cell transistors are NAND strings. The source select transistor is driven to connect one side junction of the cell transistor disposed at one end of the plurality of cell transistors to the common source line in response to a source select signal, and the drain select transistor is drain. The memory array driven to connect one side junction of the cell transistor disposed at the other end of the plurality of cell transistors to the corresponding even bit line and odd bit line in response to a selection signal;
An even discharge transistor in response to the even discharge signal, wherein one side junction is connected to the even bit line; And
An odd discharge transistor in response to the odd discharge signal, wherein one side junction is connected to the odd bit line,
The other side junction of the even discharge transistor and the other side junction of the odd discharge transistor are each
And a NAND flash memory device connected to the common source line.
The gate layer of the even discharge transistor and the odd discharge transistor is
And a gate film of the source select transistor and a gate film of the drain select transistor.
The method of claim 1, wherein the NAND flash memory device
An even select transistor connected to the even bit line and turned on in response to an even select signal, wherein the even select transistor is formed to have a thicker gate film than the even discharge transistor;
An odd select transistor connected to the odd bit line and turned on in response to an odd select signal, wherein the odd select transistor is formed to have a thicker gate film than the odd discharge transistor; And
And a page buffer driven to store signals of the even bit line and the odd bit line transmitted through the even select transistor and the odd select transistor.
The method of claim 3, wherein the page buffer
And a discharge device for discharging electric charges of the even bit line and the odd bit line.

Images