TWI718471B - NAND flash memory device with reduced number of high-voltage transistors - Google Patents

Abstract

The invention discloses a NAND flash memory device that reduces the number of high-voltage transistors, including: even bit lines; odd bit lines; common source lines; memory arrays, including even cell strings and odd cell strings, even cell strings and odd cells The strings respectively include a plurality of cell transistors, a source selection transistor, and a drain selection transistor. The plurality of cell transistors are arranged in the form of a NAND string, and the source selection transistors are configured such that one side of the junction part disposed at one end of the plurality of cell transistors and the common source It is driven in a manner that the pole lines are connected, and the drain selection transistor is driven in a manner that the one-side junction disposed at the other end of the plurality of cell transistors is connected to the corresponding even-numbered bit lines and odd-numbered bit lines; even discharge transistors, Drive in a way that even-numbered bit lines are connected to a common source line; and odd-numbered discharge transistors are driven in a way that connects odd-numbered bit lines to a common source line. The NAND flash memory device of the present invention reduces the overall layout area by reducing the number of high-voltage transistors.

Description

NAND flash memory device with reduced number of high-voltage transistors

The present invention relates to a NAND flash memory device, and more particularly, to a NAND flash memory device capable of reducing the number of high-voltage transistors.

The NAND flash memory device can store data even when the power is not supplied, and can eliminate multiple cell transistors of the selected block at one time.

FIG. 1 is a diagram showing a conventional NAND flash memory device. For high integration, the NAND flash memory device constitutes a plurality of N-channel-shaped cell transistors MC<1:n> including a control gate and a floating gate, and strings STRe and STRo connected in series. At this time, in the strings STRe and STRo, the plurality of cell transistors MC<1:n> pass through the source selection transistors TRa and the drain selection transistors TRb, the common source line CSL and the even-numbered bit line BLe, which are arranged on both sides. , Odd bit line BLo electrical connection.

At this time, the typical NAND flash memory device erasing work is to reduce the voltage of about 20V during the process of applying low or negative voltage to the control gates of a plurality of cell transistors MC<1:n>. High voltage is applied to the well WELL for execution. In this case, the voltages of the even bit lines BLe and the odd bit lines BLo connected to the strings STRe and STRo can rise to about 20V. In addition, the even-numbered bit lines BLe and odd-numbered bit lines BLo after performing the erasing operation are discharged to the bias voltage VBIAS through the plurality of discharge transistors TRDe, TRDo strobed with the plurality of discharge signals DISCHe, DISCHo.

On the other hand, in a NAND flash memory device, a considerable number of transistors have a gate film with the same thickness as the above-mentioned source selection transistor TRa and drain selection transistor TRb, and a power supply voltage of approximately 2.3V is applied to the gate terminal. VDD controls. In this case, when such a plurality of transistors are directly connected to the even-numbered bit lines BLe and the odd-numbered bit lines BLo, which rise to about 20V, the gate film may be damaged.

Therefore, in the conventional NAND flash memory device of FIG. 1, in order to prevent the damage of the gate film, the plurality of discharge transistors TRDe and TRDo connected to the even-numbered bit line BLe and odd-numbered bit line BLo are separated from the gate film. The thickness of the high-voltage transistor is formed. For reference, the even selection transistors TRSe and the odd selection transistors TRSo that are gated by the even selection signal BSLe and the odd selection signal BSLo are also composed of high-voltage transistors.

However, in the case of such high-voltage transistors, the required layout area is very large, which is a burden for the high integration of NAND flash memory devices.

Therefore, NAND flash memory devices need to reduce the number of high-voltage transistors used.

Prior art documents: Korean Published Patent No. 10-2002-0069092, publication date: August 29, 2002.

The object of the present invention is to provide a NAND flash memory device that reduces the number of required high-voltage transistors to reduce the overall layout area.

One embodiment of the present invention for achieving the above-mentioned object relates to a NAND flash memory device. The NAND flash memory device of the present invention includes: even-numbered bit lines; odd-numbered bit lines; common source lines; memory arrays, including even-cell strings and odd-cell strings, each of the even-cell strings and the odd-cell strings includes a plurality of cell transistors , A source selection transistor, and a drain selection transistor, the plurality of cell transistors are arranged in the form of a NAND string, and the source selection transistor responds to a source selection signal to make the cell transistor arranged at one end of the plurality of cell transistors The one-side junction of the cell transistor is driven by being connected to the common source line, and the drain selection transistor responds to the drain selection signal to make the one-side junction of the cell transistor disposed at the other end of the plurality of cell transistors Driven in a manner connected to the corresponding even-numbered bit lines and odd-numbered bit lines; the even discharge transistor is driven in a manner that connects the even-numbered bit lines to the common source lines in response to an even discharge signal; and The odd discharge transistor is driven in response to an odd discharge signal to connect the odd bit line and the common source line.

In the NAND flash memory device of the present invention configured as described above, the other side junctions of the plurality of discharge transistors are connected to the common source line. Therefore, the plurality of discharge transistors can be realized by low-voltage transistors having a gate film with the same thickness as those of the source selection transistors and the drain selection transistors. Finally, according to the NAND flash memory device of the present invention, the overall required layout area is greatly reduced by reducing the number of required high-voltage transistors.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the implementation of the present invention, please refer to the drawings illustrating preferred embodiments of the present invention and the content described in the drawings. However, the present invention is not limited to the embodiments described here, and can be embodied in other ways. On the contrary, the embodiments introduced here are provided for a thorough and complete understanding of the disclosed content and to fully convey the idea of the present invention to the ordinary skilled person.

On the other hand, in this specification, for structural elements that have the same structure and perform the same function, reference numerals are added in <> together with the same reference numerals. At this time, these structural elements are collectively referred to with reference numerals. And, in the case where they need to be distinguished separately, "<>" is added to the back side of the reference sign.

In the process of describing the content of the present invention through the full text of the specification, the meanings of the terms "electrically connected", "connected", and "connected" between the various structural elements include not only the case of direct connection, but also the use of When the attributes are maintained above a predetermined level and are connected through an intermediate medium. Terms such as "transmit" and "derive" each signal also include not only the direct meaning, but also the indirect meaning of maintaining the properties of the signal above a predetermined level through an intermediate medium. Throughout the specification, other terms such as "apply", "induct", "input" voltage or signal are also used with the same meaning.

In order to fully understand the operational advantages of the present invention and the objects achieved by the embodiments of the present invention, it is necessary to refer to the following content describing the exemplary embodiments of the present invention and the content described in the drawings together.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

FIG. 2 is a diagram showing a NAND flash memory device according to an embodiment of the present invention.

First, before describing an embodiment of the NAND flash memory device of the present invention, the structure of the MOS transistor used in the NAND flash memory device of the present invention will be described.

FIG. 3 is a diagram for explaining the structure of a MOS transistor used in the NAND flash memory device of FIG. 2. For reference, it should be understood that, in order to clearly show each layer (or film) and region, the thickness and length are shown enlarged or reduced in FIG. 3.

3, the MOS transistor used in the NAND flash memory device of the present invention is roughly divided into a low voltage transistor LVTR and a high voltage transistor HVTR.

The low voltage transistor LVTR and the high voltage transistor HVTR are both formed in the respective wells WELL, and have respective gate electrodes ELGT1, ELGT2 and gate films MGT1, MGT2.

At this time, the gate film MGT1 of the low voltage transistor LVTR is relatively thin, and the gate film MGT2 of the high voltage transistor HVTR is relatively thick.

However, when the voltage between the channels CHN1 and CHN2 formed in the well WELL and the gate electrodes ELGT1 and ELGT2 is large, the high voltage transistor HVTR has a possibility of damage to the gate film compared to the low voltage transistor LVTR. Very low advantage.

However, compared with the above-mentioned low-voltage transistor LVTR, the above-mentioned high-voltage transistor HVTR has the disadvantage of a large area required for layout.

Therefore, in order to reduce the overall required area of the NAND flash memory device, it is particularly important to reduce the number of required high-voltage transistors.

2 again, the NAND flash memory device of the present invention includes even bit lines BLe, odd bit lines BLo, common source lines CSL, memory array MARR, even discharge transistor TRDe, and odd discharge transistor TRDo.

The memory array MARR includes an even cell string STRe and an odd cell string STRo. The even cell string STRe and the odd cell string STRo respectively include a plurality of cell transistors MC<1:n> arranged on the well WELL of the semiconductor substrate, and source selection The transistor TRa and the drain selection transistor TRb.

At this time, the plurality of cell transistors MC<1:n> are arranged in the form of a NAND string, and are controlled by the corresponding word line WL<1:n>. Also, the above-mentioned source selection transistor TRa and the above-mentioned drain selection transistor TRb are realized by a low-voltage transistor LVTR having a gate film with a relatively thin thickness.

The source selection transistor TRa responds to the source selection signal SSL so that the one-side junction of the cell transistor MC<n> arranged at one end of the plurality of cell transistors MC<1:n> is connected to the common source line Driven by the way CSL is connected. In addition, the drain selection transistor TRb responds to the drain selection signal DSL so that the one side junction of the cell transistor MC<1> arranged at the other end of the plurality of cell transistors MC<1:n> is connected to the coupler. It is driven in a way that the digital bit line BLe and the odd bit line BLo are connected.

The even discharge transistor TRDe is driven in response to the even discharge signal DISCHe to connect the even bit line BLe and the common source line CSL.

In addition, the odd discharge transistor TRDo is driven in response to an odd discharge signal DISCHo to connect the odd bit line BLo and the common source line CSL.

Preferably, the above-mentioned NAND flash memory device of the present invention further includes an even selection transistor TRSe, an odd selection transistor TRSo, and a page buffer PB.

The even selection transistor TRSe and the odd selection transistor TRSo are driven to selectively transmit one of the even bit line BLe and the odd bit line BLo to the page buffer PB.

That is, one side junction of the even selection transistor TRSe is connected to the even bit line BLe, is turned on in response to the even selection signal BLSe, and the signal of the even bit line BLe is buffered to the page through the common bit line BLCM器PB transmission.

In addition, one side junction of the odd selection transistor TRSo is connected to the odd bit line BLo, and is turned on in response to the odd selection signal BLSo, and the signal of the odd bit line BLo is transferred to the page through the common bit line BLCM. Buffer PB transmission.

At this time, it is preferable that the even selection transistor TRSe and the odd selection transistor TRSo have a relatively thick gate film, that is, the high voltage of a thicker gate film than the source selection transistor TRa and the drain selection transistor TRb. The transistor HVTR is formed. In this case, it is possible to prevent the even selection transistor TRSe and the odd selection transistor TRSo from being damaged by the rising voltage of the even bit line BLe and the odd bit line BLo in the erasing operation described later.

The page buffer PB is driven to store the signals of the even bit line and the odd bit line BLo transmitted through the even selection transistor TRSe and the odd selection transistor TRSo.

In the NAND flash memory device having the above-mentioned structure, the even discharge transistor TRDe and the odd discharge transistor TRDo may be made of a relatively thin gate film, that is, having a gate film that is similar to the source selection transistor TRa and the drain selection transistor TRb. The low-voltage transistor LVTR of the gate film with the same thickness is realized, and the description will be continued.

4 is a timing chart for explaining main signals and voltage intensities of nodes during the erasing operation of the NAND flash memory device of FIG. 2.

First, the principle of erasing multiple cell transistors MC<1:n> in the NAND flash memory device of the present invention is explained as follows.

In the erasing timing P1 of the erasing operation, the plurality of word lines WL<1:n> applied to the control gates of the plurality of cell transistors MC<1:n> of the plurality of cell strings STRe and STRo are controlled to "0V". In addition, the cancellation voltage (Vers, approximately “20V”) is applied to the bulk wells WELL of the plurality of cell transistors MC<1:n>.

Then, the net charge (net charge) trapped in the floating gate between the bulk well WELL existing in the plurality of cell transistors MC<1:n> and the control gate is transferred to the well WELL. As a result, the threshold voltage Vt of the plurality of cell transistors MC<1:n> is lowered. In addition, when the threshold voltage Vt is sufficiently reduced and "0V" is applied to the control gate and source of the cell transistor MC<1:n> and a positive voltage is applied to the drain, the cell transistor MC<1:n> turns on the channel Current. The cell transistor MC<1:n> having a low threshold voltage as described above is called an "erased cell" or "erased state", and has a data value of "1".

In this case, the floating common source line CSL rises to about Vers-Vt by charge injection between the wells WELL (refer to reference t11).

In addition, the floating source select signal SSL and the drain select signal DSL rise to α through the coupling between the source select transistor TRa and the drain select transistor TRb that turns on the voltage of the common source line CSL. ×Vers (refer to label t12).

On the other hand, the floating even-numbered bit line BLe and the odd-numbered bit line BLo also rise to about Vers-Vt by the charge injection between the wells WELL (refer to t13).

In addition, the floating even discharge signal DISCHe and the odd discharge signal DISCHo rise to α×Vers through the coupling between the channels of the even discharge transistor TRDe and the odd discharge transistor TRDo that turns on the voltage of the common source line CSL (refer to Label t14).

That is, the voltage between the gate and the channel in the even discharge transistor TRDe and the odd discharge transistor TRDo is the same as the voltage between the gate and the channel in the source selection transistor TRa and the drain selection transistor TRb.

Therefore, the even discharge transistor TRDe and the odd discharge transistor TRDo can be formed with a gate film having the same thickness as the relatively thin source selection transistor TRa and the drain selection transistor TRb.

In addition, in the well discharge timing P2 performed next to the erasing timing P1, the voltage of the bulk wells WELL of the plurality of cell transistors MC<1:n> is controlled to "0" again from the erasing voltage Vers.

Then, due to coupling and the like, together with the common source line CSL, the source selection signal SSL, the drain selection signal DSL, the even discharge signal DISCHe, and the odd discharge signal DISCHo, the even bit line BLe and the odd The digit line BLo also drops to the ground voltage VSS side.

On the other hand, in the semiconductor memory device of the present invention, the electric charge that can remain in the even-numbered bit line BLe and the odd-numbered bit line BLo can also be discharged using a page buffer PB or the like.

FIG. 5 is a diagram showing a part of the page buffer PB of the NAND flash memory device of FIG. 2.

The aforementioned paging buffer PB includes a detection transistor 10, a discharge transistor 20, and a transfer transistor 30.

In this case, the even-numbered bit line BLe and the odd-numbered bit line BLo electrically connected to the page buffer PB can be discharged to the power supply voltage VCC through the detection transistor 10 and the discharge transistor 20.

In addition, the even-numbered bit line BLe and the odd-numbered bit line BLo electrically connected to the page buffer PB can be discharged to the ground voltage VSS through the detection transistor 10 and the transfer transistor 30.

A person of ordinary skill can easily realize the work of this paging buffer PB. Therefore, in this specification, specific descriptions related to this will be omitted.

In the NAND flash memory device of the present invention having the structure as described above, the even discharge transistor TRDe and the odd discharge transistor TRDo may have a gate having the same thickness as the source selection transistor TRa and the drain selection transistor TRb. Realization of extremely thin film low-voltage transistors.

Thus, according to the NAND flash memory device of the present invention, the number of high-voltage transistors required is significantly reduced. Finally, according to the NAND flash memory device of the present invention, the overall required layout area is significantly reduced.

The above description shows and describes several preferred embodiments of this application, but as mentioned above, it should be understood that this application is not limited to the form disclosed herein, and should not be regarded as an exclusion of other embodiments, but can be used in various Other combinations, modifications, and environments can be modified through the above teachings or technology or knowledge in related fields within the scope of the application concept described herein. The modifications and changes made by those skilled in the art do not depart from the spirit and scope of this application, and should all fall within the protection scope of the attached patent application of this application.

BLe: even bit line BLo: odd bit line CSL: common source line MARR: memory array TRDe: even discharge transistor TRDo: odd discharge transistor STRe: even cell string STRo: odd cell string MC<1>...MC<n >: Cell transistor TRa: Source selection transistor TRb: Drain selection transistor WL<1>...WL<n>: Word line SSL: Source selection signal DSL: Drain selection signal DISCHe: Even discharge signal DISCHo: Odd discharge signal TRSe: even selection transistor TRSo: odd selection transistor PB: page buffer BLCM: common bit line LVTR: low voltage transistor HVTR: high voltage transistor WELL: well ELGT1, ELGT2: gate electrode MGT1, MGT2: gate film CHN1 CHN2: Channel P1: Elimination timing P2: Well discharge timing 10: Detection transistor 20: Discharge transistor 30: Transfer transistor VCC: Power supply voltage VSS: Ground voltage BLSe: Even selection signal BLSo: Odd selection signal

A brief description of each drawing used in the present invention is provided. FIG. 1 is a diagram showing a conventional NAND flash memory device. FIG. 2 is a diagram showing a NAND flash memory device according to an embodiment of the present invention. FIG. 3 is a diagram for explaining the structure of a MOS transistor used in the NAND flash memory device of FIG. 2. 4 is a timing chart for explaining main signals and voltage intensities of nodes during the erasing operation of the NAND flash memory device of FIG. 2. FIG. 5 is a diagram showing a part of the page buffer PB of the NAND flash memory device of FIG. 2.

BLe: Even bit line

BLo: odd bit line

CSL: Common source line

MARR: storage array

TRDe: Even discharge transistor

TRDo: odd discharge transistor

STRe: Even cell string

STRo: odd cell string

MC<1>...MC<n>: unit transistor

TRa: source select transistor

TRb: Drain selection transistor

WL<1>...WL<n>: word line

SSL: Source selection signal

DSL: Drain selection signal

DISCHe: Even discharge signal

DISCHo: odd discharge signal

TRSe: Even select transistor

TRSo: odd selection transistor

PB: paging buffer

BLCM: common bit line

BSLe: Even selection signal

BSLo: odd selection signal

Claims (4)

A NAND flash memory device, characterized in that it comprises: even bit lines; odd bit lines; common source lines; a storage array including even cell strings and odd cell strings, the even cell strings and the odd cell strings each including multiple A cell transistor, a source selection transistor, and a drain selection transistor, the plurality of cell transistors are arranged in the form of a NAND string, and the source selection transistor responds to a source selection signal so that the One side of the unit transistor is connected to the common source line, and the drain selection transistor responds to the drain selection signal to enable one of the unit transistors arranged at the other end of the plurality of unit transistors. The side junction is driven in a manner that the corresponding even-numbered bit line and the odd-numbered bit line are connected; the even discharge transistor responds to an even discharge signal to connect the even-numbered bit line to the common source line Driving; and an odd discharge transistor, which is driven in response to an odd discharge signal to connect the odd bit line to the common source line; wherein the common source line, the even discharge signal, and the odd discharge signal are floating. The NAND flash memory device according to claim 1, wherein the gate films of the even discharge transistor and the odd discharge transistor have the same gate film as the gate film of the source selection transistor and the gate film of the drain selection transistor. The thickness is the same as the thickness. The NAND flash memory device according to claim 1, wherein the NAND flash memory device further includes: an even selection transistor, one side of the junction is connected to the even bit line and turned on in response to the even selection signal to have a ratio The even discharge transistor is formed by a thicker gate film; the odd selection transistor, one side of the junction is connected to the odd bit line and turned on in response to the odd selection signal to have a thicker gate than the odd discharge transistor And the page buffer is driven to store the signal of the even bit line and the signal of the odd bit line transmitted through the even selection transistor and the odd selection transistor. The NAND flash memory device according to claim 3, wherein the paging buffer is driven in a manner capable of discharging charges of the even-numbered bit lines and the odd-numbered bit lines.

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