CN109727988B - NAND flash memory device with reduced number of high voltage transistors - Google Patents
NAND flash memory device with reduced number of high voltage transistors Download PDFInfo
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- CN109727988B CN109727988B CN201811634107.6A CN201811634107A CN109727988B CN 109727988 B CN109727988 B CN 109727988B CN 201811634107 A CN201811634107 A CN 201811634107A CN 109727988 B CN109727988 B CN 109727988B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The invention discloses a NAND flash memory device reducing the number of high voltage transistors, comprising: an even bit line; odd bit lines; a common source line; a memory array including even cell strings and odd cell strings, the even cell strings and the odd cell strings including a plurality of cell transistors, source selection transistors, and drain selection transistors, respectively, the plurality of cell transistors being arranged in a NAND string, the source selection transistors being driven such that one-side junctions arranged at one ends of the plurality of cell transistors are connected to a common source line, the drain selection transistors being driven such that one-side junctions arranged at the other ends of the plurality of cell transistors are connected to corresponding even bit lines and odd bit lines; an even discharge transistor driven so as to connect the even bit lines to the common source line; and an odd discharge transistor driven in such a manner that the odd bit lines are connected to the common source line. The NAND flash memory device of the present invention reduces the overall layout area by reducing the number of high voltage transistors.
Description
Technical Field
The present invention relates to a NAND flash memory device, and more particularly, to a NAND flash memory device in which the number of high voltage transistors can be reduced.
Background
The NAND flash memory device can store data even in a state where power is not supplied, and can erase a plurality of cell transistors of a selected block at once.
Fig. 1 is a diagram illustrating a conventional NAND flash memory device. For high integration, the NAND flash memory device constitutes strings STRe, STRo in which a plurality of N-channel-shaped cell transistors MC <1: N > including a control gate and a floating gate are connected in series. In this case, in the strings STRe and STRo, the plurality of cell transistors MC <1: n > are electrically connected to the common source line CSL, the even bit line BLe, and the odd bit line BLo through the source selection transistor TRa and the drain selection transistor TRb disposed on both sides.
At this time, a typical erase operation of the NAND flash memory device is performed by applying a high voltage of about 20V to the WELL in the course of applying a low voltage (low) or a negative voltage (negative) to the control gates of the plurality of cell transistors MC <1: n >. In this case, the voltages of the even bit lines BLe and the odd bit lines BLo connected to the strings STRe and STRo may rise to about 20V. The even bit line BLe and the odd bit line BLo after the erase operation are discharged to the bias voltage VBIAS by the plurality of discharge transistors TRDe and TRDo gated by the plurality of discharge signals DISCHe and DISCHo.
On the other hand, in the NAND flash memory device, a large number of transistors have gate films having the same thickness as the source selection transistor TRa and the drain selection transistor TRb, and are controlled at the gate terminal by the power supply voltage VDD of about 2.3V. In this case, if such a plurality of transistors are directly connected to the even bit line BLe and the odd bit line BLo rising to about 20V, the gate film may be damaged.
Therefore, in the conventional NAND flash memory device of fig. 1, in order to prevent such damage of the gate film, the plurality of discharge transistors TRDe and TRDo connected to the even bit line BLe and the odd bit line BLo are formed of high-voltage transistors having a thickness larger than that of the gate film. For reference, the even selection transistors TRSe and the odd selection transistors TRSo which are gated by the even selection signal BSLe and the odd selection signal BSLo are also formed of high voltage transistors.
However, in the case of such a high-voltage transistor, a required layout area is very large, which is a burden of high integration of the NAND flash memory device.
Therefore, the NAND flash memory device needs to reduce the number of high voltage transistors used.
Prior art documents: korean laid-open patent No. 10-2002-0069092, published: year 2002, month 08, 29.
Disclosure of Invention
An object of the present invention is to provide a NAND flash memory device in which the number of high-voltage transistors required is reduced to reduce the layout area as a whole.
One embodiment of the present invention for achieving the above object relates to a NAND flash memory device. The NAND flash memory device of the present invention includes: an even bit line; odd bit lines; a common source line; a memory array including even cell strings and odd cell strings, each of the even cell strings and the odd cell strings including a plurality of cell transistors, a source selection transistor, and a drain selection transistor, the plurality of cell transistors being arranged in a NAND string, the source selection transistor being driven in response to a source selection signal so as to connect one-side junctions of the cell transistors arranged at one ends of the plurality of cell transistors to the common source line, the drain selection transistor being driven in response to a drain selection signal so as to connect one-side junctions of the cell transistors arranged at the other ends of the plurality of cell transistors to the corresponding even bit lines and odd bit lines; an even discharge transistor which is driven in response to an even discharge signal so as to connect the even bit line and the common source line; and an odd discharge transistor driven in response to an odd discharge signal in such a manner as to connect the odd bit line and the common source line.
In the NAND flash memory device of the present invention having the above configuration, the other-side junction portions of the plurality of discharge transistors are connected to the common source line. Therefore, the plurality of discharge transistors can be realized by a low-voltage transistor having a gate film with the same thickness as that of the source selection plurality of transistors and the drain selection plurality of transistors. Finally, according to the NAND flash memory device of the present invention, the overall required layout area is greatly reduced by reducing the number of required high-voltage transistors.
Drawings
A brief description of the various figures used in the present invention is provided.
Fig. 1 is a diagram illustrating a conventional NAND flash memory device.
Fig. 2 is a diagram illustrating a NAND flash memory device according to an embodiment of the present invention.
Fig. 3 is a diagram for explaining a structure of a MOS transistor used in the NAND flash memory device of fig. 2.
Fig. 4 is a timing diagram for explaining main signals and voltage strengths of nodes at the time of erase operation of the NAND flash memory device of fig. 2.
Fig. 5 is a diagram illustrating a part of the page buffer PB of the NAND flash memory device of fig. 2.
Detailed Description
In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the implementation of the present invention, reference should be made to the drawings illustrating preferred embodiments of the present invention and the contents thereof. However, the present invention is not limited to the embodiments described herein, and can be embodied in other forms. Rather, the embodiments described herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.
On the other hand, in the present specification, the same reference numerals are added to the components having the same structure and performing the same function as those having the same reference numerals. In this case, these components are collectively referred to by reference numerals. And, in the case where it is necessary to distinguish them individually, "< >" is added on the rear side of the reference numeral.
In the course of describing the contents of the present invention throughout the specification, the terms "electrically connected", "connected", and "coupled" between the respective constituent elements include not only a case of being directly connected but also a case of being connected through an intermediate medium in a state where the properties are maintained at a predetermined level or more. The terms "transfer", "derive" and the like of the respective signals also include not only a direct meaning but also an indirect meaning in which a state in which an attribute of the signal is maintained at a predetermined level or more is passed through an intermediate medium. Throughout the specification, other terms such as "apply", "introduce", "input" voltage or signal are used with the same meaning.
For a sufficient understanding of the operational advantages of the present invention and the objects achieved by the embodiments of the present invention, reference should be made to the following description and accompanying drawings which describe exemplary embodiments of the present invention.
Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.
Fig. 2 is a diagram illustrating a NAND flash memory device according to an embodiment of the present invention.
First, before describing embodiments of the NAND flash memory device of the present invention, a description will be given of a structure of a MOS transistor used in the NAND flash memory device of the present invention.
Fig. 3 is a diagram for explaining a structure of a MOS transistor used for the NAND flash memory device of fig. 2. For reference, it is to be understood that the thickness and length are shown enlarged or reduced in fig. 3 for clearly showing each layer (or film) and the region.
Referring to fig. 3, MOS transistors used in the NAND flash memory device of the present invention are roughly classified into a low voltage transistor LVTR and a high voltage transistor HVTR.
The low-voltage transistor LVTR and the high-voltage transistor HVTR are formed in the respective WELLs WELL, and have respective gate electrodes eltt 1 and eltt 2 and gate films MGT1 and MGT 2.
At this time, the gate film MGT1 of the low-voltage transistor LVTR is relatively thin, and the gate film MGT2 of the high-voltage transistor HVTR is relatively thick.
Among them, when the voltage between the channels CHN1 and CHN2 and the gate electrodes ELGT1 and eltt 2 formed in the WELL is large, the high-voltage transistor HVTR has an advantage that the possibility of breakage of the gate film is low as compared to the low-voltage transistor LVTR.
However, the above-described high-voltage transistor HVTR has a disadvantage that an area required for layout is large, compared to the above-described low-voltage transistor LVTR.
Therefore, in order to reduce the overall required area of the NAND flash memory device, it is important to reduce the number of required high-voltage transistors.
Referring again to fig. 2, the NAND flash memory device of the present invention includes an even bit line BLe, an odd bit line BLo, a common source line CSL, a memory array mar, an even discharge transistor TRDe, and an odd discharge transistor TRDo.
The memory array mar includes even cell strings STRe and odd cell strings STRo each including a plurality of cell transistors MC <1: n >, a source selection transistor TRa, and a drain selection transistor TRb arranged in a WELL of a semiconductor substrate.
At this time, the plurality of cell transistors MC <1: n > are arranged in a NAND string and controlled by corresponding word lines WL <1: n >. Also, the above-described source selection transistor TRa and the above-described drain selection transistor TRb are realized by the low voltage transistor LVTR having a gate film with a relatively thin thickness.
The source selection transistor TRa is driven in response to a source selection signal SSL so as to connect one-side junction of the cell transistors MC < n >, which are disposed at one ends of the plurality of cell transistors MC <1: n >, to the common source line CSL. The drain select transistor TRb is driven in response to a drain select signal DSL so as to connect one-side junction of the cell transistor MC <1> disposed at the other end of the plurality of cell transistors MC <1: n > to the even bit line BLe and the odd bit line BLo.
The even discharge transistor TRDe is driven in response to an even discharge signal DISCHe so as to connect the even bit line BLe to the common source line CSL.
The odd discharge transistor TRDo is driven in response to an odd discharge signal DISCHo to connect the odd bit line BLo to the common source line CSL.
Preferably, the NAND flash memory device of the present invention further includes an even selection transistor TRSe, an odd selection transistor TRSo, and a page buffer PB.
The even selection transistor TRSe and the odd selection transistor TRSo are driven to selectively transmit one of the signals on the even bit line BLe and the odd bit line BLo to the page buffer PB.
That is, one side junction of the even selection transistor TRSe is connected to the even bit line BLe, and a signal of the even bit line BLe is turned on by an even selection signal BSLe and transmitted to the page buffer PB through the common bit line BLCM.
One junction of the odd select transistor TRSo is connected to the odd bit line BLo, and is turned on in response to an odd select signal BSLo to transmit a signal of the odd bit line BLo to the page buffer PB through the common bit line BLCM.
At this time, it is preferable that the even selection transistor TRSe and the odd selection transistor TRSo are formed by a high voltage transistor HVTR having a relatively thick gate film, that is, a gate film thicker than the source selection transistor TRa and the drain selection transistor TRb. In this case, the phenomenon that the even selection transistor TRSe and the odd selection transistor TRSo are broken can be prevented by the rising voltages of the even bit line BLe and the odd bit line BLo during the erase operation described later.
The page buffer PB is driven to store the signals of the even bit line and the odd bit line BLo transmitted through the even selection transistor TRSe and the odd selection transistor TRSo.
In the NAND flash memory device having the above-described structure, the even discharge transistor TRDe and the odd discharge transistor TRDo may be implemented by the low voltage transistor LVTR having a relatively thin gate film, that is, a gate film having the same thickness as that of the source selection transistor TRa and the drain selection transistor TRb, and the description thereof will be continued.
Fig. 4 is a timing diagram for explaining main signals and voltage strengths of nodes at the time of erase operation of the NAND flash memory device of fig. 2.
First, the principle of erasing the plurality of cell transistors MC <1: n > in the NAND flash memory device of the present invention is explained as follows.
At the erasing timing P1 of the erasing operation, the word lines WL <1: n > applied to the control gates of the cell transistors MC <1: n > of the cell strings STRe and STRo are controlled to be "0V". Then, an erase voltage (Vers, about 20V) is applied to the bulk WELL WELL of the plurality of cell transistors MC <1: n >.
Then, net charge (net charge) trapped in the floating gate existing between the bulk WELL WELL of the plurality of cell transistors MC <1: n > and the control gate is transferred to the WELL WELL. This lowers the threshold voltage Vt of the plurality of cell transistors MC <1: n >. When the threshold voltage Vt is sufficiently lowered and "0V" is applied to the control gate and the source of the cell transistor MC <1: n > and a positive voltage is applied to the drain, the cell transistor MC <1: n > conducts a channel current. The cell transistor MC <1: n > having the low threshold voltage as described above is referred to as an "erased cell" or an "erased state", and has a data value of "1".
In this case, the floating common source line CSL is raised to Vers-Vt or so by charge injection (charging) between the WELLs WELL (see t 11).
The floating source selection signal SSL and drain selection signal DSL rise to α × Vers due to the coupling between the channels of the source selection transistor TRa and the drain selection transistor TRb, which turns on the voltage of the common source line CSL (see t 12).
On the other hand, the floating even bit line BLe and the floating odd bit line BLo are also raised to approximately Vers-Vt by charge injection between the WELLs WELL (see t 13).
The floating even discharge signal DISCHe and the floating odd discharge signal DISCHo are raised to α × Vers by the coupling between the channels of the even discharge transistor TRDe and the odd discharge transistor TRDo, which turns on the voltage of the common source line CSL (see t 14).
That is, the voltages between the gates and the channels of the even discharge transistor TRDe and the odd discharge transistor TRDo are the same as the voltages between the gates and the channels of the source selection transistor TRa and the drain selection transistor TRb.
Therefore, the even discharge transistor TRDe and the odd discharge transistor TRDo can be formed to have gate films having the same thickness as that of the relatively thin source selection transistor TRa and drain selection transistor TRb.
Then, at a WELL discharge timing P2 following the erase timing P1, the voltage of the bulk WELL of the plurality of cell transistors MC <1: n > is controlled from the erase voltage Vers to "0" again.
Then, due to coupling or the like, the even bit line BLe and the odd bit line BLo are also lowered toward the ground voltage VSS side together with the common source line CSL, the source selection signal SSL, the drain selection signal DSL, the even discharge signal DISCHe, and the odd discharge signal DISCHo.
On the other hand, in the semiconductor memory device of the present invention, the charges that can remain on the even bit line BLe and the odd bit line BLo can be discharged by the page buffer PB and the like.
Fig. 5 is a diagram illustrating a part of the page buffer PB of the NAND flash memory device of fig. 2.
The page buffer PB includes a detection transistor 10, a discharge transistor 20, and a transmission transistor 30.
In this case, the even bit line BLe and the odd bit line BLo electrically connected to the page buffer PB may be discharged to the power supply voltage VCC by the sensing transistor 10 and the discharging transistor 20.
The even bit line BLe and the odd bit line BLo electrically connected to the page buffer PB are discharged to the ground voltage VSS through the sensing transistor 10 and the transfer transistor 30.
The operation of the page buffer PB can be easily performed by a person skilled in the art. Therefore, in this specification, a detailed description thereof will be omitted.
In order to solve the above problems, in the NAND flash memory device of the present invention having the above-described configuration, the even discharge transistor TRDe and the odd discharge transistor TRDo may be implemented by low-voltage transistors having gate films with the same thickness as that of the source selection transistor TRa and the drain selection transistor TRb.
Thus, according to the NAND flash memory device of the present invention, the number of required high voltage transistors is significantly reduced. Finally, according to the NAND flash memory device of the present invention, the layout area required as a whole is significantly reduced.
While the present invention has been described with reference to an embodiment shown in the drawings, the embodiment is illustrative only, and various modifications and equivalent embodiments can be made by those skilled in the art. Therefore, the true technical scope of the present invention should be defined by the technical idea of the appended claims.
Claims (4)
1. A NAND flash memory device, comprising:
an even bit line;
odd bit lines;
a common source line;
a memory array including even cell strings and odd cell strings, each of the even cell strings and the odd cell strings including a plurality of cell transistors, a source selection transistor, and a drain selection transistor, the plurality of cell transistors being arranged in a NAND string, the source selection transistor being driven in response to a source selection signal so as to connect one-side junctions of the cell transistors arranged at one ends of the plurality of cell transistors to the common source line, the drain selection transistor being driven in response to a drain selection signal so as to connect one-side junctions of the cell transistors arranged at the other ends of the plurality of cell transistors to the corresponding even bit lines and odd bit lines;
an even discharge transistor which responds to an even discharge signal and of which one side junction is connected to the even bit line; and
an odd discharge transistor responsive to an odd discharge signal and having one side junction thereof connected to the odd bit line,
wherein the other side junction of the even discharge transistor and the other side junction of the odd discharge transistor are connected to the common source line, respectively.
2. The NAND flash memory device of claim 1 wherein the gate films of the even discharge transistor and the odd discharge transistor are formed to have the same thickness as the gate films of the source select transistor and the drain select transistor.
3. The NAND flash memory device of claim 1 further comprising:
an even selection transistor having a gate film thicker than the even discharge transistor, one side junction connected to the even bit line and turned on in response to an even selection signal;
an odd select transistor having one side junction connected to the odd bit line and turned on in response to an odd select signal, and formed to have a gate film thicker than the odd discharge transistor; and
and a page buffer which is driven to store the signal of the even bit line and the signal of the odd bit line transmitted through the even selection transistor and the odd selection transistor.
4. The NAND flash memory device of claim 3 wherein the page buffer is driven so as to discharge the charges on the even bit lines and the odd bit lines.
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| KR10-2018-0108681 | 2018-09-12 | ||
| KR1020180108681A KR102090874B1 (en) | 2018-09-12 | 2018-09-12 | Nand flash memory device reducing the number of high voltage transistor |
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| CN109727988A CN109727988A (en) | 2019-05-07 |
| CN109727988B true CN109727988B (en) | 2020-10-02 |
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| US6235586B1 (en) * | 1999-07-13 | 2001-05-22 | Advanced Micro Devices, Inc. | Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications |
| US6480419B2 (en) | 2001-02-22 | 2002-11-12 | Samsung Electronics Co., Ltd. | Bit line setup and discharge circuit for programming non-volatile memory |
| KR100630535B1 (en) * | 2004-03-23 | 2006-09-29 | 에스티마이크로일렉트로닉스 엔.브이. | Method of reading multi level NAND flash memory cell and circuit for the same |
| US7379333B2 (en) * | 2004-10-28 | 2008-05-27 | Samsung Electronics Co., Ltd. | Page-buffer and non-volatile semiconductor memory including page buffer |
| KR20080039107A (en) * | 2006-10-31 | 2008-05-07 | 주식회사 하이닉스반도체 | Nand type flash memory device with page buffer and method for reading data of the same |
| KR100816123B1 (en) * | 2007-01-02 | 2008-03-21 | 주식회사 하이닉스반도체 | Nand flash memory device |
| KR100826653B1 (en) * | 2007-04-06 | 2008-05-06 | 주식회사 하이닉스반도체 | Erase verify method of nand flash memory device |
| KR20100013954A (en) * | 2008-08-01 | 2010-02-10 | 주식회사 하이닉스반도체 | Method of testing a semiconductor memory device |
| KR101049663B1 (en) * | 2009-06-08 | 2011-07-14 | 주식회사 하이닉스반도체 | Page buffer circuit, nonvolatile memory device having same, and operating method thereof |
| KR20130019242A (en) * | 2011-08-16 | 2013-02-26 | 에스케이하이닉스 주식회사 | Semiconductor device and methof of manufacturing the same |
| CN103035293B (en) * | 2011-10-08 | 2015-07-15 | 华邦电子股份有限公司 | Semiconductor storage device |
| CN105989886B (en) * | 2015-02-16 | 2019-09-17 | 华邦电子股份有限公司 | Nonvolatile semiconductor memory device |
| US9830961B2 (en) * | 2015-09-29 | 2017-11-28 | Toshiba Memory Corporation | Nonvolatile semiconductor storage device including a discharge transistor for discharging a bit line to a source line |
| KR102068190B1 (en) * | 2018-03-20 | 2020-01-20 | 도실리콘 씨오., 엘티디. | Program method of nand flash memory device |
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| KR102090874B1 (en) | 2020-03-18 |
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