TW202011585A - An NAND flash memory device for reducing the number of high-voltage transistors - Google Patents

Abstract

The invention discloses an NAND flash memory device for reducing the number of high-voltage transistors. The NAND flash memory device comprises: even bit lines; odd bit lines; common source lines; a memory array that comprises an even unit string and an odd unit string, each of the even unit string and the odd unit string comprises a plurality of unit transistors, a source selection transistor and a drain selection transistor, wherein the plurality of unit transistors are configured in the form of NAND strings; the source selection transistor is driven in a manner that one side joint part arranged at one ends of the unit transistors is connected with the common source line, and the drain selection transistor is driven in a manner that one side joint part arranged at the other ends of the unit transistors is connected with the corresponding even bit line and the corresponding odd bit line; the device also has: an even discharge transistor that is driven so that the even bit line and the common source line are connected to each other; and an odd discharge transistor that is driven so that the odd bit line and the common source line are connected to each other. The NAND flash memory device of the present invention reduces the overall layout area by reducing the number of high-voltage transistors.

Description

NAND flash memory device with reduced number of high voltage transistors

The present invention relates to a NAND flash memory device, and in particular, to a NAND flash memory device that can reduce the number of high-voltage transistors.

The NAND flash memory device can store data even when power is not supplied, and can eliminate multiple unit transistors of the selected block at a time.

FIG. 1 is a diagram showing a conventional NAND flash memory device. In order to achieve high integration, the NAND flash memory device constitutes a plurality of N-channel-shaped cell transistors MC<1:n> including a control gate and a floating gate to connect strings STRe and STRo in series. At this time, in the above-mentioned strings STRe and STRo, the plurality of unit transistors MC<1:n> pass through the source selection transistor TRa and the drain selection transistor TRb arranged on both sides and the common source line CSL and the even bit line BLe , BLo odd bit line electrical connection.

At this time, the typical NAND flash memory device eliminates work by applying a low or negative voltage to the control gates of a plurality of cell transistors MC<1:n>, applying a voltage of about 20V High voltage is applied to the well WELL for execution. In this case, the voltages of the even bit line BLe and the odd bit line BLo connected to the strings STRe and STRo can rise to about 20V. Then, the even bit line BLe and the odd bit line BLo after the erasing operation are discharged to the bias voltage VBIAS through the plurality of discharge transistors TRDe and TRDo that are gated with the plurality of discharge signals DISCHE and DISCHo.

On the other hand, in a NAND flash memory device, a considerable number of transistors have a gate film having the same thickness as the source selection transistor TRa and the drain selection transistor TRb, and a power supply voltage of about 2.3 V at the gate terminal VDD for control. In this case, when such multiple transistors are directly connected to the even bit line BLe and the odd bit line BLo rising to about 20V, the gate film may be damaged.

Therefore, in the conventional NAND flash memory device of FIG. 1, in order to prevent such damage to the gate film, the plurality of discharge transistors TRDe and TRDo connected to the even bit line BLe and the odd bit line BLo are formed by the gate film. The thickness of the high-voltage transistor is thick. For reference, even selection transistors TRSe and odd selection transistors TRSo gated by the even selection signal BSLe and the odd selection signal BSLo are also constituted by high voltage transistors.

However, in the case of such a high-voltage transistor, the required layout area is very large, which is a burden of high integration of the NAND flash memory device.

Therefore, the NAND flash memory device needs to reduce the number of high-voltage transistors used.

Prior art document: Korean Patent Publication No. 10-2002-0069092, publication date: August 29, 2002.

An object of the present invention is to provide a NAND flash memory device that reduces the number of high-voltage transistors required to reduce the overall layout area.

An embodiment of the present invention for achieving the above object relates to a NAND flash memory device. The NAND flash memory device of the present invention includes: even bit lines; odd bit lines; common source lines; memory array, including even cell strings and odd cell strings, the even cell strings and the odd cell strings respectively include a plurality of cell transistors , A source selection transistor and a drain selection transistor, the plurality of unit transistors are arranged in the form of a NAND string, the source selection transistor is responsive to a source selection signal to make the unit transistors arranged at one end of the plurality of unit transistors Is connected to the common source line, and the drain selection transistor is responsive to the drain selection signal to make the side junction of the unit transistor disposed at the other end of the plurality of unit transistors Driving in a manner connected to the corresponding even-numbered bit lines and odd-numbered bit lines; an even discharge transistor driven in a manner to connect the even-numbered bit lines to the common source line in response to an even discharge signal; and The odd discharge transistor drives the odd bit line and the common source line in response to the odd discharge signal.

In the NAND flash memory device of the present invention configured as described above, the other side of the plurality of discharge transistors is connected to the common source line. Therefore, the plurality of discharge transistors may be realized by a low-voltage transistor having a gate film having the same thickness as that of the source selection transistors and the drain selection transistors. Finally, according to the NAND flash memory device of the present invention, the overall required layout area is greatly reduced by reducing the number of high-voltage transistors required.

In order to fully understand the advantages of the present invention and the actions of the present invention and the objects achieved by the implementation of the present invention, please refer to the drawings and the contents described in the drawings illustrating preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described here, and can be embodied in other ways. Rather, the embodiments described herein are provided for a thorough and complete understanding of the disclosure and to fully convey the idea of the present invention to those of ordinary skill.

On the other hand, in this specification, for the same structure and structural elements that perform the same function, the same reference signs are added within the <>. At this time, these structural elements are collectively referred to by reference numerals. And, when it is necessary to distinguish them separately, "<>" is added behind the reference sign.

In the process of explaining the content of the present invention through the entire specification, the meanings of the terms “electrically connected”, “connected”, and “coupled” between the various structural elements include not only the case of direct connection, but also the use of When the attributes are maintained at a level above a predetermined level and connected through an intermediate medium. Terms such as "delivery" and "derived" of each signal include not only the direct meaning, but also the indirect meaning of maintaining the state of the signal above a prescribed level through the intermediate medium. Throughout the specification, other terms such as "apply", "import", "input" voltage or signal are also used in the same meaning.

In order to fully understand the operational advantages of the present invention and the objects achieved by the embodiments of the present invention, the following contents describing the exemplary embodiments of the present invention and the contents described in the drawings must be referred to together.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

2 is a diagram showing a NAND flash memory device according to an embodiment of the present invention.

First, before describing an embodiment of the NAND flash memory device of the present invention, the structure of the MOS transistor used in the NAND flash memory device of the present invention will be described.

FIG. 3 is a diagram for explaining the structure of a MOS transistor used in the NAND flash memory device of FIG. 2. For reference, it should be understood that in order to clearly show each layer (or film) and region, the thickness and length are shown enlarged or reduced in FIG. 3.

Referring to FIG. 3, MOS transistors used in the NAND flash memory device of the present invention are roughly divided into a low voltage transistor LVTR and a high voltage transistor HVTR.

The low-voltage transistor LVTR and the high-voltage transistor HVTR are formed in respective wells WELL, and have respective gate electrodes ELGT1, ELGT2 and gate films MGT1, MGT2.

At this time, the gate film MGT1 of the low voltage transistor LVTR is relatively thin, and the gate film MGT2 of the high voltage transistor HVTR is relatively thick.

However, when the voltage between the channels CHN1 and CHN2 formed in the well WELL and the gate electrodes ELGT1 and ELGT2 is large, the high-voltage transistor HVTR has the possibility of damaging the gate film compared to the low-voltage transistor LVTR Very low advantages.

However, compared with the above-mentioned low-voltage transistor LVTR, the above-mentioned high-voltage transistor HVTR has a disadvantage that the area required for layout is large.

Therefore, in order to reduce the overall required area of the NAND flash memory device, it is particularly important to reduce the number of high-voltage transistors required.

Referring again to FIG. 2, the NAND flash memory device of the present invention includes even bit line BLe, odd bit line BLo, common source line CSL, memory array MARR, even discharge transistor TRDe, and odd discharge transistor TRDo.

The memory array MARR includes an even cell string STRe and an odd cell string STRo, and the even cell string STRe and the odd cell string STRo respectively include a plurality of cell transistors MC<1:n> arranged on a well WELL of a semiconductor substrate, source selection The transistor TRa and the drain selection transistor TRb.

At this time, the plurality of cell transistors MC<1:n> are arranged in the form of NAND strings and controlled by the corresponding word lines WL<1:n>. Also, the source selection transistor TRa and the drain selection transistor TRb are realized by a low-voltage transistor LVTR having a gate film with a relatively thin thickness.

The source selection transistor TRa is responsive to the source selection signal SSL so that one side junction of the unit transistor MC<n> disposed at one end of the plurality of unit transistors MC<1:n> and the common source line Driven by CSL connection. In addition, the drain selection transistor TRb is responsive to the drain selection signal DSL so that the one-side junction of the unit transistor MC<1> disposed at the other end of the plurality of unit transistors MC<1:n> is coupled to the dual The digital bit line BLe and the odd bit line BLo are connected and driven.

The even discharge transistor TRDe is driven in such a manner as to connect the even bit line BLe and the common source line CSL in response to the even discharge signal DISCHE.

In addition, the odd discharge transistor TRDo is driven to connect the odd bit line BLo and the common source line CSL in response to the odd discharge signal DISCHo.

Preferably, the above NAND flash memory device of the present invention further includes an even selection transistor TRSe, an odd selection transistor TRSo, and a page buffer PB.

The even selection transistor TRSe and the odd selection transistor TRSo are driven to selectively transmit one of the even bit line BLe and the odd bit line BLo to the page buffer PB.

That is, one side junction of the even selection transistor TRSe is connected to the even bit line BLe, opens in response to the even selection signal BLSe, and buffers the signal of the even bit line BLe to the paging buffer through the common bit line BLCM PB transmission.

In addition, one side junction of the odd selection transistor TRSo is connected to the odd bit line BLo, and is opened in response to the odd selection signal BLSo and the signal of the odd bit line BLo is paged to the paging through the common bit line BLCM Buffer PB transmission.

At this time, it is preferable that the even selection transistor TRSe and the odd selection transistor TRSo have a relatively thick gate film, that is, a high voltage of the gate film thicker than the source selection transistor TRa and the drain selection transistor TRb The transistor HVTR is formed. In this case, it is possible to prevent the even selection transistor TRSe and the odd selection transistor TRSo from being damaged by the rising voltages of the even bit line BLe and the odd bit line BLo in the elimination operation described later.

The paging buffer PB is driven to store the signals of the even bit lines and the odd bit lines BLo transmitted through the even selection transistor TRSe and the odd selection transistor TRSo.

In the NAND flash memory device having the structure as described above, the even discharge transistor TRDe and the odd discharge transistor TRDo may be formed by a relatively thin gate film, that is, having a same thickness as the source selection transistor TRa and the drain selection transistor TRb The low-voltage transistor LVTR of the gate film having the same thickness is realized, and the explanation will be continued.

4 is a timing chart for explaining the main signal and the voltage strength of a node during the erasing operation of the NAND flash memory device of FIG. 2.

First, the principle of erasing a plurality of cell transistors MC<1:n> in the NAND flash memory device of the present invention is explained as follows.

In the erasing timing P1 of the erasing operation, the plurality of word lines WL<1:n> applied to the control gates of the plurality of cell transistors MC<1:n> of the plurality of cell strings STRe, STRo are controlled to “0V”. Then, an erasing voltage (Vers, about “20V”) is applied to the bulk well WELL of the plurality of cell transistors MC<1:n>.

Then, the net charge trapped in the floating gate between the bulk well WELL existing in the plurality of cell transistors MC<1:n> and the control gate is transferred to the well WELL. Thus, the threshold voltage Vt of the plurality of cell transistors MC<1:n> is lowered. In addition, when the threshold voltage Vt is sufficiently reduced to apply "0V" to the control gate and source of the cell transistor MC<1:n> and a positive voltage is applied to the drain, the cell transistor MC<1:n> conducts the channel Current. The cell transistor MC<1:n> having the low critical voltage as described above is called an “erased cell” or “erased state”, and has a data value of “1”.

In this case, the floating common source line CSL rises to about Vers-Vt by charge injection between the wells WELL (refer to reference symbol t11).

In addition, the floating source selection signal SSL and the drain selection signal DSL rise to α by the coupling between the channels of the source selection transistor TRa and the drain selection transistor TRb that conduct the voltage of the common source line CSL ×Vers (refer to reference t12).

On the other hand, the floating even bit line BLe and the odd bit line BLo also rise to about Vers-Vt by the charge injection between the wells WELL (refer to reference number t13).

In addition, the floating even discharge signal DISCHEe and odd discharge signal DISCHo rise to α×Vers through the coupling between the channels of the even discharge transistor TRDe and the odd discharge transistor TRDo that turn on the voltage of the common source line CSL (see Label t14).

That is, the voltage between the gate and the channel in the even discharge transistor TRDe and the odd discharge transistor TRDo is the same as the voltage between the gate and the channel in the source selection transistor TRa and the drain selection transistor TRb.

Therefore, the even discharge transistor TRDe and the odd discharge transistor TRDo can be formed with a gate film having the same thickness as that of the relatively thin source selection transistor TRa and the drain selection transistor TRb.

Then, at the well discharge timing P2 performed following the erasing timing P1, the voltages of the bulk wells WELL of the plurality of cell transistors MC<1:n> are controlled from the erasing voltage Vers to "0" again.

Then, due to coupling, etc., together with the common source line CSL, the source selection signal SSL, the drain selection signal DSL, the even discharge signal DISCHE and the odd discharge signal DISSCHo, the even bit line BLe and the odd The digital line BLo also drops toward the ground voltage VSS side.

On the other hand, in the semiconductor memory device of the present invention, the charges that can remain on the even bit line BLe and the odd bit line BLo can also be discharged by the page buffer PB or the like.

FIG. 5 is a diagram showing a part of the paging buffer PB of the NAND flash memory device of FIG. 2.

The page buffer PB described above includes a detection transistor 10, a discharge transistor 20, and a transfer transistor 30.

In this case, the even bit line BLe and the odd bit line BLo electrically connected to the page buffer PB can be discharged to the power supply voltage VCC through the detection transistor 10 and the discharge transistor 20.

Moreover, the even bit line BLe and the odd bit line BLo electrically connected to the page buffer PB can be discharged to the ground voltage VSS through the detection transistor 10 and the transfer transistor 30.

As long as an ordinary technician can easily realize the work of this paging buffer PB. Therefore, in this specification, a detailed description related to this will be omitted.

In the NAND flash memory device of the present invention having the above-described structure, the even discharge transistor TRDe and the odd discharge transistor TRDo may have a gate having the same thickness as that of the source selection transistor TRa and the drain selection transistor TRb The low voltage transistor of the polar film is realized.

Thus, according to the NAND flash memory device of the present invention, the number of high-voltage transistors required is significantly reduced. Finally, according to the NAND flash memory device of the present invention, the overall required layout area is significantly reduced.

The above description shows and describes several preferred embodiments of the present application, but as mentioned above, it should be understood that the present application is not limited to the form disclosed herein and should not be regarded as an exclusion from other embodiments, but can be used in various Other combinations, modifications, and environments can be modified within the scope of the application described herein, through the above teachings or techniques or knowledge in related fields. Changes and changes made by those skilled in the art without departing from the spirit and scope of this application should be within the scope of protection of the scope of patent applications attached to this application.

BLe: even bit line BLo: odd bit line CSL: common source line MARR: memory array TRDe: even discharge transistor TRDo: odd discharge transistor STRe: even cell string STRo: odd cell string MC＜1＞…MC＜n >: Unit transistor TRa: Source selection transistor TRb: Drain selection transistor WL<1>...WL<n>: Word line SSL: Source selection signal DSL: Drain selection signal DISCHE: Even discharge signal DISSCHo: Odd discharge signal TRSe: even selection transistor TRSo: odd selection transistor PB: paging buffer BLCM: common bit line LVTR: low voltage transistor HVTR: high voltage transistor WELL: well ELGT1, ELGT2: gate electrodes MGT1, MGT2: gate film CHN1 CHN2: channel P1: elimination timing P2: well discharge timing 10: detection transistor 20: discharge transistor 30: transfer transistor VCC: power supply voltage VSS: ground voltage BLSe: even selection signal BLSo: odd selection signal

A brief description of the drawings used in the present invention is provided. FIG. 1 is a diagram showing a conventional NAND flash memory device. 2 is a diagram showing a NAND flash memory device according to an embodiment of the present invention. 3 is a diagram for explaining the structure of a MOS transistor used in the NAND flash memory device of FIG. 2. 4 is a timing chart for explaining the main signal and the voltage strength of a node during the erasing operation of the NAND flash memory device of FIG. 2. FIG. 5 is a diagram showing a part of the paging buffer PB of the NAND flash memory device of FIG. 2.

BLe: even bit line

BLo: odd bit line

CSL: common source line

MARR: storage array

TRDe: even discharge transistor

TRDo: odd discharge transistor

STRe: even unit string

STRo: odd cell string

MC<1>...MC<n>: cell transistor

TRa: source selection transistor

TRb: drain select transistor

WL<1>...WL<n>: word line

SSL: source selection signal

DSL: drain select signal

DISCHe: even discharge signal

DISCHo: odd discharge signal

TRSe: even select transistor

TRSo: odd selection transistor

PB: paging buffer

BLCM: common bit line

BSLe: even selection signal

BSLo: odd selection signal

Claims (4)

A NAND flash memory device, comprising: even bit lines; odd bit lines; common source lines; memory array, including even cell strings and odd cell strings, the even cell strings and the odd cell strings respectively include multiple A plurality of unit transistors, a source selection transistor and a drain selection transistor, the plurality of unit transistors are arranged in the form of a NAND string, and the source selection transistor is responsive to a source selection signal so that one end of the plurality of unit transistors is arranged One junction of the unit transistor is driven to be connected to the common source line, and the drain selection transistor responds to a drain selection signal to make one of the unit transistors disposed at the other end of the plurality of unit transistors The side junctions are driven in such a manner as to connect the corresponding even bit lines and odd bit lines; even discharge transistors, in response to the even discharge signal, to connect the even bit lines to the common source line Driving; and odd discharge transistors, in response to the odd discharge signal, to drive the odd bit lines and the common source lines in a manner to connect. The NAND flash memory device according to claim 1, wherein the gate films of the even discharge transistor and the odd discharge transistor have a gate film that is identical to the gate film of the source select transistor and the gate film of the drain select transistor The thickness is formed by the same thickness. The NAND flash memory device according to claim 1, characterized in that the NAND flash memory device further comprises: an even selection transistor, and one side junction is connected to the even bit line and opens in response to an even selection signal to have a ratio The above-mentioned even discharge transistor is formed with a thicker gate film; an odd selection transistor, one side junction is connected to the odd bit line and opened in response to an odd selection signal to have a thicker gate than the odd discharge transistor A polar film is formed; and a page buffer is driven to store the signals of the even bit lines and the signals of the odd bit lines transmitted through the even selection transistors and the odd selection transistors. The NAND flash memory device according to claim 3, wherein the page buffer is driven to be able to discharge the charges of the even bit lines and the odd bit lines.

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