US20070166889A1 - Method of forming a well of a NAND flash memory device - Google Patents
Method of forming a well of a NAND flash memory device Download PDFInfo
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- US20070166889A1 US20070166889A1 US11/702,698 US70269807A US2007166889A1 US 20070166889 A1 US20070166889 A1 US 20070166889A1 US 70269807 A US70269807 A US 70269807A US 2007166889 A1 US2007166889 A1 US 2007166889A1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000007943 implant Substances 0.000 claims description 11
- 238000007599 discharging Methods 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 description 8
- 239000000872 buffer Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Definitions
- the disclosure generally relates to a NAND flash memory device and to a method of forming a well of the NAND flash memory device, and more particularly, to a well formed in a cell region of a NAND flash memory device.
- a cell is erased through a F-N tunneling phenomenon.
- the NAND flash memory cell is formed on a single P well.
- a number of the cells are constructed in a string shape to form a cell string.
- a number of the cell strings are arranged in the longitudinal or lateral direction to form a cell block. Accordingly, an erase operation is performed by the cell block.
- FIGS. 1A and 1B are conceptual views shown to explain a conventional erase operation.
- a voltage of 0V is applied to a word line W/L of a selected cell block through a string select transistor SSL.
- a word line W/L of a non-selected cell block is floated through the string select transistor SSL.
- the cell is erased since a voltage difference between a gate electrode and a well of a memory cell within the selected cell block is too great (see FIG. 1A ) and the gate electrode of the memory cell within the non-selected cell block is boosted to reduce the voltage difference between the word line W/L and the well. The cell is thus not erased (see FIG. 1B ).
- the non-selected cell block since a voltage of 20V or more is generally applied to the P well, the non-selected cell block also undergoes stress due to the same bias. Further, there exists the leakage current due to a string select transistor for floating the word line of the non-selected cell block. The word line of the non-selected cell block does not keep floated due to this leakage. As a result, there is a problem in that the status of data is not kept since a shallow erase phenomenon occurs. In addition, there is a problem in that specifications of a target device are not met because erase disturbance is caused.
- a NAND flash memory device and a method of forming a well in the NAND flash memory device.
- wells are divided and formed by a cell block, whereby a stress time for the cell block is reduced to prevent erase disturbance.
- the NAND flash memory device includes a triple N well formed within a semiconductor substrate to electrically protect a number of memory cells in a predetermined region of the semiconductor substrate.
- the device also includes two or more triple P wells formed within the triple N well, and a number of cell blocks having a number of memory cell strings. The cell blocks are respectively formed on the triple P wells and share a number of bit lines, respectively.
- a NAND flash memory device includes a semiconductor substrate in which a memory cell region and a peripheral region are defined. Such a device also includes one or more triple N wells formed within the memory cell region of the semiconductor substrate to electrically protect a number of memory cells, wells for peripheral devices formed within the peripheral region of the semiconductor substrate, one or more triple P wells formed within the triple N wells, a number of cell blocks formed on the triple P wells, respectively, wherein each of the cell blocks has a number of memory cell strings sharing a number of bit lines, and a number of transistors formed on the wells for the peripheral devices.
- the method of forming a well of a NAND flash memory device includes forming a first mask through which the entire cell region is opened or the cell region is opened as much as a multiple of 2 or 3 on a P-type semiconductor substrate.
- the method also includes performing a N-type ion implant process using the first mask as an ion implant mask to form a triple N well within the P-type semiconductor substrate, forming a second mask through which the entire triple N well region of the semiconductor substrate in which the triple N well is formed is opened or the triple N well region is opened as much as a multiple of 2 or 3, and performing a P-type ion implant process using the second mask as an ion implant mask to form a triple P well within the triple N well.
- FIGS. 1A and 1B are conceptual views shown to explain a conventional erase operation
- FIGS. 2A and 2B are conceptual views shown to explain a NAND flash memory device according to the present invention.
- FIG. 3 is a graph showing the relationship between an erase time and an erase speed
- FIGS. 4A and 4B are cross-sectional views for explaining a method of a well in a NAND flash device according to the present invention.
- FIGS. 2A and 2B are conceptual views shown to explain a NAND flash memory device according to the present invention.
- the NAND flash memory device may include a triple N well 20 formed in a semiconductor substrate in order to electrically protect a number of memory cells in a given region of the semiconductor substrate, two or more triple P wells 30 formed within the triple N well 20 , and a number of cell blocks 40 a to 40 n having a number of memory cell strings, wherein the cell blocks are formed on the plurality of the triple P wells 30 and have a number of bit lines B/L, respectively.
- the NAND flash memory device may include a semiconductor substrate in which a memory cell region and a peripheral region are defined, one or more triple N wells 20 formed in the semiconductor substrate in order to electrically protect a number of memory cells in a given region of the semiconductor substrate, a well for peripheral devices (not shown) formed in a peripheral region of the semiconductor substrate, one or more triple P wells 30 which are respectively formed within the triple N wells 20 , a number of cell blocks 40 a to 40 n having a number of memory cell strings, wherein the cell blocks are formed on the plurality of the triple P wells 30 and have a number of bit lines B/L, respectively, and a number of transistors (not shown) formed on wells for the peripheral devices.
- Each of the cell blocks 40 a to 40 n includes a number of string select transistors (not shown) which are connected to the plurality of the bit lines B/L, respectively, and are driven according to a local string select signal, a number of source select transistors (not shown) which are connected to a common source line (not shown) and are driven according to a local source select signal (not shown), a number of cell strings in which a number of memory cells are connected in a string shape, wherein the cell strings are connected between the string select transistors (not shown) and source select transistors, respectively, and a number of word lines (not shown) connected to gate terminals within the cell string, respectively.
- the NAND flash memory device may further include page buffer units 50 which are connected to the number of bit lines B/L, respectively, for applying a given program voltage or a read voltage to the bit lines B/L according to an external control signal.
- the page buffer unit 50 preferably includes a number of page buffers, which are located at the top and bottom of the cell region and each share two even and odd bit lines.
- the cell blocks as many as the number of 10242 may share the number of the bit lines B/L, respectively. That is, the string select transistors at the same location within the 1st to 2047th cell blocks are connected to the same bit line. For example, it is assumed that there are 1024 bit lines and 1024 string select transistors exist within each of the cell blocks. The 1st string select transistors within each of the cell blocks are connected to the 1st bit line and the 1024th string select transistors are connected to the 1024th bit line. Further, the triple P wells 30 can be divided in a variety of shapes and the number of the cell blocks existing within the triple P wells may vary.
- the triple P wells 30 are divided in a multiple of 2 or 3 and are formed. If the triple N well 20 is one or more, the triple P wells 30 are preferably divided in a multiple of 1, 2 or 3 and are formed. Also,. the triple N wells can be divided in a multiple of 1 or 2 and are formed. Moreover, the number of the cell blocks 40 located within one triple P well 30 is divided in a multiple of 2 or 3 of a total of the cell blocks 40 a to 40 n . In other words, if the triple P wells 30 are divided into 2 , the entire cell blocks 40 a to 40 n are divided into 1 ⁇ 2 and are respectively located on the triple P wells 30 by 1 ⁇ 2. The triple P wells are formed on the cell regions that are divided into 2, respectively.
- the well of the cell array has a structure in which the triple N well 20 is formed in a P-type semiconductor substrate and the triple P wells 30 to be used as a bulk of the cell array is formed within the triple N well 20 , so that the triple P wells 30 are electrically isolated from the P substrate of the same type in a P-N diode mode. Accordingly, electrons of the floating gate are emitted by high voltages of different potentials by applying a voltage of 0V to the word lines and a high voltage of over 20V to the bulk during an erase operation.
- 2048 cell blocks 40 a to 40 n are connected to the same global bit line in parallel and the triple P wells 30 are divided to form two triple P wells 30 . Then, if 1024 blocks are positioned in one triple P well 30 and the P wells are coded individually, the stress time reduces to 1 ⁇ 2. If 4 triple P wells 30 are formed, the stress time reduces to 1 ⁇ 4. If the P well 30 is divided, the block is also divided into 1024 in number. Accordingly, during the erase operation, a P well 30 having a selected block undergoes stress since it is applied with 20V. However, a P well 30 not having a selected block does not experience stress since it is applied with 0V.
- FIG. 3 is a graph showing the relationship between an erase time and an erase speed. As shown in FIG. 3 , whenever the stress time reduces to 1 ⁇ 2, an erase time reduces about 0.3V. It is thus possible to prevent disturbance due to erase stress. Moreover, since the triple P wells 30 are divided, capacitance between the triple P wells 30 and the triple N well 20 reduces. Thus, an overall erase time budget can be reduced because well bias charging and discharging time reduce.
- FIGS. 4A and 4B are cross-sectional views for explaining the method of the well in the NAND flash device according to the present invention.
- a first mask (not shown) for ion implant through which a given cell region is opened is formed on a P-type semiconductor substrate 10 .
- a N-type ion implant process is performed to form triple N wells 20 within the P-type semiconductor substrate 10 .
- the first mask may open the entire cell region or the cell region as much as a multiple of 2 or 3.
- the triple N wells 20 are formed in the entire cell region or the triple N wells 20 as much as a multiple of 2 or 3 are formed in the cell region.
- a second mask (not shown) through which the triple N wells 20 are opened is formed in the cell region of the semiconductor substrate 10 in which the triple N wells 20 are formed.
- a P-type ion implant process is performed to form triple P wells 30 within the triple N wells 20 .
- the second mask can open the entire triple N well 20 region or the triple N well 20 region as much as a multiple of 2 or 3.
- a single triple N well 20 can be formed in the cell region of the P-type semiconductor substrate 10 and two triple P wells 30 can be formed within the triple N well 20 .
- two triple N wells 20 can be formed in the cell region of the P-type semiconductor substrate 10 and the triple P wells 30 can be formed within the two triple N wells 20 , respectively.
- a P well (not shown) for low voltage NMOS and an N well (not shown) for low voltage PMOS can be formed in a region where a low voltage device will be formed through a subsequent process.
- a tunnel oxide film (not shown), a floating gate (not shown), a dielectric film (not shown) and a control gate (not shown) are formed on the triple P well 30 through predetermined processes, thereby forming flash memory cells. (not shown).
- Interlayer insulating films (not shown) for isolating the flash memory cells are formed. The interlayer insulating films are patterned to form contact plugs (not shown) and bit lines are then formed on the contact plugs.
- triple wells of a NAND flash memory device are formed within a cell region in plural.
- a cell block including flash memory cells is formed on the triple wells. Accordingly, during an erase operation of a flash memory device, a stress time for non-selected blocks can be reduced and erase disturbance can be prevented, through the plurality of the wells. Further, as triple P wells are divided, capacitance between the triple P wells and the triple N well reduces. Therefore, well bias charging and discharging time can be reduced and an overall erase time budget can be thus reduced.
Abstract
Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple wells. Accordingly, during an erase operation of a flash memory device, a stress time for non-selected blocks can be reduced and erase disturbance can be also prevented, through the plurality of the wells. Further, capacitance between the triple P wells and the triple N well is reduced since triple P wells are divided. Therefore, well bias charging and discharging time can be reduced and an overall erase time budget can be thus reduced.
Description
- 1. Field of the Disclosure
- The disclosure generally relates to a NAND flash memory device and to a method of forming a well of the NAND flash memory device, and more particularly, to a well formed in a cell region of a NAND flash memory device.
- 2. Brief Description of Related Technology
- Generally, in a NAND flash memory device, a cell is erased through a F-N tunneling phenomenon. The NAND flash memory cell is formed on a single P well. A number of the cells are constructed in a string shape to form a cell string. A number of the cell strings are arranged in the longitudinal or lateral direction to form a cell block. Accordingly, an erase operation is performed by the cell block.
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FIGS. 1A and 1B are conceptual views shown to explain a conventional erase operation. Referring toFIGS. 1A and 1B , a voltage of 0V is applied to a word line W/L of a selected cell block through a string select transistor SSL. A word line W/L of a non-selected cell block is floated through the string select transistor SSL. If a high voltage is applied to a P well, the cell is erased since a voltage difference between a gate electrode and a well of a memory cell within the selected cell block is too great (seeFIG. 1A ) and the gate electrode of the memory cell within the non-selected cell block is boosted to reduce the voltage difference between the word line W/L and the well. The cell is thus not erased (seeFIG. 1B ). - However, since a voltage of 20V or more is generally applied to the P well, the non-selected cell block also undergoes stress due to the same bias. Further, there exists the leakage current due to a string select transistor for floating the word line of the non-selected cell block. The word line of the non-selected cell block does not keep floated due to this leakage. As a result, there is a problem in that the status of data is not kept since a shallow erase phenomenon occurs. In addition, there is a problem in that specifications of a target device are not met because erase disturbance is caused.
- Disclosed herein are a NAND flash memory device and a method of forming a well in the NAND flash memory device. Generally, in a region where a NAND flash memory cell will be formed, wells are divided and formed by a cell block, whereby a stress time for the cell block is reduced to prevent erase disturbance.
- The NAND flash memory device includes a triple N well formed within a semiconductor substrate to electrically protect a number of memory cells in a predetermined region of the semiconductor substrate. The device also includes two or more triple P wells formed within the triple N well, and a number of cell blocks having a number of memory cell strings. The cell blocks are respectively formed on the triple P wells and share a number of bit lines, respectively.
- According to another embodiment, a NAND flash memory device includes a semiconductor substrate in which a memory cell region and a peripheral region are defined. Such a device also includes one or more triple N wells formed within the memory cell region of the semiconductor substrate to electrically protect a number of memory cells, wells for peripheral devices formed within the peripheral region of the semiconductor substrate, one or more triple P wells formed within the triple N wells, a number of cell blocks formed on the triple P wells, respectively, wherein each of the cell blocks has a number of memory cell strings sharing a number of bit lines, and a number of transistors formed on the wells for the peripheral devices.
- The method of forming a well of a NAND flash memory device includes forming a first mask through which the entire cell region is opened or the cell region is opened as much as a multiple of 2 or 3 on a P-type semiconductor substrate. The method also includes performing a N-type ion implant process using the first mask as an ion implant mask to form a triple N well within the P-type semiconductor substrate, forming a second mask through which the entire triple N well region of the semiconductor substrate in which the triple N well is formed is opened or the triple N well region is opened as much as a multiple of 2 or 3, and performing a P-type ion implant process using the second mask as an ion implant mask to form a triple P well within the triple N well.
- Additional features of the invention may become apparent to those skill in the art from a review of the following detailed description, taken in conjunction with the drawing figures and the appended claims.
- For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawings wherein:
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FIGS. 1A and 1B are conceptual views shown to explain a conventional erase operation; -
FIGS. 2A and 2B are conceptual views shown to explain a NAND flash memory device according to the present invention; -
FIG. 3 is a graph showing the relationship between an erase time and an erase speed; and -
FIGS. 4A and 4B are cross-sectional views for explaining a method of a well in a NAND flash device according to the present invention. - While the disclosed device and method are susceptible of embodiments in various forms, there are illustrated in the drawings (and will hereafter be described) specific embodiments, with the understanding that the disclosure and drawings are intended to be illustrative, and are not intended to limit the claimed invention to the specific embodiments described herein.
- Described below are the preferred embodiments according to the present invention will be described with reference to the accompanying drawings. Because the preferred embodiments are provided for the purpose that the ordinary skilled in the art are able to understand the present invention, they may be modified in various manners and the scope of the present invention is not limited by the preferred embodiments described later. Further, in the drawing, like reference numerals are used to identify the same or similar parts.
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FIGS. 2A and 2B are conceptual views shown to explain a NAND flash memory device according to the present invention. Referring toFIGS. 2A and 2B , according to an embodiment of the present invention, the NAND flash memory device may include a triple N well 20 formed in a semiconductor substrate in order to electrically protect a number of memory cells in a given region of the semiconductor substrate, two or moretriple P wells 30 formed within the triple N well 20, and a number ofcell blocks 40 a to 40 n having a number of memory cell strings, wherein the cell blocks are formed on the plurality of thetriple P wells 30 and have a number of bit lines B/L, respectively. - Further, according to another embodiment of the present invention, the NAND flash memory device may include a semiconductor substrate in which a memory cell region and a peripheral region are defined, one or more
triple N wells 20 formed in the semiconductor substrate in order to electrically protect a number of memory cells in a given region of the semiconductor substrate, a well for peripheral devices (not shown) formed in a peripheral region of the semiconductor substrate, one or moretriple P wells 30 which are respectively formed within thetriple N wells 20, a number ofcell blocks 40 a to 40 n having a number of memory cell strings, wherein the cell blocks are formed on the plurality of thetriple P wells 30 and have a number of bit lines B/L, respectively, and a number of transistors (not shown) formed on wells for the peripheral devices. - Each of the cell blocks 40 a to 40 n includes a number of string select transistors (not shown) which are connected to the plurality of the bit lines B/L, respectively, and are driven according to a local string select signal, a number of source select transistors (not shown) which are connected to a common source line (not shown) and are driven according to a local source select signal (not shown), a number of cell strings in which a number of memory cells are connected in a string shape, wherein the cell strings are connected between the string select transistors (not shown) and source select transistors, respectively, and a number of word lines (not shown) connected to gate terminals within the cell string, respectively.
- The NAND flash memory device may further include
page buffer units 50 which are connected to the number of bit lines B/L, respectively, for applying a given program voltage or a read voltage to the bit lines B/L according to an external control signal. Thepage buffer unit 50 preferably includes a number of page buffers, which are located at the top and bottom of the cell region and each share two even and odd bit lines. - In this embodiment, the cell blocks as many as the number of 10242 may share the number of the bit lines B/L, respectively. That is, the string select transistors at the same location within the 1st to 2047th cell blocks are connected to the same bit line. For example, it is assumed that there are 1024 bit lines and 1024 string select transistors exist within each of the cell blocks. The 1st string select transistors within each of the cell blocks are connected to the 1st bit line and the 1024th string select transistors are connected to the 1024th bit line. Further, the
triple P wells 30 can be divided in a variety of shapes and the number of the cell blocks existing within the triple P wells may vary. In this embodiment, if the triple N well 20 is one, it is preferred that thetriple P wells 30 are divided in a multiple of 2 or 3 and are formed. If the triple N well 20 is one or more, thetriple P wells 30 are preferably divided in a multiple of 1, 2 or 3 and are formed. Also,. the triple N wells can be divided in a multiple of 1 or 2 and are formed. Moreover, the number of the cell blocks 40 located within onetriple P well 30 is divided in a multiple of 2 or 3 of a total of the cell blocks 40 a to 40 n. In other words, if thetriple P wells 30 are divided into 2, the entire cell blocks 40 a to 40 n are divided into ½ and are respectively located on thetriple P wells 30 by ½. The triple P wells are formed on the cell regions that are divided into 2, respectively. - In a flash memory device of a NAND type in which an erase operation using a bulk bias is performed with the F-N tunneling method, the well of the cell array has a structure in which the
triple N well 20 is formed in a P-type semiconductor substrate and thetriple P wells 30 to be used as a bulk of the cell array is formed within the triple N well 20, so that thetriple P wells 30 are electrically isolated from the P substrate of the same type in a P-N diode mode. Accordingly, electrons of the floating gate are emitted by high voltages of different potentials by applying a voltage of 0V to the word lines and a high voltage of over 20V to the bulk during an erase operation. In this time, if there are 2048 blocks, there may be a 2047th non-selected block if the erase operation is performed in a block unit. That is, if a 1 pulse time for erasure is 2ms, 2047×2ms=41 sec. If enable cycling is 100K, the flash memory device undergoes stress during 4.1 Msec. - Therefore, according to the present invention, 2048
cell blocks 40 a to 40 n are connected to the same global bit line in parallel and thetriple P wells 30 are divided to form twotriple P wells 30. Then, if 1024 blocks are positioned in one triple P well 30 and the P wells are coded individually, the stress time reduces to ½. If 4triple P wells 30 are formed, the stress time reduces to ¼. If the P well 30 is divided, the block is also divided into 1024 in number. Accordingly, during the erase operation, a P well 30 having a selected block undergoes stress since it is applied with 20V. However, a P well 30 not having a selected block does not experience stress since it is applied with 0V. -
FIG. 3 is a graph showing the relationship between an erase time and an erase speed. As shown inFIG. 3 , whenever the stress time reduces to ½, an erase time reduces about 0.3V. It is thus possible to prevent disturbance due to erase stress. Moreover, since thetriple P wells 30 are divided, capacitance between thetriple P wells 30 and thetriple N well 20 reduces. Thus, an overall erase time budget can be reduced because well bias charging and discharging time reduce. - A method of forming a well in a NAND flash device according to the present invention will now be described with reference to the accompanying drawings.
FIGS. 4A and 4B are cross-sectional views for explaining the method of the well in the NAND flash device according to the present invention. Referring toFIG. 4A , a first mask (not shown) for ion implant through which a given cell region is opened is formed on a P-type semiconductor substrate 10. A N-type ion implant process is performed to formtriple N wells 20 within the P-type semiconductor substrate 10. The first mask may open the entire cell region or the cell region as much as a multiple of 2 or 3. Thereby, thetriple N wells 20 are formed in the entire cell region or thetriple N wells 20 as much as a multiple of 2 or 3 are formed in the cell region. - Referring to
FIG. 4B , a second mask (not shown) through which thetriple N wells 20 are opened is formed in the cell region of thesemiconductor substrate 10 in which thetriple N wells 20 are formed. A P-type ion implant process is performed to formtriple P wells 30 within thetriple N wells 20. At this time, the second mask can open the entire triple N well 20 region or the triple N well 20 region as much as a multiple of 2 or 3. - In this embodiment, a single triple N well 20 can be formed in the cell region of the P-
type semiconductor substrate 10 and twotriple P wells 30 can be formed within thetriple N well 20. Or, twotriple N wells 20 can be formed in the cell region of the P-type semiconductor substrate 10 and thetriple P wells 30 can be formed within the twotriple N wells 20, respectively. In this time, a P well (not shown) for low voltage NMOS and an N well (not shown) for low voltage PMOS can be formed in a region where a low voltage device will be formed through a subsequent process. Thereafter, a tunnel oxide film (not shown), a floating gate (not shown), a dielectric film (not shown) and a control gate (not shown) are formed on the triple P well 30 through predetermined processes, thereby forming flash memory cells. (not shown). Interlayer insulating films (not shown) for isolating the flash memory cells are formed. The interlayer insulating films are patterned to form contact plugs (not shown) and bit lines are then formed on the contact plugs. - As described above, according to the present invention, triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple wells. Accordingly, during an erase operation of a flash memory device, a stress time for non-selected blocks can be reduced and erase disturbance can be prevented, through the plurality of the wells. Further, as triple P wells are divided, capacitance between the triple P wells and the triple N well reduces. Therefore, well bias charging and discharging time can be reduced and an overall erase time budget can be thus reduced.
- The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom, as modifications within the scope of the invention may be apparent to those having ordinary skill in the art.
Claims (3)
1. A method of forming a well of a NAND flash memory device, the method comprising:
forming, on a P-type semiconductor substrate, a first mask through which the entire cell region is opened or a cell region is opened as much as a multiple of 2 or 3;
performing a N-type ion implant process using the first mask as an ion implant mask to form a triple N well within the P-type semiconductor substrate;
forming a second mask through which the entire triple N well region of the semiconductor substrate in which the triple N well is formed is opened or a triple N well region is opened as much as a multiple of 2 or 3; and,
performing a P-type ion implant process using the second mask as an ion implant mask to form a triple P well within the triple N well.
2. The method of claim 1 , wherein one triple N well is formed in the cell region of the P-type semiconductor substrate and two triple P wells are formed within the triple N well.
3. The method of claim 1 , wherein two triple N wells are formed in the cell region of the P-type semiconductor substrate and the triple P wells are formed within the two triple N wells, respectively.
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US11/702,698 US20070166889A1 (en) | 2004-05-11 | 2007-02-06 | Method of forming a well of a NAND flash memory device |
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KR1020040033207A KR100604561B1 (en) | 2004-05-11 | 2004-05-11 | NAND flash memory device and method of forming well in the same |
US11/010,987 US7551511B2 (en) | 2004-05-11 | 2004-12-13 | NAND flash memory device and method of forming a well of a NAND flash memory device |
US11/702,698 US20070166889A1 (en) | 2004-05-11 | 2007-02-06 | Method of forming a well of a NAND flash memory device |
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US11/702,698 Abandoned US20070166889A1 (en) | 2004-05-11 | 2007-02-06 | Method of forming a well of a NAND flash memory device |
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KR (1) | KR100604561B1 (en) |
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DE (1) | DE102004060421A1 (en) |
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US20080268624A1 (en) * | 2007-04-27 | 2008-10-30 | Hynix Semiconductor Inc. | Method of Fabricating Semiconductor Device |
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KR100604561B1 (en) * | 2004-05-11 | 2006-07-31 | 에스티마이크로일렉트로닉스 엔.브이. | NAND flash memory device and method of forming well in the same |
KR100792369B1 (en) * | 2006-01-13 | 2008-01-09 | 주식회사 하이닉스반도체 | Flash memory device and method for manufacturing the same |
KR100830575B1 (en) * | 2006-09-26 | 2008-05-21 | 삼성전자주식회사 | Flash memory device and multi-block erase method thereof |
US7940572B2 (en) | 2008-01-07 | 2011-05-10 | Mosaid Technologies Incorporated | NAND flash memory having multiple cell substrates |
US7907449B2 (en) * | 2009-04-09 | 2011-03-15 | Sandisk Corporation | Two pass erase for non-volatile storage |
KR101604631B1 (en) | 2009-07-21 | 2016-03-18 | 삼성전자주식회사 | Non-volatile memory device and program method thereof |
JP5853853B2 (en) | 2012-05-09 | 2016-02-09 | 富士通セミコンダクター株式会社 | Semiconductor memory device and driving method thereof |
KR20210117612A (en) * | 2020-03-19 | 2021-09-29 | 에스케이하이닉스 주식회사 | Semiconductor device |
US11444160B2 (en) | 2020-12-11 | 2022-09-13 | Globalfoundries U.S. Inc. | Integrated circuit (IC) structure with body contact to well with multiple diode junctions |
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- 2004-12-13 TW TW093138522A patent/TWI271823B/en not_active IP Right Cessation
- 2004-12-14 DE DE102004060421A patent/DE102004060421A1/en not_active Withdrawn
- 2004-12-27 JP JP2004375616A patent/JP2005328023A/en active Pending
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2005
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2007
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Also Published As
Publication number | Publication date |
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TWI271823B (en) | 2007-01-21 |
TW200537650A (en) | 2005-11-16 |
US20050253198A1 (en) | 2005-11-17 |
US7551511B2 (en) | 2009-06-23 |
CN100466259C (en) | 2009-03-04 |
DE102004060421A1 (en) | 2005-12-08 |
CN1697183A (en) | 2005-11-16 |
JP2005328023A (en) | 2005-11-24 |
KR100604561B1 (en) | 2006-07-31 |
KR20050108143A (en) | 2005-11-16 |
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