JPH03290960A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To enable erasure of data for each appropriate unit of a memory cell array block by dividing a memory cell array into a plurality of blocks and by providing each block with an electrode for setting a well potential. CONSTITUTION:Eight memory cells M1 to M8 are connected directly to construct one NAND cell, and a source diffusion layer 7 of the NAND cell is so formed as to surround memory cell array regions A1 and A2 turned up vertically by a bit line contact part and constructs an erasure unit block. For each erasure unit block, an electrode wiring 11 for setting a well potential is disposed on an n-type silicon substrate 1 having a bit line 9 formed, with a CVD oxide film 10 interposed, so that it intersects the line 9. By giving a high potential to the layer 7, the wiring 11, etc., erasure of data for each divided block of a memory cell array in a p-type well 2 is enabled and replacement of a floppy disk or a hard disk by EEPROM made to have a large capacity can be realized with ease.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).

(Conventional technology) NAND, which can be highly integrated, is one of the EEFROMs.
Cell-type EEPROMs are known.

In this method, a plurality of memory cells are connected in series so that adjacent cells share their sources and drains, and are connected as a unit to a bit line. Memory cells are usually FETMO in which a charge storage layer and a control gate are stacked.
It has an S structure. The memory cell array is integrated into, for example, a p-type well formed in an n-type silicon substrate.

The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a source line (reference potential wiring) via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell located farthest from the bit line. A high voltage VpI (about -20V) is applied to the control gate of the selected memory cell, and an intermediate potential (about -10V) is applied to the control gate and selection gate of the memory cell on the bit line side. , an OV or intermediate potential is applied to the bit line depending on the data. When OV is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, causing electron injection from the drain to the floating gate. This causes the threshold value of the selected memory cell to shift in the positive direction. When an intermediate potential is applied to the bit line, no electron injection occurs and there is no threshold change.

Data erasure is performed simultaneously on all memory cells in the NAND cell. That is, a high voltage of 20 V is applied to the p-type well and the n-type substrate with all control gates and selection gates set to OV, bit lines and source lines in a floating state. As a result, electrons from the floating gates of all memory cells are released into the p-type well, and the threshold voltage is shifted in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to Ov, the control gates and selection gates of other memory cells are set to the power supply potential Vcc (-5V), and it is detected whether or not current flows in the selected memory cell. It is done by doing.

As is clear from the above description of the operation, in the conventional NAND cell type EEPROM, data is erased by applying a high voltage of about 20 V to the p-type well in which the memory cell array is formed. As a result, all memory cells formed in the same p-type well are erased. This means that data cannot be rewritten by selectively erasing a portion of the memory cell array.

A promising future application field for large-capacity EEPROMs is the replacement of magnetic recording media. For example, replacing floppy disks and hard disks. In these magnetic disks, the erase/write unit is 512
The range of bytes is set from byte to 1. EE
Therefore, it is desirable for a PROM to have an erase unit of the order of a byte.

(Problems to be Solved by the Invention) As described above, the conventional EEFROM has a problem in that data cannot be erased by dividing a plurality of cells formed in one well into a plurality of unit blocks.

The present invention has been made in view of these points, and it is an object of the present invention to provide a nonvolatile semiconductor memory device that enables data erasure in units of appropriate memory cell array blocks.

[Structure of the Invention (Means for Solving the Problems) The present invention provides a method in which a second conductivity type well is formed in a first conductivity type semiconductor substrate, and a charge storage layer and a control gate are stacked in the second conductivity type well. In a non-volatile semiconductor memory device in which a memory cell array having electrically rewritable (MOS) transistor-structured memory cells is formed, the memory cell array is divided into a plurality of blocks, and the potential of the second conductivity type well is changed for each block. The well potential setting electrode is provided to set the well potential.

In the present invention, it is particularly preferable that the memory cell array formed in the second conductivity type well be connected to the first
The structure is divided into a plurality of blocks surrounded by conductivity type diffusion layers, and a well potential setting electrode for setting the potential of the second conductivity type well is disposed in each block.

(Function) According to the present invention, by setting the erase unit of the EEFROM to an appropriate size, it becomes possible to replace a floppy disk or a hard disk, and the field of application of the EEFROM is expanded. In particular, the chip size can be increased by dividing the second conductivity type well into multiple blocks surrounded by the first conductivity type diffusion layer, which serves as the reference potential line of the memory cell array, without dividing the second conductivity type well into multiple parts on a mask. The erase unit can be made smaller without having to do so.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a memory cell array portion of a NAND cell type EEFROM according to an embodiment, FIG. 2 is a cross-sectional view taken along line AA', and FIG. 3 is a cross-sectional view taken along line B-B'. A p-type well 2 is formed in an n-type silicon substrate, and a memory cell array consisting of a plurality of NAND cells is formed within this p-type well 2.In this embodiment, a memory cell array consisting of a plurality of NAND cells is formed. Memory cells M1 to M8 are connected in series to form one NAND cell. Each memory cell has a floating gate 4 stacked on a p-type well 2 with a gate insulating film interposed therebetween.
(4+, 42,..., 48) and control gate 5 (
5, 5□, . . . , 58), and the memory cells are connected in series so that the n-type diffusion layers 6, which are the sources and drains, are shared by adjacent ones.

Drain side of NAND cell.

Selection gates 51 and 52 are provided on the source side, respectively. CVD is applied to the drain side diffusion layer 6 of the NAND cell.
Bit line 9 disposed on oxide film 8 is in contact with it. The control gates 4 of the ΔNAND cells arranged in the row direction have a common control gate line CG.

CG2. ..., are arranged as CCS. The selection gates 5□ and 52 are also arranged continuously in the row direction as selection gate control lines SDI and SSI, respectively. On the other hand, in the column direction, two NAND cells are arranged in a folded manner at a bit line contact portion, and are commonly connected to a bit line 9 running in the column direction. The source diffusion layer 7 of the NAND cell is formed to surround the memory cell array regions A, . There is. In this embodiment, for each erase unit block, a CVD oxide film 1 is formed on the substrate on which the bit line 9 is formed.
The well potential setting electrode wiring 11 is connected to the bit line 9 via the bit line 9.
It is arranged to intersect with the This well potential setting electrode wiring 11 is in contact with the p+ type scattering layer 12 formed in the p type well 2 at a position in the field region adjacent to the contact position of the bit line 9. The other erase blocks are configured similarly.

Writing to EEFROM configured in this way.

Erasing and reading operations will be explained next. For example, when writing data to memory cells along the control gate line CGs, the high voltage Vpp-20 is applied to the control gate line CG8.
V is applied to the control gate line CG on the bit line side from this,
~CG7 and the selection gate line SI5+ have an intermediate potential (-
Approximately 10V) is applied to the bit line, and O is applied to the bit line according to the data.
v or give an intermediate potential. In the selected memory cell along the bit line to which Ov is applied, electron injection occurs from the drain to the floating gate, and the threshold value of the memory cell shifts in the positive direction. No electron injection occurs in the memory cells along the bit line to which the intermediate potential is applied, and there is no change.

A similar write operation is performed in order from memory cells distant from the bit line.

Data erasure is performed for each erase unit block.

For example, the memory cell array area A1 in FIG. Erasing within a unit block consisting of A2 is performed by setting all the control gate lines 9 selection gate lines in this block to the Ov1 bit line in a floating state, and transferring them to the n-type substrate 1. A high voltage vpp is applied to the source diffusion layer 7 and the well potential setting electrode wiring 11. For other erase unit blocks, the control gate line 1 selection gate line and the well potential fixing electrode wiring are kept at OV. This results in
Electrons from the floating gates of all memory cells in the selected unit block are released into the p-type well, and the threshold voltage is shifted in the negative direction.

During this erase operation, the p-type well regions of the selected block and other blocks are substantially separated by a depletion layer extending from the source diffusion layer 7 surrounding the selected unit block. The situation is shown in FIG. In FIG. 5, block A is the cell array block selected for erasing, and B is the unselected cell array block.

20V is applied to the p-type well region 2A of the selected block A.
is applied, and the p-type well region 2B of the unselected block B is set to OV. In addition, the source diffusion layer 7 and the substrate 1 have 2
0V is applied. Therefore, the depletion layer 12 extends as shown by diagonal lines, and the p-type well region 2A selected within one p-type well 2 is electrically isolated from the other p-type well regions 28, and the selected p-type well region 2A within the block is Only data will be deleted.

Note that during this data erasing operation, it is preferable that the timing of applying potentials to each part be as shown in FIG. That is, n
Applying a high voltage VpI to the mold substrate 1 and the source diffusion layer 7,
A high voltage vpp is applied to the well potential setting electrode wiring of the selected block with a delay of time τ. At the end of the erase operation, conversely, the high voltage vpp applied to the electrode wiring for setting the well potential is first returned to 0■, and after a delay of time τ, the other high voltage Vl)p is returned to OV. In this way, by providing a certain delay in applying the high voltage Vpp to each part, it is possible to prevent the situation in which the high voltage Vl)p is applied to all p-type wells at the same time, and ensure data erasure of the selected block. will be held. The data read operation is
The control gate line selected in the NAND cell is set as OV,
This is performed by setting the control gates and selection gates of the other memory cells to the power supply potential Vce (-5V) and detecting whether or not current flows in the selected memory cell.

As described above, according to this embodiment, the memory cell array in the p-type well is divided into a plurality of erase unit blocks,
Data can be erased for each block. Therefore, it becomes easy to replace a floppy disk or hard disk with a large-capacity EEPROM. If the p-type well itself is divided into unit blocks on a mask, a large area will be consumed because the formation of a deep p-type well involves large lateral diffusion, but in this example, the p-type well itself is divided into unit blocks. Since it is not divided, there is no problem with increasing number of men.

FIG. 6 is a sectional view corresponding to FIG. 2 of a NAND cell type EEPROM of another embodiment.

In this embodiment, an n-type buried diffusion layer 13 is formed at the interface between the p-type well 2 and the substrate 1 under the n-type source diffusion layer 7 surrounding the erase unit block. Such a buried diffusion layer 13
By providing this, the width of the p-type well below the source diffusion layer 7 becomes substantially smaller, and even if the p-type well 2 is deep, separation of the p-type well region by the depletion layer during erasing can be ensured. .

FIG. 7 shows yet another embodiment of a NAND cell type EEPRO.
FIG. 2 is a sectional view corresponding to FIG. 2 of M.

In this embodiment, the region 14 under the source diffusion layer 7 of the p-type well 2 is formed shallowly. For example, during ion implantation when forming the p-type well 2, a mask is formed in the source diffusion layer formation region to prevent ion implantation. Then, p-type ions are diffused under the source diffusion layer 7 during the thermal process during the formation of the p-type medium well, and although the p-type well 2 is formed, it becomes a shallow p-type well layer.

In this embodiment as well, the p-type well region of a unit erase block is reliably separated from the p-type well regions of other unit erase blocks by the depletion layer.

Further, the p-type well depth of the source diffusion layer region can be made substantially shallower by forming the source diffusion layer deeper than other source and drain regions of the memory cell. Furthermore, the above combination also allows the p-type well region of a unit erase block to be separated from other regions by a depletion layer.

FIG. 8 shows yet another embodiment of a NAND cell type EEFRO.
FIG. 2 is a sectional view corresponding to FIG. 2 of M.

In this embodiment, unlike the previous embodiments, the source diffusion layer 7 that determines an erase unit block is replaced by a p-type well 2.
It is formed to a depth that reaches the n-type substrate 1. This is substantially equivalent to forming a p-type well for each erase unit block.

In this embodiment, the read operation is carried out between the source diffusion layer 7 and n
Since the type substrate 1 is connected, if the n type substrate 1 is grounded, it is the same as the conventional case. However, normally, C
In the case of MOSLSI, Vcc is applied to the n-type substrate. In this case, for example, when reading out the memory cell M2 with the bit line floating at the "L" level, the control gate CG12 is set to OV, and the other control gates C
G 11゜CG13 to CG18 5V, selection gate line 1
Both tsD1゜SSI are set to 5V, and p-type well 2 is set to oV.
Set to . If the memory cell M2 is programmed to "0", its threshold value is negative, so a current flows from the source diffusion layer at Vcc to the bit line, contrary to the conventional case.

If the memory cell M2 is programmed to "11", its threshold value is positive and no current flows through the bit line.In this way, reading can be performed by reversing the direction in which current flows from the conventional one.

In the case of this embodiment, the width increases as the source diffusion layer 7 becomes deeper, but the increase in area is smaller than when the p-type well is divided on a mask. Further, since the source diffusion layer 7 is only located around the memory cell block, an increase in area is not a problem in this respect as well. And according to this example,
Unlike the previous embodiments, the erase unit block is separated by pn junction.

FIG. 9 is a modification of FIG. 8, in which the source diffusion layer 7
In order to make it easier to divide the type well 2, the p-type well 2 is made shallower under the source diffusion layer 7.

Figure 10 shows an example of the manufacturing process to obtain the structure shown in Figure 9.
Shown in a) to Cd). In the ion implantation process for forming a p-type well in the n-type silicon substrate 1, a mask 21 is formed in the source diffusion layer formation region (see FIG. 10(a)).
)). In the subsequent thermal process, a p-type well 2 is formed under the mask 21, but the thickness of that part becomes thinner (see Fig. 10).
b)). Then, using the mask 22, ion implantation is performed to form a source diffusion layer (FIG. 10(C)). At this time, p of the region that will become the source diffusion layer 7 surrounding the erase unit block is
If the mold layer is thin enough, the source of the memory cell.

Even if it is formed at the same time as the drain diffusion layer, it can reach the substrate. Of course, the source diffusion layer 7
It may be formed deeply separately from other source and drain diffusion layers of the element.

FIGS. 11(a) to 11(C) show yet another manufacturing process example. In the source diffusion layer region, the same insulating film 31 as the element isolation region is formed in advance (FIG. 11(a)). Then, a gate with a stacked structure is formed (FIG. 11(b)), and then the insulating film 31 in the source diffusion layer region is selectively etched away to form a deep source diffusion layer 7 there (first step).
Figure 1 (C)). This also provides the structure of the embodiment shown in FIG.

Although a NAND cell type EEPROM has been described in the above embodiment, the present invention is not limited to this, but has a similar memory cell structure, and a tunnel current is generated between the p-type well and the charge storage layer of the memory cell. It can also be applied to other types of EEFROM in which data is rewritten using the above method.

[Effects of the Invention] As described above, according to the present invention, the EEFRO is capable of replacing the magnetic disk by dividing the unit of data erasure.
M can be provided.

[Brief explanation of drawings]

FIG. 1 shows a NAND cell type EEPRO according to an embodiment of the present invention.
FIG. 2 is a plan view showing the memory cell array of M.
3 is a sectional view along line BB', FIG. 4 is a diagram showing operation waveforms during data erasing, FIG. 5 is a diagram showing electrical isolation of erase unit blocks, 6 is a sectional view of an EEFROM of another embodiment corresponding to FIG. 2, FIG. 7 is a sectional view of an EEFROM of another embodiment corresponding to FIG. 2, and FIG. 8 is a sectional view of an EEFROM of another embodiment. 9 is a sectional view corresponding to FIG. 2 of the EEFROM of another embodiment. FIGS. 10(a) to 10(d) are manufacturing steps of the structure shown in FIG. 9. Figures illustrating process examples: Figures 11(a) to 11(C) are diagrams illustrating other manufacturing process examples. 1... n-type silicon substrate, 2... p-type well, 3...
...Floating gate, 4... Control gate, 6... Source, drain diffusion layer, 7... Source diffusion layer, 8°10.
...CVD oxide film, 9...bit line, 11...well potential setting electrode wiring, 12...p+ type contact part, 13...n type buried diffusion layer, 14...shallow diffusion layer Part, M, ~M8...Memory cell.

Claims (8)

[Claims] (1) A second conductivity type well is formed in a first conductivity type semiconductor substrate, and the memory cell has an electrically rewritable MOS transistor structure in which a charge storage layer and a control gate are stacked in the second conductivity type well. In a nonvolatile semiconductor memory device in which a memory cell array is formed, the memory cell array is divided into a plurality of blocks, and a well potential setting electrode for setting the potential of the second conductivity type well is provided in each of the plurality of blocks. A nonvolatile semiconductor memory device characterized by: (2) A second conductivity type well is formed in the first conductivity type semiconductor substrate, and a memory cell array having memory cells having a MOS transistor structure in which a charge storage layer and a control gate are stacked is formed in the second conductivity type well. In a non-volatile semiconductor memory device, a memory cell array formed in one second conductivity type well is surrounded by a first conductivity type diffusion layer serving as a reference potential wiring and is divided into a plurality of blocks. A nonvolatile semiconductor memory device characterized in that each well is provided with a well potential setting electrode for setting the potential of the second conductivity type well. (3) The nonvolatile semiconductor according to claim 1 or 2, wherein the memory cell is electrically rewritten by transfer of charge by a tunnel current between the charge storage layer and the second conductivity type well. Storage device. (4) The memory cells are capable of being electrically rewritten by transfer of charge through a tunnel current between the charge storage layer and the second conductivity type well, and a plurality of adjacent memory cells share a source and a drain. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the NAND cells are connected in series in a manner such that a NAND cell is configured. (5) The nonvolatile material according to claim 2, wherein the first conductivity type diffusion layer serving as the reference potential line penetrates through the second conductivity type well and is connected to the first conductivity type semiconductor substrate. Semiconductor storage device. (6) A second conductivity type well is formed in the first conductivity type semiconductor substrate, and in the second conductivity type well, a memory cell having a FETMOS structure in which a floating gate and a control gate are stacked has its source and drain adjacent to each other. It has a memory cell array that is connected in series to form NAND cells and is arranged in a matrix, and the drain at one end of each NAND cell is connected to a bit line running in the column direction via a selection gate. In a nonvolatile semiconductor memory device in which control gates in each NAND cell are arranged continuously for NAND cells arranged in a row direction to form a word line, a memory cell array formed in one second conductivity type well is surrounded by a first conductivity type source diffusion layer serving as a reference potential wiring and is divided into a plurality of blocks, and a well potential setting electrode wiring for setting the potential of the second conductivity type well in each of the plurality of blocks is connected to the word What is claimed is: 1. A nonvolatile semiconductor memory device, characterized in that the well is arranged in the same direction as the bit line and is in contact with a second conductivity type well at a position adjacent to a bit line contact position. (7) The nonvolatile semiconductor memory device according to claim 6, wherein the plurality of blocks are divided in the column direction. (8) The nonvolatile nonvolatile material according to claim 6, wherein the first conductivity type source diffusion layer serving as the reference potential line penetrates through the second conductivity type well and is connected to the first conductivity type semiconductor substrate. semiconductor memory device.