JP3453001B2 - Semiconductor integrated circuit device, nonvolatile semiconductor memory device, and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device having a triple well structure formed on an epi substrate.

[0002]

2. Description of the Related Art In recent years, a flash memory, which is a kind of non-volatile semiconductor memory device, can be manufactured at a lower cost than a dynamic random access memory (DRAM), and is therefore expected as a memory device for the next generation. The memory cell of this type of flash memory has a source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information, and a corresponding word line. Control gate electrode, which is used for injecting electrons into the floating gate electrode by the FN tunnel phenomenon or channel hot electron phenomenon of the gate insulating film made of a tunnel oxide film located immediately below the floating gate electrode, or the floating gate electrode. Erasing or writing is done by extracting the electrons accumulated in the electrodes,
The binary state of the threshold value is created by the state of electrons in the floating gate electrode, and "0" or "1" is read out depending on the state.

Generally, a flash memory can electrically erase all memory cells at once.
Recently, a method of collectively erasing in block units having a plurality of memory cells has become mainstream. For example, "IEEE JOURNAL OF SOLID-STATE CIRCUI
T, VOL.29, NO.4, APRIL 1994 ”, pages 454 to 460
Page or IEICE TRANS. ELECTRON., VOL.E77-C, NO.8 AU
It is described as a DINOR type flash memory on pages 1279 to 1286 of GUST 1994.

[0004]

In such a flash memory, when a plurality of memory cells are erased in a block unit, a back gate (Vbb) voltage is applied to a well region where the memory cells are formed. Further, a voltage higher than the power supply voltage is applied to the drain region or the source region of the memory cell at the time of erasing or writing. Therefore, the structure tends to cause latch-up due to the parasitic transistor of the thyristor structure.

In order to electrically insulate the well region in which memory cells are formed in block units from the semiconductor substrate, the well region is provided so as to further surround the well region in which memory cells are formed (triple well structure). Therefore, it is necessary to consider the punch-through breakdown voltage between the well region in which the memory cell is formed and the semiconductor substrate. Furthermore, as the degree of integration increases and the area occupied by the memory cells becomes smaller, it is necessary to improve the quality of the gate insulating film in which electrons are injected and extracted. Furthermore, there is a tendency to form a high voltage generating circuit that generates a high voltage used during erasing or writing together on a semiconductor substrate on which a memory cell is formed. It is also necessary to consider the junction breakdown voltage between the well region in which the semiconductor element forming the above is formed and the semiconductor substrate.

The present invention has been made in view of the above points, and it is an object of the present invention to obtain a semiconductor integrated circuit device, a non-volatile semiconductor memory device having improved latch-up resistance, and manufacturing methods thereof. . A second object of the present invention is to obtain a semiconductor integrated circuit device, a non-volatile semiconductor memory device and a method for manufacturing them, in which the punch-through breakdown voltage between the well region and the semiconductor substrate is improved.
Further, a third object of the present invention is to obtain a nonvolatile semiconductor memory device which can increase the number of times of rewriting information and has a long life, and a manufacturing method thereof. Furthermore, a fourth object of the present invention is to obtain a semiconductor integrated circuit device, a nonvolatile semiconductor memory device, and a method for manufacturing them, in which the junction breakdown voltage between the well region and the semiconductor substrate is improved.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first semiconductor layer of a first conductivity type; and a first semiconductor on the surface of the first semiconductor layer. A second semiconductor layer of the first conductivity type epitaxially grown with an impurity concentration lower than that of the layer, and a second semiconductor layer on the surface of the second semiconductor layer and on the surface of the first semiconductor layer;
Second conductive type first well region formed with the semiconductor layer interposed therebetween, the first conductive type second well region formed on the surface of the first well region, and the second semiconductor A third well region of a first conductivity type formed on the surface of the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer, and a first well region separated from the surface of the second semiconductor layer. A semiconductor substrate having a formed second well region of the second conductivity type is formed, and a first semiconductor element formed in the second well region of the semiconductor substrate and a third well region of the semiconductor substrate. And a third semiconductor element formed in the fourth well region of the semiconductor substrate .
The well region is formed from the surface of the semiconductor substrate to the first semiconductor layer.
From the concentration peak and this concentration peak in the depth direction toward
Furthermore, the value of the concentration peak is deeper than the surface of the semiconductor substrate.
Impurity of the second conductivity type including the part where the concentration drops by 2 digits
It has a distribution of objects, and is it the surface of the semiconductor substrate that falls by two digits?
The depth is less than or equal to the thickness of the second semiconductor layer .

According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a first semiconductor layer of a first conductivity type and an impurity concentration of the first semiconductor layer on a surface of the first semiconductor layer. An epitaxially grown second semiconductor layer of the first conductivity type having a low impurity concentration, and the second semiconductor layer interposed between the surface of the second semiconductor layer and the surface of the first semiconductor layer. Formed on the surface of the first semiconductor region, a second well region of the first conductivity type formed on the surface of the first well region, and a second well region of the first conductivity type formed on the surface of the first well region. , A third well region of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer, and a second conductivity type formed on the surface of the second semiconductor layer so as to be separated from the first well region. A semiconductor substrate having a fourth well region of a mold, Non-volatile memory cell formed in the second well region of the semiconductor substrate, the second conductivity type MOS transistor formed in the third well region of the semiconductor substrate, and the fourth well region formed in the fourth well region of the semiconductor substrate. MO of 1 conductivity type
An S transistor is provided , and the first well region is a semiconductor substrate.
Concentration in the depth direction from the surface of the plate to the first semiconductor layer
The peak and the concentration peak
Part where the concentration drops by 2 digits from the concentration peak value to a deeper position
Has a second conductivity type impurity distribution including
The second semiconductor layer has a depth from the surface of the semiconductor substrate
Is less than or equal to the thickness .

A non-volatile semiconductor memory device according to a third aspect of the present invention is a memory cell array having a plurality of memory cells, and information is written in the memory cells of the memory cell array, and information stored in the memory cells is read out. A peripheral circuit for erasing information stored in a cell, a plurality of memory cells of a memory cell array are divided into a plurality of blocks, and an erasing operation is collectively performed in each block. A P-type first semiconductor layer, an epitaxially grown P-type second semiconductor layer having an impurity concentration lower than that of the first semiconductor layer on the surface of the first semiconductor layer, and the second An N-type first well region formed on the surface of the semiconductor layer by interposing a second semiconductor layer between the surface of the first semiconductor layer and the surface of the first semiconductor layer; A plurality of P-type second well regions formed separately from each other on the surface of the second semiconductor layer, and a P-type impurity formed on the surface of the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer. A third well region of
A semiconductor substrate having a first well region and an N-type fourth well region formed separately from the surface of the second semiconductor layer is provided, and one of the plurality of second well regions is provided for each block unit.
Corresponding to the above, a plurality of memory cells in each block unit are formed in the corresponding second well region, and at least a part of the plurality of N-channel MOS transistors forming the peripheral circuit is the third N-channel MOS transistor. A plurality of P-channel MOs formed in the well region and forming peripheral circuits
At least a portion of the P-channel MOS transistor of the S transistor is formed in the fourth well region, a first of the upper
Area from the surface of the semiconductor substrate to the first semiconductor layer
Concentration peak in the depth direction and
From the concentration peak value to the deep position from the surface of the semiconductor substrate,
There is a distribution of N-type impurities including the part where the degree drops by two digits.
However, the depth from the surface of the semiconductor substrate where it falls by two digits is the first
The thickness of the second semiconductor layer is less than or equal to the thickness of the second semiconductor layer .

A non-volatile semiconductor memory device according to a fourth aspect of the present invention is a memory cell array having a plurality of memory cells, and information is written into the memory cells of the memory cell array, information stored in the memory cells is read out, and a memory. A peripheral circuit for erasing information stored in a cell, a plurality of memory cells of the memory cell array are divided into a plurality of blocks, and an erasing operation is collectively performed in each block. , A P-type first semiconductor layer, an epitaxially grown P-type second semiconductor layer having an impurity concentration lower than that of the first semiconductor layer on the surface of the first semiconductor layer, and The second semiconductor layer is formed on the surface of the second semiconductor layer so as to be separated from each other, and the second semiconductor layer is formed between the surface of the first semiconductor layer and the surface of the first semiconductor layer. A plurality of N-type first well regions, a plurality of P-type second well regions respectively formed on the surfaces of the plurality of first well regions, and a surface of the second semiconductor layer And a P-type third well region having an impurity concentration higher than that of the second semiconductor layer, and an N-type first well region formed on the surface of the second semiconductor layer away from the first well region. A semiconductor substrate having four well regions and corresponding to one of the plurality of second well regions for each block unit, a plurality of memory cells of each block unit are formed in the corresponding second well region. , At least part of the plurality of N-channel MOS transistors forming the peripheral circuit is formed in the third well region, and at least the plurality of P-channel MOS transistors forming the peripheral circuit are formed. P-channel MOS transistor parts is formed on a fourth well region, double
A number of first well regions from the surface of the semiconductor substrate to the first
The concentration peak and this concentration peak are formed in the depth direction toward the semiconductor layer.
The concentration peak at a position deeper than the surface of the semiconductor substrate.
N-type defect including the part where the concentration drops by two digits from the peak value
The surface of the semiconductor substrate, which has a pure distribution and falls by two digits
Is less than or equal to the thickness of the second semiconductor layer .

A nonvolatile semiconductor memory device according to a fifth aspect of the present invention is a memory cell array having a plurality of memory cells, information is written in the memory cells of the memory cell array, and information stored in the memory cells is read out. A peripheral circuit for erasing information stored in a cell, the peripheral circuit having a booster circuit receiving a power supply potential applied to a power supply potential node and outputting a boosted potential higher than the power supply potential A first semiconductor layer of a first conductivity type, and an epitaxially grown second semiconductor layer of an impurity concentration lower than that of the first semiconductor layer on the surface of the first semiconductor layer And a second conductive type first formed on the surface of the second semiconductor layer with the second semiconductor layer interposed between the surface of the first semiconductor layer and the surface of the first semiconductor layer.
Well region, the second well region of the first conductivity type formed on the surface of the first well region, and the surface of the second semiconductor layer, the impurity concentration of which is higher than that of the second semiconductor layer. A semiconductor having a third well region of a first conductivity type having an impurity concentration and a fourth well region of a second conductivity type formed on the surface of the second semiconductor layer so as to be separated from the first well region. comprising a substrate, a semiconductor element constituting the output stage of the boost circuit is formed in the second well region, the second well region
The diffusion region of the second conductivity type formed on the surface of the
Region, the second well region as the base region, and the first well region
The collector region is the well region, and the base region and the collector region are
Diode-connected bipolar device that is electrically connected to the
Of the plurality of second-conductivity-type MOS transistors constituting the peripheral circuit.
The S transistor is formed in the third well region, and at least a part of the MOS transistors of the first conductivity type forming the peripheral circuit are formed in the fourth well region.

[0012]

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, wherein an impurity concentration lower than that of the first semiconductor layer is epitaxially grown on the surface of the first conductivity type first semiconductor layer. And a step of forming a second semiconductor layer of the first conductivity type, and ion-implanting impurities of the second conductivity type so that a peak of the impurity concentration is located at a predetermined depth from the surface of the second semiconductor layer. A step of forming a first well region of a second conductivity type on the surface of the second semiconductor layer, including the step of implanting, and a step of forming a first well region on the surface of the first well region.
Forming a second well region of the first conductivity type above the peak position of the impurity concentration at a predetermined position in the well region, and impurities higher than the impurity concentration of the second semiconductor layer on the surface of the second semiconductor layer. Forming a third well region of a first conductivity type having a concentration, and forming a fourth well region of a second conductivity type on the surface of the second semiconductor layer, spaced apart from the first well region. A step of forming the first semiconductor element in the second well region, a step of forming the second semiconductor element in the third well region, and a step of forming the third semiconductor element in the fourth well region. And steps are provided.

A method of manufacturing a semiconductor integrated circuit device according to a seventh aspect of the present invention comprises a step of forming an epi layer by epitaxial growth on the surface of a first semiconductor layer of the first conductivity type, and a step of forming the epi layer. An impurity of the first conductivity type is ion-implanted so that a peak of the impurity concentration is located at a position at a predetermined depth from the surface, and the second impurity of the first conductivity type having an impurity concentration lower than the impurity concentration of the first semiconductor layer is implanted. A step of forming a semiconductor layer, a step of forming a second well of the second conductivity type on the surface of the second semiconductor layer, and a step of forming a second well of the first conductivity type on the surface of the first well region. Forming a well region,
Forming a third well region of a first conductivity type having an impurity concentration higher than that of the second semiconductor layer on the surface of the second semiconductor layer; and a second conductivity type on the surface of the second semiconductor layer. Forming the fourth well region away from the first well region, forming the first semiconductor element in the second well region, and forming the second semiconductor element in the third well region. The step of forming and the step of forming the third semiconductor element in the fourth well region are provided.

A method of manufacturing a semiconductor integrated circuit device according to an eighth aspect of the present invention comprises a step of forming an epi layer by epitaxial growth on the surface of a first semiconductor layer of the first conductivity type, and a step of forming the epi layer. An impurity of the first conductivity type is ion-implanted so that a peak of the impurity concentration is located at a position at a predetermined depth from the surface, and the second impurity of the first conductivity type having an impurity concentration lower than the impurity concentration of the first semiconductor layer is implanted. The method includes the step of forming a semiconductor layer and the step of ion-implanting a second conductivity type impurity so that a peak of the impurity concentration is located at a predetermined depth from the surface of the second semiconductor layer. Forming on the surface of the layer a first well region of the second conductivity type by interposing the peak position of the second semiconductor layer between the surface of the first semiconductor layer and the surface of the first semiconductor layer; A second wafer of the first conductivity type is formed on the surface of the region. Forming a region, forming a third well region of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer on the surface of the second semiconductor layer, and the second semiconductor layer Forming a fourth well region of the second conductivity type on the surface of the second semiconductor device apart from the first well region, forming a first semiconductor element in the second well region, and forming a third well region And a step of forming a third semiconductor element in the fourth well region.

[0016]

[0017]

[0018]

According to the first aspect of the present invention, the low-concentration second semiconductor layer formed by epitaxial growth is interposed between the first well region and the high-concentration first semiconductor layer. Latch-up and punch-through between the second well region and the second semiconductor layer are less likely to occur.
The junction breakdown voltage between the well region and the second semiconductor layer is increased.

In the second aspect of the present invention, the low-concentration second semiconductor layer formed by epitaxial growth is interposed between the first well region and the high-concentration first semiconductor layer. , Latch-up and second well region and second
Punch-through between the first well region and the second semiconductor layer is increased, and the second semiconductor layer reduces the density of impurities and defects in the gate insulating film. Excuse me.

According to the third aspect of the present invention, the first well region enables the second well region to be independently supplied with a potential, and the low concentration second semiconductor formed by epitaxial growth is used. A layer is interposed between the first well region and the high-concentration first semiconductor layer to prevent latch-up and punch-through between the second well region and the second semiconductor layer, The junction breakdown voltage between the first well region and the second semiconductor layer can be increased, and the second semiconductor layer can reduce the density of impurities and defects in the gate insulating film.

According to the fourth aspect of the present invention, the first well region enables the second well region to be independently supplied with a potential, and the second semiconductor of low concentration is formed by epitaxial growth. A layer is interposed between the first well region and the high-concentration first semiconductor layer to prevent latch-up and punch-through between the second well region and the second semiconductor layer, The junction breakdown voltage between the first well region and the second semiconductor layer can be increased, and the second semiconductor layer can reduce the density of impurities and defects in the gate insulating film.

In the fifth aspect of the present invention, the low-concentration second semiconductor layer formed by epitaxial growth is interposed between the first well region and the high-concentration first semiconductor layer. , Latch-up and second well region and second
Punch-through between the first well region and the second semiconductor layer with respect to the semiconductor element forming the output stage of the booster circuit is increased.

[0023]

In the sixth aspect of the present invention, the first well region is formed by interposing a low-concentration second semiconductor layer formed by epitaxial growth between the first well region and the surface of the first semiconductor layer. Since it is formed, latch-up is less likely to occur, the intervening low-concentration second semiconductor layer is less likely to cause latch-up and punch-through between the second well region and the second semiconductor layer. Impurity of the second conductivity type is ion-implanted so that the junction breakdown voltage between the region and the second semiconductor layer is increased and the peak of the impurity concentration is located at a predetermined depth from the surface of the second semiconductor layer. The process allows the impurity concentration profile at the bottom of the first well region to be freely selected.

In a seventh aspect of the present invention, the first well region is formed by interposing a low-concentration second semiconductor layer formed by epitaxial growth between the first well region and the surface of the first semiconductor layer. Since it is formed, latch-up is unlikely to occur, the intervening low-concentration second semiconductor layer is less likely to cause punch-through between the second well region and the second semiconductor layer, and the first well region and the first well region are prevented. The first conductivity type impurity is ion-implanted so that the junction breakdown voltage with the second semiconductor layer is increased and the peak of the impurity concentration is located at a position where the second semiconductor layer has a predetermined depth from the surface of the epi layer. The process is the second
The impurity concentration profile at the bottom of the semiconductor layer can be freely selected.

According to an eighth aspect of the present invention, the first well region is formed by interposing a low-concentration second semiconductor layer formed by epitaxial growth between the first well region and the surface of the first semiconductor layer. Since it is formed, latch-up is unlikely to occur, the intervening low-concentration second semiconductor layer is less likely to cause punch-through between the second well region and the second semiconductor layer, and the first well region and the first well region are prevented. The second semiconductor layer has a high junction breakdown voltage, and the second impurity concentration peak is located at a predetermined depth from the surface of the second semiconductor layer.
The step of ion-implanting a conductivity type impurity allows the profile of the impurity concentration at the bottom of the first well region to be freely selected, and the second semiconductor layer is formed at a predetermined depth from the surface of the epi layer. The step of ion-implanting impurities of the first conductivity type so that the peak of
The profile of the impurity concentration at the bottom of the second semiconductor layer can be freely selected.

[0027]

[0028]

[0029]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. First, the configuration of a flash memory, which is a kind of semiconductor nonvolatile memory device to which the first embodiment is applied, is shown in FIG.
It will be described based on. In Figure 1, 1 _{11-1 42,} respectively, a source region of N-type diffusion layer, a drain region of N-type diffusion layer formed spaced apart from the source region, the source region and the drain A floating gate electrode formed on the channel region located between the floating gate electrode and the region via a gate oxide film made of a tunnel oxide film, and a control gate electrode opposed to the floating gate electrode via an interlayer insulating film. It has a memory cell.

For convenience of explanation, FIG. 1 shows 4 rows and 2 columns.
Block 2 in which erase operation is collectively performed in units of 2 rows and 2 columns
Although only a and 2b are shown, a plurality of memory cells 1 arranged in a matrix of a plurality of rows and a plurality of columns constitute a memory cell array, and the memory cell array has a plurality of blocks 2 which are batch erase units. Each block 2 has multiple lines,
It has a plurality of columns of memory cells 1. The plurality of memory cells 1 forming each block 2 will be described in detail later, but one N of the plurality of N-type well regions formed in the P-type well region formed on the semiconductor substrate is separated from each other.
It is formed in the well region of the mold, and the substrate potential is independently applied to each block 2 by applying the substrate potential to the N-type well region. It should be noted that the subscript numbers in the reference numerals indicate the rows and / or the columns, and the alphabets indicate the individual block units, and the subscripts are omitted when generically indicated. The same applies hereinafter.

Reference numerals 3 _{1 to} 3 ₄ are word lines connected to the control gate electrodes of the plurality of memory cells 1 arranged in the corresponding rows, respectively, and the second polysilicon layer (floating layer). The gate electrode is formed by the first polysilicon layer) and the polysilicon layer integrally formed with the control gate electrode, and the first layer arranged in parallel above the polysilicon layer. And a metal layer.
4 _{1-4 2} main bit lines arranged in columns corresponding respectively, are those formed by the metal layer of the second layer which is arranged above the word lines 3. Reference _numerals 5 _{1a to} 52b are sub-bit lines arranged in corresponding columns and for each corresponding block 2, and connected to the drain regions of the plurality of memory cells 1 of the corresponding block 2 in the corresponding column,
It is formed by a third polysilicon layer arranged above the polysilicon layer of the word line 3.

[0032] 6 _1a to 6 _2b is attached to the sub-bit line every 4 corresponding respectively, N-channel MOS transistor connected between the sub-bit line 4 corresponding to the main bit lines 3 arranged in columns corresponding And a gate electrode formed by the second polysilicon layer. Source lines 7a-7b are provided for each corresponding block 2, and source lines 8a-8b are connected to the source regions of the plurality of memory cells 1 of the corresponding block 2, respectively.
Are provided for each corresponding block 2, and in order to apply the substrate potential of the plurality of memory cells 1 of the corresponding block 2, well potential lines connected to the P-type well region in which the plurality of memory cells 1 are formed. Is.

Blocks 9a and 9b respectively correspond to the block 2.
Block select signal lines 10 connected to the gate electrodes (control electrodes) of a plurality of select gates 6 provided for each corresponding block 2 transmit information for writing to the memory cell 1. , Input / output lines for reading information stored in the memory cell 1, 11 ₁ to 1
1 ₂ provided for each main bit line 4 corresponding respectively, a transfer gate formed from driving N-channel MOS transistor between the main bit line 3 and the input and output lines 10 corresponding, the gate electrode and the second It is formed by the polysilicon layer of the layer. 12 _{1 to} 12 ₂ are provided for each corresponding transfer gate 11,
Corresponding transfer gate gate electrode (control electrode)
Is a column select signal line connected to.

Numeral 13 receives a row address signal, a write / erase control signal, a first high potential (eg 10 V) higher than the power source potential (eg 3.3 V) and a negative potential (eg -8 V), and receives it as a row address signal. On the basis of the write / erase control signal, a desired number of word lines 3 (the number of word lines in block units when erasing, one when writing and reading) is selected based on the write / erase control signal. Selective potential, for example, at the time of writing (in this example, the operation of pulling out the electrons accumulated in the floating gate electrode is referred to as writing), negative potential, and erasing (in this example, the operation of injecting electrons into the floating gate electrode is erased. Name)
It is a row decoder which sometimes gives a first high potential and a power source potential at the time of reading, and keeps the other word lines 3 at the ground potential.

Reference numeral 14 receives a part of the row address signal and a part of the column address signal, a write / erase control signal and a negative potential (eg, -8V), and receives a part of the write / erase control signal and the row address signal and the column. The source line 7 and the well potential line 8 are set to desired potentials based on a part of the address signal, for example, all the source lines 7 are made floating (electrically floating state) at the time of writing and all the well potential lines 8 are set. Is a ground potential, all source lines 7 and all well potential lines 8 are ground potentials at the time of reading, and source lines corresponding to the block 2 selected by a part of the row address signal and a part of the column address signal at the time of erasing. 7 / well potential line 8 is applied with a negative potential, and the other source lines 7 and well potential lines 8 are set to the ground potential.
It is a well decoder.

Reference numeral 15 denotes a part of the row address signal, a part of the column address signal, the write / erase control signal, and a second high potential (eg, 3.3 V) higher than the first high potential and lower than the first high potential. 6V), one of the plurality of block select signal lines 9 is selected based on a part of the row address signal and a part of the column address signal, and the selected block select signal line 9 is written / erased. A select gate decoder that applies a selection potential, for example, a second high potential at the time of writing, a ground potential at the time of erasing, a power source potential at the time of reading, based on a control signal, and maintains the state of the other block select signal lines 9 at the ground potential. .

Reference numeral 16 receives a column address signal, a write / erase control signal, and a second high potential (eg, 6V) higher than the power source potential (eg, 3.3V) and lower than the first high potential, and receives the column address signal as a column address signal. Based on the write / erase control signal, one of the plurality of column select signal lines 12 is selected based on the write / erase control signal.
The column decoder supplies a ground potential at the time of erasing and a power source potential at the time of reading, and keeps the other column select signal lines 12 at the ground potential. Reference numeral 17 receives the address signals (row address signals and column address signals are input in time series) input to the address input pads 18 ... 18, and receives the row decoder 13, the source / well decoder 14, and the select gate decoder 15 And an address buffer circuit for supplying an address signal to the column decoder 16.

A write / erase control signal 19 receives a write / erase control signal, data information, and a second high potential (eg, 6 V) higher than the power source potential (eg, 3.3 V) and lower than the first high potential. Indicates that writing is performed and that the data information input via the input / output pad 21 and the data input / output buffer 20 is to be programmed, a second high potential is applied to the input / output line 10 and at other times. Is a write circuit whose output is in a high impedance state, and 22 is a write / erase control signal,
When the erase control signal indicates the time of reading, the memory cell 1 which is activated is activated, a low potential (for example, 1.2 V) is applied to the input / output line 10, and whether or not a current flows is detected and amplified to be selected.
Is a sense amplifier for outputting read information from the input / output pad 21 via the data input / output buffer 20.

Reference numeral 23 is a first high voltage generating circuit for receiving a write / erase control signal and applying a first high potential (for example, 10 V) to the row decoder 13 based on the write / erase control signal. Reference numeral 24 is a write / erase control circuit. Receives an erase control signal,
A first high voltage generating circuit for applying a second high potential (for example, 6 V) to the select gate decoder 15, the column decoder 16 and the write circuit 19 based on the write / erase control signal, 25 is a write / erase control signal. In response to the write / erase control signal, the row decoder 13 and the source / well decoder 14 receive a negative potential (for example, −
8 V), a negative potential generating circuit, 26 is the row decoder 13, the source / well decoder 14, the select gate decoder 15, the column decoder 16 and the writing circuit 19
And sense amplifier 22 and first and second high voltage generation circuits 2
3 and 24 and a write / erase control circuit for supplying a write / erase control signal to the negative voltage generation circuit 25. Reference numeral 27 indicates a chip in the nonvolatile semiconductor memory device.

The row decoder 13, the source / well decoder 14, the select gate decoder 15, the column decoder 16, the address buffer circuit 17, the write circuit 19, the input / output buffer circuit 20, and the sense amplifier 2 are provided.
2, the first and second high voltage generation circuits 23 and 24, the negative voltage generation circuit 25, and the write / erase control circuit 26 write information in the memory cell 1 of the memory cell array, and store the information stored in the memory cell 1. A peripheral circuit for reading and erasing the information accumulated in the memory cell 1 is configured, and each has a plurality of N-channel MOS transistors and a plurality of P-channel MOS transistors. The gate electrode is formed of the second polysilicon layer.

Next, a semiconductor substrate 100 applied to the first embodiment for forming the flash memory configured as described above will be described with reference to FIG. FIG. 2 shows a main part of a semiconductor substrate applied to the first embodiment of the present invention, and the number of well regions and the like are not limited to those shown in FIG. In FIG. 2, 101
Is a first semiconductor layer made of a P-type silicon substrate having a high concentration (for example, about 1 × 10 ¹⁹ / cm ³ ), and 102 is epitaxially grown on the surface of the first semiconductor layer to a thickness of 1 to 10 μm. A P-type first impurity layer having an impurity concentration lower than that of the first semiconductor layer 101 (for example, 1 × 10 ¹⁵ / cm ³ and 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁸ ). 2 semiconductor layers.

Reference numeral 103 denotes an N-type first well region formed by interposing the second semiconductor layer 102 between the surface of the second semiconductor layer and the surface of the first semiconductor layer 101. For example, the depth is 1 to approximately 9 μm, and the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ . 104a, 1
Reference numeral 04b is a P-type second well region formed on the surface of the first well region, and has a depth of 0.5 to about 8.5, for example.
μm and the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / c
m is ^3. 105a, 105b, 105c are the second
On the surface of the first semiconductor layer 101.
The second semiconductor layer 102 is formed between the second semiconductor layer 102 and the surface of the second semiconductor layer 102, and has an impurity concentration higher than that of the second semiconductor layer 102 (for example, 1 × 10 ¹⁵ / cm ³ to 1 × 1).
0 ¹⁸⁾ in the third well region of the P type having, but the depth is 0.5 to approximately 8.5μm example, the first semiconductor layer 101 without the second semiconductor layer 102 is interposed It may be the depth of contact with the surface. 106a, 106b, 106
c is an N-type fourth well region formed on the surface of the second semiconductor layer 102 so as to be separated from the first well region 103, and has a depth of, for example, 0.5 to approximately 9 μm and contains impurities. The concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ .

The semiconductor substrate 100 having the above structure
FIG. 3 shows an idea when the flash memory having the configuration shown in FIG. 1 is formed. That is, the memory cells 1 that make up the memory cell array are arranged in the second well region 10
4a, 104b. In this case, a plurality of memory cells of each block unit are formed in the corresponding second well region corresponding to one of the plurality of second well regions for each block unit which is a batch erase unit. , For example, the memory cells 1 ₁₁ , 1 ₁₂ and 1 which form the block 2a.
_21, 1 ₂₂ are formed in the second well region 104a, the memory cell 1 _31, 1 ₃₂ of the block 2b, 1 _41, 1 ₄₂
Are formed in the second well region 104b.

On the other hand, a row decoder 13, a source / well decoder 14, a select gate decoder 15, a column decoder 16, an address buffer circuit 17, a write circuit 19, and an input / output buffer circuit 20 which constitute a peripheral circuit.
And sense amplifier 22 and first and second high voltage generation circuits 2
A plurality of N-channel MOS transistors in 3 and 24, the negative voltage generation circuit 25, and the write / erase control circuit 26 are formed in the third well regions 105a, 105b, and 105c, and a plurality of P-channel MOS transistors are formed in the fourth well region.
Are formed in the well regions 106a, 106b and 106c.

The N-channel MOS transistor serving as the select gate 6 formed in the memory cell array is similar to the memory cell 1 in that the second well in which the memory cell 1 is formed on the surface of the first well region 103. Well area 1
It is formed in a second well region (not shown) formed apart from 04a and 104b. Further, the electrical isolation between the plurality of memory cells 1 formed in each of the second well regions 104a and 104b is determined by the element isolation oxide film (LOCOS) formed so as to surround each memory cell 1 as shown in FIG. ) 107, the third and fourth well regions 105a, 105
b, 105c, 106a, 106b, 106c, the element isolation oxide film (LOCOS) 107 is formed so as to surround each MOS transistor as shown in FIG. Is done by.

Next, an example of a method of manufacturing the flash memory configured as described above, particularly, a method of manufacturing the semiconductor substrate 100 applied to this flash memory will be described mainly with reference to FIGS. First, as shown in FIG. 4, a high concentration of P having an impurity concentration of 1 × 10 ¹⁹ / cm ³ is used.
Is epitaxially grown on the surface of the first semiconductor layer 101 made of a silicon substrate (silicon wafer) of a mold by a generally known method, and the impurity concentration of the thickness of about 5 μm is 1 × 10 ¹⁵ / cm ³ . A certain low-concentration P-type epi layer 102a is formed. The concentration distribution from the surface of the epi layer 102a to the inside of the first semiconductor layer 101 at this time is as shown by the alternate long and short dash line A in FIG.

Then, P is formed on the surface of the epi layer 102a.
Of boron [B], which is a type impurity, at 100 keV, 1 × 1
The ion implantation layer 10 was implanted at a dose of 0 ¹² to 1 × 10 ¹³ / cm ^2.
2b is formed. Then, in a nitrogen atmosphere, 1130 to 1
The ion-implanted layer 10 is heat-treated at 180 ° C. for 10 hours.
2b boron [B] is thermally diffused, and as shown in FIG.
The entire epi layer 102a is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³
Which is a low concentration P-type second semiconductor layer 102. The impurity concentration of boron [B] at this time is shown by the solid line B in FIG.

Next, as shown in FIG. 6, a mask (not shown) other than a desired region (a region where a memory cell array is formed in this example) is masked, and N-type impurities are introduced through the mask. Phosphorus [P] is applied to the above desired area at 150 ke
V, 1 × 10 ¹² to 1 × 10 ¹³ / cm ² and then heat-treated at 1130 to 1180 ° C. for 5 hours in a nitrogen atmosphere to thermally diffuse phosphorus [P] to a depth of about 3 μm.
N with an impurity concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³
A first well region 103 of the mold is formed. The impurity concentration due to phosphorus [P] at this time is shown by the dotted line C in FIG.

Thereafter, as shown in FIG. 7, a desired region (a memory cell formation region corresponding to each block unit which is a batch erase unit in the memory cell array, and an N-channel MOS transistor forming a peripheral circuit are formed. Other than the region), a mask (not shown) is used, and boron [B], which is a P-type impurity, is implanted through the mask into the desired region at 100 keV and 1 × 10 ¹² to 1 × 10 ¹³ / cm ^2. , Boron implantation layers 104A, 104B, 105A, 10
5B and 105C are formed. Then remove the mask,
Boron injection layer 104A, 104B, 105A, 105
B and 105C are masked (not shown), and phosphorus [P], which is an N-type impurity, is applied through the mask to regions other than the boron implantation layers 104A, 104B, 105A, 105B, and 105C at 150 keV and 1 × 10 5. ¹² ~ 1 x 10 ¹³ / c
Implantation is performed at m ² to form phosphorus implantation layers 106A to 106D.

In this state, 1130 to 1 in a nitrogen atmosphere
Heat treatment is performed at 180 ° C. for several hours to form the boron-implanted layer 104.
A, 104B, 105A, 105B, 105C and boron [B] and phosphorus [P] in the phosphorus implantation layers 106A to 106D are thermally diffused, and as shown in FIG. 0.5 μm, impurity concentration 1 ×
The P-type second well regions 104a and 104b of 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ are formed on the surface of the second semiconductor layer 102 to a depth of approximately 1.5 μm and an impurity concentration of 1 × 10 ¹⁵ to 1 ×.
10 ¹⁸ / cm is ³ P-type third well region 106a
˜106 c, depth approximately 3 μm, impurity concentration 1 × 10 ¹⁵
˜1 × 10 ¹⁸ / cm ³ N-type fourth well region 1
06a-106c are formed, respectively. The impurity concentration due to boron [B] at this time is shown by a dotted line D in FIG.

In this way, the semiconductor substrate 100 shown in FIG. 2 is formed. Note that FIG. 8 and FIG. 2 show the semiconductor substrate 100 in the same state. In the semiconductor substrate 100 having the above-described structure, FIG.
The impurity profile shown in the cross section is as shown in FIG. As is clear from FIG. 10, the second
From the surface of the semiconductor layer 102 of the second to a depth of approximately 1.5 μm
Well region 104a is formed in the second well region 1
The first well region 103 is interposed between the bottom surface of 04a and the depth of about 3 μm, and the second semiconductor layer 102 extends from the bottom surface of the first well 103 to the surface of the first semiconductor layer 101.
Is intervening.

The impurity profile shown in the section BB 'in FIG. 8 is as shown in FIG. As is apparent from FIG. 11, the second semiconductor layer 102
From the surface of the third well region 10 to a depth of about 1.5 μm
5a is formed, and the second semiconductor layer 102 is formed from the bottom surface of the third well region 105a to the surface of the first semiconductor layer 101.
Is intervening. As shown in FIG. 11, the third well region 105a and the second semiconductor layer 1 are formed.
Since both 02 have the same conductivity type as the P type, the boundary between the third well region 105a and the second semiconductor layer 102 is not clear, and the impurity concentration gently decreases.

Further, the impurity profile shown in the section CC 'in FIG. 8 is as shown in FIG. As apparent from FIG. 12, the second semiconductor layer 102
To the depth of about 3 μm from the surface of the fourth well region 106a
From the bottom surface of the fourth well region 106a to the first
The second semiconductor layer 102 is interposed up to the surface of the semiconductor layer 101. In this example,
Since the first to fourth well regions are all formed by thermal diffusion, the impurity profile is a profile approximated by a Gaussian distribution in which the concentration near the surface is maximum.

Next, the semiconductor substrate 101 shown in FIG.
In order to electrically insulate the plurality of memory cells 1 formed in each of the second well regions 104a and 104b by a generally known method, element isolation is performed so as to surround each memory cell 1. An oxide film (LOCOS) 107 is formed and the third and fourth well regions 105 are formed.
a, 105b, 105c, 106a, 106b, 106
An element isolation oxide film (LOCOS) 107 is formed so as to surround each MOS transistor in order to electrically insulate a plurality of MOS transistors formed in each of the c.

Thereafter, a memory cell is formed in a region surrounded by the element isolation oxide film in the second well regions 104a and 104b by a generally known method,
An N channel MOS transistor is formed in a region surrounded by the element isolation oxide film in the third well regions 105a to 105c, and a P channel is formed in a region surrounded by the element isolation oxide film in the fourth well regions 106a to 106c. MO
Form an S-transistor. Then, by a generally known method, contact formation, wiring formation, etc. are performed,
The flash memory is completed.

Next, an erase operation (in this example, an electron is injected into the floating gate electrode) and a write operation (in this example, an electron accumulated in the floating gate electrode is extracted) of the flash memory configured as described above. The operation) and the read operation will be described with reference to FIG. In [Erase operation] This embodiment, which is collectively erased in units of blocks, now, memory cells 1 _11, 1 ₁₂ of the block 2a, 1 _21, 1 ₂₂ and collectively erase the memory cells of the other blocks 2b 1 ₃₁ , 1 ₃₂ , 1 ₄₁ and 1 ₄₂ are not erased.

When a signal for instructing batch erase from the outside is input to the write / erase control circuit 26, the write / erase control circuit 26 outputs a write / erase signal meaning erase to the row decoder 13 and the source / well decoder. 14, the select gate decoder 15, the column decoder 16, the write circuit 19, the sense amplifier 22, the first and second high voltage generating circuits 23 and 24, and the negative voltage generating circuit 25, and these circuits can be collectively erased. Eggplant on the other hand,
The address buffer circuit 17 includes an address input pad 18
An address signal, in this case, a row address signal and a column address signal, which are input in time series, which means that the block 2a is selected, is input.

Write / erase signal meaning erase from the write / erase control circuit 26 and the address buffer 17.
The row decoder 13 receives an address signal from the memory cell 1 ₁₁ of the block 2a to be selected, 1 _12, 1 _21, 1 ₂₂
The first high potential (for example, 10 V) from the first high voltage generation circuit 23 is applied to the word lines 3 ₁ , 3 ₂ connected to the memory cells 1 ₃₁ , 1 ₃₂ , 1 _{41 of} the unselected block 2b, 1
The potential of the word lines 3 ₃ and 3 ₄ connected to ₄₂ is maintained at the ground potential.

Further, the source / well decoder 14 which has received the write / erase signal indicating the erase from the write / erase control circuit 26 and the address signal from the address buffer 17 has the memory cell 1 ₁₁ of the selected block 2a.
1 _12, 1 _21, 1 applied to the source line 7a connected to ₂₂ a negative potential (e.g., -8 V) from the negative voltage generating circuit 25, the memory cell 1 ₃₁ of the block 2b is not selected, 1 _32, 1 _41, 1
The potential of the source line 7b connected to ₄₂ is maintained at the ground potential, and at the same time, the memory cell 1 ₁₁ of the selected block 2a,
1 _12, 1 _21, 1 ₂₂ substrate, i.e., have a negative potential (e.g., -8 V) from the negative voltage generating circuit 25 to the well potential line 8a connected to the second well region 104a shown in FIG. 2, The memory cells 1 ₃₁ , 1 _{32 of} the unselected block 2b,
1 _41, 1 ₄₂ substrate, that is, to maintain the potential of the well potential line 8b connected to the second well region 104b shown in FIG. 2 to the ground potential.

Further, the select gate decoder 15 which has received the write / erase signal meaning the erase from the write / erase control circuit 26 and the address signal from the address buffer 17 has all the block select signal lines 9a,
To maintain the 9b potential to the ground potential, the select gate 6 _1a to 6 _2b maintains the non-conductive state, the main bit lines 4 _1, 4 ₂
Electrically disconnected state and the sub-bit line 5 _1a to 5 _2b,
Sub bit line 5 _1a to 5 _{2 b} is in the electrically floating state (floating).

Furthermore, the write / erase control circuit 26
The column decoder receiving the write / erase signal meaning the erase from the column buffer and the address signal from the address buffer 17 maintains the potentials of all the column select signal lines 12 ₁ and 12 ₂ at the ground potential.
_{1 to} 11 ₂ maintain a non-conductive state, the input / output line 10 and the main bit lines 4 ₁ and 4 ₂ are electrically disconnected, and the main bit lines 4 ₁ and 4 ₂ are electrically floating. (Floating).

Further, the output of the write circuit 19 which has received the write / erase signal indicating the erase from the write / erase control circuit 26 is in the high impedance state, and the sense amplifier 22 is in the inactive state. is there.
Therefore, the memory cell 1 ₁₁ of the selected block 2a,
1 _12, 1 _21, in one _22, to the control gate electrode and the first high potential (e.g. 10V), the source region a negative potential (e.g. -8 V), the drain region into the floating substrate (second well Since the region 104a) is set to a negative potential (for example, −8V), it is between the source region and the control gate electrode, and between the substrate surface region located between the source region and the drain region, that is, between the channel region and the control gate electrode. Since a high electric field is applied to the electrons, electrons are injected from the channel region and the source region to the floating gate electrode by a tunnel phenomenon through the gate oxide film located immediately below the floating gate electrode and located above the channel region and the source region. As a result, electrons are accumulated in the floating gate electrode and the threshold voltage of the memory cell is increased, which means that the memory cell is erased.

[0063] On the other hand, in the memory cell 1 _31, 1 _32, 1 _41, 1 ₄₂ of the block 2b not selected, the control gate electrode ground potential, the source region is ground potential, because the drain region is in a floating , A high electric field is not generated between the control gate electrode and the source region, drain region, and channel region, electrons are not injected into the floating gate electrode, and electrons accumulated in the floating gate electrode are not extracted. It is a thing. In this way, batch erasing is performed for each block.

[0064] [Write Operation] Now, the information write (program) the memory cell 1 ₁₁ of the block 2a, the other memory cells 1 _12, 1 _21, 1 ₂₂ and the memory cell 1 ₃₁ of other blocks 2b, 1 _32, shall not write information for 1 _41, 1 _42.

When a signal for instructing programming is input to the programming / erasing control circuit 26 from the outside, the programming / erasing control circuit 26 sends a programming / erasing signal meaning programming to the row decoder 13 and the source / well decoder 1.
4, select gate decoder 15 and column decoder 16
Write circuit 19, sense amplifier 22, first and second
To the high voltage generating circuits 23 and 24 and the negative voltage generating circuit 25, so that these circuits can be written. On the other hand, an address signal is sent to the address buffer circuit 17 via the address input pad 18, in this case, the memory cell 1 _11.
A row address signal and a column address signal, which are input in a time series, which means that is selected, are input.

The row decoder 13 receiving the write / erase signal meaning the write from the write / erase control circuit 26 and the address signal from the address buffer 17,
A negative potential (for example, -8V) from the negative voltage generation circuit 25 is applied to the word line 3 ₁ connected to the memory cell 1 ₁₁ selected based on the row address signal, and the remaining word lines 3 ₂ ,
Keep all 3 ₃ and 3 ₄ potentials at ground potential.

Further, the source / well decoder 14 receiving the write / erase signal meaning the write from the write / erase control circuit 26 and the address signal from the address buffer 17 makes all the source lines 7a and 7b floating. Together with the substrate of all memory cells,
That is, the second well regions 104a and 10 shown in FIG.
The potential of the well potential lines 8a and 8b connected to 4b is maintained at the ground potential.

Further, the select gate decoder 15 which has received the write / erase signal meaning the write from the write / erase control circuit 26 and the address signal from the address buffer 17 receives a part of the row address signal and one of the column address signals. Memory cell 1 ₁₁ to select based on section
The second high potential (for example, 6 V) from the second high voltage generation circuit 24 is applied to the block select signal line 9a corresponding to the block in which the block exists, and the potential of the remaining block select signal line 9b is maintained at the ground potential. . As a result, the select gate 6 _1a connected to the block select signal line 9a,
6 _2a becomes conductive, main bit lines 4 ₁ , 4 ₂ and sub bit lines 5 _1a , 5 _2a are electrically connected, and sub bit lines 5 _1a , 5 _2a have main bit line 4 ₁ , 4 _second potential is transmitted. Further, the select gates 6 _1b and 6 _2b connected to the block select signal line 9b maintain the non-conduction state, and the main bit lines 4 ₁ and 4 ₂ are electrically disconnected from the sub bit lines 5 _1b and 5 _2b. In this state, the sub-bit lines 5 _1b and 5 _2b are in an electrically floating state.

Furthermore, the write / erase control circuit 26
The column decoder receiving the write / erase signal meaning the write from and the address signal from the address buffer 17 receives the main bit line 4 arranged in the column where the memory cell 1 ₁₁ selected based on the column address signal is arranged. ₁
To the column select signal line 12 ₁ connected to the transfer gate 11 ₁ connected to
The second high potential (for example, 6V) from is applied to maintain the potential of the remaining column select signal line 12 ₂ at the ground potential.
As a result, the transfer gate 11 ₁ connected to the column select signal line 12 ₁ becomes conductive, and the input / output line 1 1
0 and the main bit lines 4 ₁ , 4 ₂ are electrically connected,
The potential of the input / output line 10 is transmitted to the main bit line 4 ₁ .
Further, the transfer gate 11 ₂ connected to the column select signal line 12 ₂ maintains the non-conduction state, and the input / output line 1
0 and the main bit line 4 ₂ are electrically disconnected, and the main bit line 4 ₂ is in an electrically floating state.

In addition, the write circuit 19 which has received the write / erase signal meaning the write from the write / erase control circuit 26 receives the input / output signal from the input / output pad 21 via the data input / output buffer 20. Output line 1
A second high potential (for example, 6 V) from the second high voltage generating circuit 24 is applied to 0. The sense amplifier 22 which has received the write / erase signal meaning the write from the write / erase control circuit 26 is in the inactive state.

[0071] Thus, in the memory cell 1 ₁₁ to be selected, the control gate electrode a negative potential (e.g., -8
V), the source region is set to the floating state, the drain region is set to the second high potential (for example, 6 V), and the substrate (second well region 104a) is set to the ground potential. Since a high electric field is applied to the electrons, the electrons accumulated in the floating gate electrode are extracted to the drain electrode by the tunnel phenomenon via the gate oxide film located directly below the floating gate electrode and located on the drain electrode.

[0072] Further, in the word line 3 ₁ unselected memory cell 1 ₁₂ connected to the the control gate electrode a negative potential (e.g. -8 V), the source region is floated, the drain region floating, the substrate ( Since the second well region 104a) is set to the ground potential, a high electric field does not occur between the control gate electrode and the source region, drain region, and channel region, and the electrons accumulated in the floating gate electrode are extracted. In addition, no electrons are injected into the floating gate electrode.

[0073] Further, in the word line 3 ₂ of connected non-selected memory cells 1 _21, 1 _22, to the control gate electrode ground potential, the source region is floating,
Since the drain region is floating and the substrate (the second well region 104a) is at the ground potential, a high electric field does not occur between the control gate electrode and the source region, drain region, or channel region, and the floating gate electrode The electrons accumulated in the floating gate electrode are not extracted and the electrons are not injected into the floating gate electrode.

[0074] Furthermore, in the word line 3 _3, 3 ₄ connected to the non-selected memory cells 1 _31, 1 _32, 1 _41, 1 _42, to the control gate electrode ground potential, the source region is floating, Since the drain region is floating and the substrate (second well region 104a) is at the ground potential, the control gate electrode and the source region,
A high electric field is not generated between the drain region and the channel region, the electrons accumulated in the floating gate electrode are not extracted, and the electrons are not injected into the floating gate electrode. In this way, one memory cell 1 selected based on the row address signal and the column address signal input from the outside is selected.
Only for ₁₁ , the electrons accumulated in the floating gate electrode can be extracted to the drain electrode side, and writing can be performed.

[Read Operation] Now, the information stored in the memory cell 1 ₁₁ of the block 2a is read, and the other memory cells 1 ₁₂ , ₁₁₂₁ , ₁₂₂ and the other blocks 2 are read.
b of the memory cells 1 _31, 1 _32, for 1 _41, 1 ₄₂ shall not read the information stored.

When a signal for instructing read is input from the outside to the write / erase control circuit 26, the write / erase control circuit 26 outputs a write / erase signal meaning read out to the row decoder 13 and the source / well decoder 1.
4, select gate decoder 15 and column decoder 16
Write circuit 19, sense amplifier 22, first and second
To the high voltage generating circuits 23 and 24 and the negative voltage generating circuit 25, so that these circuits can be read. On the other hand, an address signal is sent to the address buffer circuit 17 via the address input pad 18, in this case, the memory cell 1 _11.
A row address signal and a column address signal, which are input in a time series, which means that is selected, are input.

The row decoder 13 which has received the write / erase signal meaning read from the write / erase control circuit 26 and the address signal from the address buffer 17 is
A power supply potential (for example, 3.3V) is applied to the word line 3 ₁ connected to the memory cell 1 ₁₁ selected based on the row address signal.
And all the remaining word lines 3 ₂ , 3 ₃ , and 3 ₄ are maintained at the ground potential.

Further, the source / well decoder 14 which has received the write / erase signal meaning read from the write / erase control circuit 26 and the address signal from the address buffer 17 has all the source lines 7a and 7b and all the source lines 7a and 7b. The potential of the substrate of the memory cell, that is, the well potential lines 8a and 8b connected to the second well regions 104a and 104b shown in FIG. 2 is maintained at the ground potential.

Further, the select gate decoder 15 which has received the write / erase signal meaning read from the write / erase control circuit 26 and the address signal from the address buffer 17 receives a part of the row address signal and one of the column address signals. Memory cell 1 ₁₁ to select based on section
The power supply potential (for example, 3.3 V) is applied to the block select signal line 9a corresponding to the block in which the block exists, and the potential of the remaining block select signal line 9b is maintained at the ground potential.
As a result, the select gates 6 _1a and 6 _2a connected to the block select signal line 9a become conductive, and the main bit lines 4 ₁ and 4 ₂ and the sub bit lines 5 _1a and 5 _2a are electrically connected. . Further, the select gates 6 _1b and 6 _2b connected to the block select signal line 9b maintain the non-conduction state, and the main bit lines 4 ₁ and 4 ₂ are electrically disconnected from the sub bit lines 5 _1b and 5 _2b. In this state, the sub-bit lines 5 _1b and 5 _2b are in an electrically floating state.

Furthermore, the write / erase control circuit 26
The column decoder receiving the write / erase signal meaning read from the memory cell and the address signal from the address buffer 17 receives the main bit line 4 arranged in the column in which the memory cell 1 ₁₁ selected based on the column address signal is arranged. ₁
A power supply potential is applied to the column select signal line 12 ₁ connected to the transfer gate 11 ₁ connected to, and the potential of the remaining column select signal line 12 ₂ is maintained at the ground potential. As a result, the transfer gate 11 ₁ connected to the column select signal line 12 ₁ becomes conductive, and the input / output line 10 and the main bit lines 4 ₁ , 4 ₂ are electrically connected. Further, the transfer gate 11 ₂ connected to the column select signal line 12 ₂ maintains the non-conduction state, and the input / output line 10 and the main bit line 4 ₂ are electrically disconnected.
The main bit line 4 ₂ is in the electrically floating state (floating).

Further, the write circuit 19 which has received the write / erase signal indicating the read from the write / erase control circuit 26 has its output in the high impedance state, and therefore has no influence on the input / output line 10. . The sense amplifier 22, which has received the write / erase signal indicating the read from the write / erase control circuit 26, is activated and applies a low potential (for example, 1.2 V) to the input / output line 10.
It detects whether or not a current flows through the input / output line 10, amplifies the detected information, and outputs it as read information to the input / output pad via the data input / output buffer 20.

[0082] Therefore, when the memory cell 1 ₁₁ for selecting is written information, i.e., if the electrons accumulated in the floating gate electrode is pulled out,
Since the threshold voltage of memory cell 1 ₁₁ is low,
By applying the power supply potential to the word line 3 ₁ , the memory cell 1 ₁₁ is in a conductive state. Therefore, when a low potential is applied to the input / output line 10 from the sense amplifier 22,
A current flows through the source line 7a via the transfer gate 11 ₁ , the main bit line 4 ₁ , the select gate 6 _1a , the sub bit line 5 _1a and the memory cell ₁₁ 1, and the sense amplifier 22 senses it and reads out the read information " It is output to the data input / output buffer 20 as 1 ″.

On the other hand, when information is not written in the selected memory cell 1 ₁₁ , that is, when electrons are accumulated in the floating gate electrode, the threshold voltage of the memory cell 1 ₁₁ is high. The memory cell ₁₁ 1 remains non-conductive even when the power supply potential is applied to the word line 3 ₁ . Therefore, the sense amplifier 2
Even if a low potential is applied to the input / output line 10 from 2, the current does not flow in the source line 7a. Output to the input / output buffer 20.

At this time, since all the remaining word lines 3 _{2 to} 3 ₄ to which the selected memory cell 1 ₁₁ is not connected are set to the ground potential, the memory cells connected to these word lines 3 _{2 to} 3 ₄ are connected. 1 _{21-1 42} regardless all the stored information, because it maintains the non-conductive state, never the path the current flows occurs through the memory cells 1 _{21-1 42.} Although the remaining memory cells 1 ₁₂ connected to the word line 3 ₁ to which the selected memory cell 1 ₁₁ is connected are turned on or off depending on the stored information, these memory cells 1 ₁₂ Main bit line 4 connected to
_{Since 2} is electrically disconnected from the input / output line 10 by the transfer gate 11 ₂ , there is no path for current to flow through these memory cells 1 ₁₂ .
In this way, only for one memory cell 1 _11, which is selected based on the row address signal and column address signal input from the outside, sense amplifiers 22 whether or not a current flows on the basis of the stored information Can be detected, so that the information stored in the memory cell ₁₁ 1 can be read.

The flash memory configured as described above has the following advantages. First
In addition, the memory cells 1 can be collectively erased in block units.
Second, a negative potential (e.g., -8 V) higher in absolute value than the power supply potential is applied to the source region of the memory cell 1 and the second well region 104 at the time of batch erasing in block units, and the drain region of the memory cell at the time of writing. Since a second high potential (for example, 6 V) higher than the power supply potential is applied to the first well region 103, it is essentially prone to latch-up due to a parasitic thyristor transistor, but the first well region 103
And the high-concentration first semiconductor layer 101, the low-concentration second semiconductor layer 1 formed by epitaxial growth
02 is interposed, the resistance of the second semiconductor layer 102 is significantly lowered, and the latch-up resistance is improved.

Third, tunnel oxidation of the memory cell 1 in which electrons are injected and extracted on the surface of the second well region 104 formed on the surface of the second semiconductor layer 102 formed by epitaxial growth. Since the gate insulating film made of a film is formed, the second well region 10 is formed.
4, the density of impurities (eg oxygen concentration) and defect density on the surface can be easily controlled, and those having a low density of impurities and defect can be obtained. Therefore, a high quality gate insulating film can be formed, a long life, and a memory that can be rewritten many times. The cell is obtained. Fourth, since the low-concentration second semiconductor layer 102 formed by epitaxial growth is interposed between the first well region 103 and the high-concentration first semiconductor layer 101, the first well The breakdown voltage of the region 103 with respect to the second semiconductor layer 102 can be set high, and the punch-through breakdown voltage between the second well region 104 and the second semiconductor layer 102 is also improved.

Although the first embodiment has the structure in which the first well region 103, the third well region 105 and the fourth well region 106 are in contact with each other, as shown in FIG. In addition, the first well region 103, the third well region 105, and the fourth well region 106 may be separated from each other, that is, the second semiconductor layer 102 may be interposed between the well regions. , Again,
As shown in FIG. 4, the first well region 103, the third well region 105, and the fourth well region 106 may have a structure in which they overlap each other.

Example 2. FIG. 15 shows a second embodiment of the present invention. In the first embodiment described above, the first well region 103 has a plurality of second well regions 104a and 10a.
4b is provided, the first well regions 103a and 103b are provided for the second well regions 104a and 104b, that is, for each block unit obtained by dividing a plurality of memory cells into blocks. Corresponding to each block unit, the first and second well regions 103 and 104
Is the same as that described in the first embodiment. Even with such a configuration, the same effect as that of the first embodiment is obtained.

Example 3. 16 and 17 show a third embodiment of the present invention. The first high voltage generating circuit 23 and / or the second high voltage generating circuit 24 in the first embodiment described above are shown in FIGS. It is characterized by having the configuration shown, and other points are the same as those shown in the first embodiment. FIG. 16 is a circuit diagram of a high voltage generation circuit, in which D1 to Dn are diode elements connected in series between a power supply potential node Vcc to which a power supply potential (for example, 3.3V) is applied and an output node OUT. so,
As shown in (b), it is composed of a diode-connected NPN bipolar transistor in which a base electrode and a collector electrode are connected. C1 to Cn are capacitive elements in which one electrode is connected to the cathodes of the corresponding diode elements D1 to Dn, and the other electrode of the capacitive element located at an odd number alternately supplies the power supply potential and the ground potential. Receiving the repeated clock signal φ, the other electrode of the capacitive element located at an even-numbered position has the clock signal φ
And a clock signal / φ that alternately repeats the power supply potential and the ground potential.

When the high-voltage generating circuit configured as described above is incorporated in the semiconductor substrate 100 in the first embodiment described above, FIG.
It is as shown in 7. In FIG. 17, 10
3 _{1 to} 103 _n are first wells for forming the memory cell 1 in which the second semiconductor layer 102 is interposed between the surface of the second semiconductor layer 102 and the surface of the first semiconductor layer 101. The N-type first well region formed at the same time as the region 103 and at a distance from each other serves as a collector region of a diode-connected NPN bipolar transistor. And the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ .

104 _{1 to} 104 _n are formed on the respective surfaces of the first well regions 103 _{1 to} 103 _n , and the second well regions 104a and 10a in which the memory cell 1 is formed are formed.
The second P-type well region formed at the same time as 4b serves as the base region of the diode-connected NPN bipolar transistor, and serves as the second well regions 104a and 104b.
Similarly, the depth is, for example, 0.5 to approximately 8.5 μm, and the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ . 1
07 _{1 to} 107 _n are the second well regions 104 ₁ to 1
04 _n is an emitter region of a diode-connected NPN bipolar transistor formed of an N type diffusion region formed on each surface of the _n 04 _n , for example, a source region and a drain region of the memory cell 1 and a source of an N channel MOS transistor of a peripheral circuit. It is formed at the same time as the region and the drain region.

108 _{1 to} 108 _n are formed on the surfaces of the first well regions 103 _{1 to} 103 _n , respectively, and have an N-type collector concentration higher than the impurity concentration of the _first well regions 103 _{1 to} 103 _n. Electrode diffusion region, 1091 to 109
n are formed on the respective surfaces of the second well region 104 ₁ -104 _n, the second well region 104 ₁ to 1
This is a P-type base electrode diffusion region having a higher concentration than the impurity concentration of 04 _n .

In the high voltage generating circuit configured as described above, the potentials of the anode and the cathode of the diode element increase as they approach the output node. That is, the potential of the first well region 103 shown in FIG. 17 also becomes high. As a result, although it is necessary to increase the junction breakdown voltage between the first well region 103 and the second semiconductor layer 102, in the third embodiment, the second semiconductor layer 102 is formed by epitaxial growth. Since the semiconductor layer has a low concentration as described above, a necessary and sufficient junction breakdown voltage is obtained.

Example 4. 18 to 20 show a fourth embodiment of the present invention, which is different from the above-described first embodiment only in the method of forming the first well region 103, and other points are the same as the above-described embodiments. Similar to Example 1. Therefore, a method of manufacturing a semiconductor substrate will be described below in order to mainly describe differences from the first embodiment.

First, as in the first embodiment, as shown in FIGS.
As shown in FIG. 3, a low concentration P-type epi layer 102a is formed on the surface of the first semiconductor layer 101 (the epi layer 102 at this time is formed).
The concentration distribution from the surface of a to the inside of the first semiconductor layer 101 is the same as that of the first embodiment, and is shown by a chain line A in FIG. ), And thereafter, boron [B], which is a P-type impurity, is implanted into the surface of the epi layer 102a, and heat treatment is performed in a nitrogen atmosphere to thermally diffuse the boron [B] to form the epi layer 10.
2a is a low-concentration P-type second semiconductor layer 102. The impurity concentration of boron [B] at this time is the same as that in the first embodiment, and is shown by the solid line B in FIG.

Next, as shown in FIG. 7, a mask (not shown) except for a desired region (in this example, a region where a memory cell array is formed and a region where a P channel MOS transistor of a peripheral circuit is formed) is formed. Then, phosphorus [P], which is an N-type impurity, is passed through the mask so that the peak is located at a predetermined depth in the desired region by 1 to 5 Me.
V, 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² ion implantation,
To form a bottom region 103A of the first well region 103 to form a bottom region 106A ₀ ~106C ₀ in the fourth well region 106a-106c. At this time, the impurity concentration of the bottom region 103A and the bottom regions 106A _{0 to} 106C ₀ should be 20 and as shown by a dotted line C ₁ , the impurity concentration peak (1 × It is formed so as to have 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ . Although ion implantation is also performed to form a region in which the P-channel MOS transistor of the peripheral circuit is formed, that is, the fourth well region, ion implantation may not be particularly performed in this region.

Thereafter, the same as in the above-described first embodiment (see FIG. 19).
In FIG. 3), masks other than a desired region (a region where a memory cell forming region corresponding to each block unit which is a batch erase unit in the memory cell array and a region where an N channel MOS transistor forming a peripheral circuit is formed) are formed (see FIG. Boron [B], which is a P-type impurity, is implanted into the desired region through the mask, and the boron implantation layer 104 is formed.
A, 104B, 105A, 105B and 105C are formed. After that, the mask is removed, and the boron implantation layer 104A,
A mask (not shown) is used to mask 104B, 105A, 105B, and 105C, and phosphorus [P], which is an N-type impurity, is added to the boron implantation layers 104A, 104B, and 10 through the mask.
The phosphorus-implanted layer 10 is formed in a region other than 5A, 105B, and 105C.
6A to 106D are formed.

In this state, heat treatment is performed to thermally diffuse boron [B] and phosphorus [P] to form the first well region 103 by the bottom region 103A and the phosphorus implantation layer 106D as shown in FIG. , This first well region 10
3 P-type second well regions 104a and 104b on the surface
To form P-type third well regions 105a to 105c on the surface of the second semiconductor layer 102, and to form bottom regions 106A _{0 to} 106C ₀ and phosphorus implantation layers 106A to 106C on the surface of the second semiconductor layer 102. Then, N-type fourth well regions 106a to 106c are formed. The impurity concentration due to boron [B] at this time is the same as in Example 1, and is shown by a dotted line D in FIG.

The semiconductor substrate 100 is thus formed. Semiconductor substrate 1 configured in this way
No. 00, the impurity profile shown in the section AA ′ in FIG. 20 is as shown in FIG.
As is clear from FIG. 22, the second well region 104a extends from the surface of the second semiconductor layer 102 to a depth of approximately 1.5 μm.
Is formed, and the first well region 103 having a peak of the impurity concentration is interposed at a depth of approximately 2 μm from the bottom surface of the second well region 104 a to a depth of approximately 2.5 μm, and the first well region 103 is formed. From the bottom surface of the well region 103 to the first semiconductor layer 101
The second semiconductor layer 102 is interposed up to the surface of.

The impurity profile shown in the section BB 'in FIG. 20 is the same as that in the first embodiment, and is shown in FIG. As apparent from FIG. 23, the second semiconductor layer 102
From the surface of the third well region 10 to a depth of about 1.5 μm
5a is formed, and the second semiconductor layer 102 is formed from the bottom surface of the third well region 105a to the surface of the first semiconductor layer 101.
Is intervening. Note that, as shown in FIG. 23, the third well region 105 a and the second semiconductor layer 1
Since both 02 have the same conductivity type as the P type, the boundary between the third well region 105a and the second semiconductor layer 102 is not clear, and the impurity concentration gently decreases.

Further, the impurity profile shown in the section CC 'in FIG. 20 is as shown in FIG. As is clear from FIG. 24, the second semiconductor layer 10
The second well region 1 from the surface of 2 to a depth of approximately 2.5 μm
06a is formed and has a peak of impurity concentration at a position of a depth of approximately 2 μ, and the second semiconductor layer 102 extends from the bottom surface of the fourth well region 106a to the surface of the first semiconductor layer 101.
Is intervening.

The fourth embodiment thus formed has the same effect as that of the first embodiment, and also has the first well region 103 (and the fourth well regions 106a to 106).
At the time of forming c), since the ion implantation method which has the peak of the impurity concentration at a predetermined depth is adopted,
This has the advantage that the center depth of the bottom region of the first well region 103 and the thickness in the depth direction can be freely selected.

Example 5. 25 and 26 show Example 5 of the present invention, which is different from Example 1 described above only in the method of forming the second semiconductor layer 102, and other points are the same as in Example 1 described above. Similar to Example 1. Therefore, a method of manufacturing a semiconductor substrate will be described below in order to mainly describe differences from the first embodiment.

First, as shown in FIG. 25, generally, on the surface of the first semiconductor layer 101 formed of a high-concentration P-type silicon substrate (silicon wafer) having an impurity concentration of 1 × 10 ¹⁹ / cm ³ , Epitaxial growth is performed by a known method, and an impurity concentration of about 5 μm and an impurity concentration of 1 × 10 5
A low-concentration P-type epi layer 102a having a density of ¹⁵ / cm ³ is formed. The concentration distribution from the surface of the epi layer 102a to the inside of the first semiconductor layer 101 at this time is similar to that of the first embodiment, and is shown by a chain line A in FIG.

Thereafter, P-type impurity boron [B] is added in an amount of 1.5 to 5 Me so that the peak of the impurity concentration is located at a predetermined depth from the surface of the epi layer 102a.
Implantation is performed with V at 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² , and the ion implantation layer 102c is formed at a position of a predetermined depth. The impurity concentration due to boron [B] at this time is shown by the solid line B in FIG.
It is as shown by 1.

Next, it is formed in the same manner as in the first embodiment.
That is, as shown in FIG. 6, a mask (not shown) other than a desired region (a region where a memory cell array is formed in this example) is masked, and phosphorus [P] which is an N-type impurity is passed through the mask. Into the desired region, and then heat treatment is performed in a nitrogen atmosphere to thermally diffuse phosphorus [P],
A first well region 103 of the mold is formed. The impurity concentration due to phosphorus [P] at this time is the same as that in the first embodiment,
As shown by the dotted line C in FIG. 27, the first well region 103 is located at a position shallower than the peak of the impurity concentration at a predetermined position of the second semiconductor layer 102. .

Thereafter, as shown in FIG. 7, a desired region (a memory cell formation region corresponding to each block unit which is a batch erase unit in the memory cell array, and an N channel MOS transistor forming a peripheral circuit are formed. Other than the region), a mask (not shown) is used, and boron [B], which is a P-type impurity, is implanted into the desired region through the mask, and boron implantation layers 104A, 104B, 105A,
105B and 105C are formed. Then, the mask is removed, and the boron implantation layers 104A, 104B, 105A, 10
5B and 105C are masked (not shown), and phosphorus [P], which is an N-type impurity, is added through the mask to the boron implantation layers 104A, 104B, 105A, 105B, and 105C.
Implanting into regions other than the above, phosphorus-implanted layers 106A to 106D are formed.

In this state, heat treatment is performed in a nitrogen atmosphere to thermally diffuse boron [B] and phosphorus [P], and then, as shown in FIG.
As shown in FIG. 3, P-type second well regions 104a and 104b are formed on the surface of the first well region 103, and P-type third well regions 105a to 105a are formed on the surface of the second semiconductor layer 102.
5c and N-type fourth well regions 106a to 106c are formed. The impurity concentration of boron [B] at this time is the same as that in the first embodiment, and is shown by a dotted line D in FIG.

In the semiconductor substrate 100 having such a structure, the impurity profile shown in the section AA 'in FIG. 26 is as shown in FIG. FIG. 28
As is apparent, the second well region 104a is formed from the surface of the second semiconductor layer 102 to a depth of approximately 1.5 μm, and the depth from the bottom surface of the second well region 104a is approximately 3.
The first well region 103 is interposed between 5 μm, and
The second semiconductor layer 102 is interposed from the bottom surface of the first well 103 to the surface of the first semiconductor layer 101. Moreover, the peak of the impurity concentration in the second semiconductor layer 102 is located between the bottom surface of the first well 103 and the surface of the first semiconductor layer 101.

The impurity profile shown in the section BB 'in FIG. 26 is as shown in FIG. As apparent from FIG. 29, the second semiconductor layer 102
From the surface to the depth of about 3 μm
From the bottom of the third well region 105a to the first
The second semiconductor layer 102 is interposed up to the surface of the semiconductor layer 101. Moreover, the second semiconductor layer 102
The peak of the impurity concentration in is located between the bottom surface of the third well 105a and the surface of the first semiconductor layer 101.

Further, the impurity profile shown in the section CC ′ in FIG. 26 is as shown in FIG. As is apparent from FIG. 30, the second semiconductor layer 10
4th well region 1 from the surface of 2 to a depth of approximately 3.5 μm
06a are formed, and the second semiconductor layer 10 is formed from the bottom surface of the fourth well region 106a to the surface of the first semiconductor layer 101.
2 is interposed. Moreover, the peak of the impurity concentration in the second semiconductor layer 102 is the fourth well 10
It is located between the bottom surface of 6a and the surface of the first semiconductor layer 101.

The fifth embodiment thus formed has the same effects as those of the first embodiment, and also has a predetermined depth, that is, the first and the second semiconductor layers 102. Third and fourth well regions 103, 105 and 1
Since the ion implantation method in which the peak of the impurity concentration is made to exist between 06 and the first semiconductor layer 101 is adopted, the central depth and the thickness in the depth direction at this portion can be freely selected. It has advantages.

In the fifth embodiment, the formation of the first well region 103 is performed by ion implantation of impurities so that the peak of the impurity concentration is located at a predetermined depth as shown in the fourth embodiment. It may be formed as described above.

Example 6. 31 to 34 show Embodiment 6 of the present invention, which differs from Embodiment 1 described above only in the method of forming the second semiconductor layer 102, that is, the epitaxially grown epi layer is used as it is. The semiconductor layer 102 is used as the semiconductor layer 102, and other points are the same as those in the first embodiment. Therefore, a method of manufacturing a semiconductor substrate will be described below in order to mainly describe differences from the first embodiment.

First, as shown in FIG. 31, generally, on the surface of the first semiconductor layer 101 formed of a high-concentration P-type silicon substrate (silicon wafer) having an impurity concentration of 1 × 10 ¹⁹ / cm ³ , Epitaxial growth is performed by a known method, and an impurity concentration of about 5 μm and an impurity concentration of 1 × 10 5
^A second semiconductor layer 102 is formed of a low-concentration P-type epi layer having a concentration of ¹⁵ / cm ³ . Second semiconductor layer 1 at this time
The concentration distribution from the surface of 02 to the inside of the first semiconductor layer 101 is as shown by the alternate long and short dash line A in FIG.

Thereafter, as shown in FIG. 32, a mask (not shown) other than a desired region (a region where a memory cell array is formed in this example) is masked, and phosphorus, which is an N-type impurity, is masked through the mask. [P] was added to the surface layer in the desired region at 150 keV, 1 × 10 ¹² to 1 × 10 ¹³ / c.
m ² and then 1130 to 11 in a nitrogen atmosphere
Heat treatment is performed at 80 ° C. for 5 hours to thermally diffuse phosphorus [P] to a depth of about 3.5 μm and an impurity concentration of 1 × 10 ¹⁵ to 1 ×.
An N-type first well region 103 of 10 ¹⁸ / cm ³ is formed. The impurity concentration due to phosphorus [P] at this time is shown in FIG.
5 is indicated by a dotted line C2.

Then, the first well region 103 at this time
The conditions for forming are determined as follows. That is, the impurity diffusion in the LSI process simply follows the Fickian diffusion equation, and if this is solved one-dimensionally with respect to the diffusion from a certain amount of diffusion source, the following equation (1) is obtained, and the distribution of the impurity concentration is given by the following equation (1). ) Is the Gaussian distribution. C (x, t) = (Q / √πDt) × exp (−x ² / 4Dt) (1) where Q is the total amount of impurity atoms of the implanted impurities in the surface layer of the second semiconductor layer 102, D is the diffusion coefficient, x is the distance (depth) from the surface of the second semiconductor layer 102, and t is the diffusion time. Further, 2√Dt is generally called a diffusion distance and corresponds to 1σ of Gaussian distribution.

On the other hand, in consideration of the impurity concentration required for the first well region 103 and the junction breakdown voltage of the PN junction surface at the bottom of the first well region 103, the peak impurity concentration of the first well region 103 is Second semiconductor layer 10
It was found that it is necessary to take the difference of the density with 2 from about 2 digits. Therefore, the bottom surface of the first well region 103 and the first well region 103
The second semiconductor layer 102 is formed between the second semiconductor layer 102 and the surface of the semiconductor layer 101.
In order to intervene, that is, to leave as little as possible, the depth that is two orders of magnitude lower than the peak concentration of the first well region 103 (located on the surface of the second semiconductor layer 102 in this sixth embodiment) is the second. It must be less than or equal to the thickness of the semiconductor layer 102.

That is, in the Gaussian distribution, if the distance from the position of the peak concentration is 2σ, the concentration decreases by two digits from the peak concentration, so 2σ must be less than the thickness of the second semiconductor layer 102. When 2σ is equal to or more than the thickness of the second semiconductor layer 102, the bottom surface of the first well region 103 is in contact with or overlaps with the surface of the first semiconductor layer 101. As a result, 4√Dt (=
2σ) is less than the thickness of the second semiconductor layer 102, so that the second semiconductor layer 102 is interposed between the bottom surface of the first well region 103 and the surface of the first semiconductor layer 101. You can The first well region 103 is formed by satisfying such conditions.

Thereafter, as shown in FIG. 33, a desired region (a memory cell formation region corresponding to each block unit which is a batch erase unit in the memory cell array, and an N channel MOS transistor forming a peripheral circuit are formed. Other than the region), a mask (not shown) is used, and boron [B], which is a P-type impurity, is implanted into the desired region through the mask at 100 keV, 1 × 10 ¹² to 1 × 10 ¹³ / cm ^2. , Boron implantation layers 104A, 104B, 105A, 10
5B and 105C are formed. Then remove the mask,
Boron injection layer 104A, 104B, 105A, 105
B and 105C are masked (not shown), and phosphorus [P], which is an N-type impurity, is applied through the mask to regions other than the boron implantation layers 104A, 104B, 105A, 105B, and 105C at 150 keV and 1 × 10 5. ¹² ~ 1 x 10 ¹³ / c
Implantation is performed at m ² to form phosphorus implantation layers 106A to 106D.

In this state, in a nitrogen atmosphere, 1130 to 1
Heat treatment is performed at 180 ° C. for several hours to form the boron-implanted layer 104.
A, 104B, 105A, 105B, 105C and boron [B] and phosphorus [P] in the phosphorus injection layers 106A to 106D are thermally diffused, and as shown in FIG. 34, a depth of approximately 1 μm is formed on the surface of the first well region 103. , Impurity concentration is 1 × 1
The P-type second well regions 104a and 104b having a density of 0 ¹⁵ to 1 × 10 ¹⁸ / cm ³ are formed on the surface of the second semiconductor layer 102 to a depth of approximately 2 μm and an impurity concentration of 1 × 10 ¹⁵ to 1 × 10 ^18.
/ Cm ³ of P-type third well regions 106a-10
6c, depth of about 3.5 μm, and impurity concentration of 1 × 10 ¹⁵ 〜
1 × 10 ¹⁸ / cm ³ N-type fourth well region 10
6a-106c are formed, respectively. The impurity concentration of boron [B] at this time is as shown by the dotted line D in FIG.

In the semiconductor substrate 100 having such a structure, the impurity profile shown in the section AA 'in FIG. 34 is as shown in FIG. Fig. 36
As apparent from the above, the second well region 104a is formed from the surface of the second semiconductor layer 102 to a depth of about 1 μm, and the depth from the bottom surface of the second well region 104a is about 3.5.
The first well region 103 is interposed between μm, and the second semiconductor layer 102 is interposed from the bottom surface of the first well 103 to the surface of the first semiconductor layer 101. That is, 4√Dt (= 2σ) is the second semiconductor layer 10
Since the ion-implanted impurities are diffused into the surface layer of the second semiconductor layer 102 on the basis of the diffusion condition satisfying the thickness less than 2, the thickness of the bottom surface of the first well region 103 and the high concentration of the impurity are surely increased. The low-concentration second semiconductor layer 102 is interposed between the surface of the first semiconductor layer 101 and the surface of the first semiconductor layer 101.

The impurity profile shown in the section BB 'in FIG. 34 is as shown in FIG. As apparent from FIG. 37, the second semiconductor layer 102
From the surface of the third well region 105a to a depth of approximately 2 μm
From the bottom of the third well region 105a to the first
The second semiconductor layer 102 is interposed up to the surface of the semiconductor layer 101.

Further, the impurity profile shown in the section CC ′ in FIG. 34 is as shown in FIG. 38. As apparent from FIG. 38, the second semiconductor layer 10
4th well region 1 from the surface of 2 to a depth of approximately 3.5 μm
06a are formed, and the second semiconductor layer 10 is formed from the bottom surface of the fourth well region 106a to the surface of the first semiconductor layer 101.
2 is interposed. The sixth embodiment formed in this way also has the same effect as the first embodiment.

Example 7. 39 to 42 show Embodiment 7 of the present invention, which is different from Embodiment 1 described above only in the method of forming the second semiconductor layer 102 and the method of forming the first well region 103. That is, the epitaxially grown epi layer is used as it is for the second semiconductor layer 102.
And to form the first well region 103 by ion-implanting impurities to a predetermined depth.
The other points are the same as in the first embodiment described above.
Therefore, a method of manufacturing a semiconductor substrate will be described below in order to mainly describe differences from the first embodiment.

First, as shown in FIG. 39, generally, on the surface of the first semiconductor layer 101 formed of a high-concentration P-type silicon substrate (silicon wafer) having an impurity concentration of 1 × 10 ¹⁹ / cm ³ , Epitaxial growth is performed by a known method, and an impurity concentration of about 3 μm and an impurity concentration of 1 × 10
^A second semiconductor layer 102 is formed of a low-concentration P-type epi layer having a concentration of ¹⁵ / cm ³ . Second semiconductor layer 1 at this time
The concentration distribution from the surface of 02 to the inside of the first semiconductor layer 101 is as shown by the alternate long and short dash line A in FIG.

Then, as shown in FIG. 40, a mask (not shown) other than the desired region (the region where the memory cell array is formed in this example) is masked, and phosphorus, which is an N-type impurity, is masked through the mask. [P] is set to 1.75 Me so that the peak is located at a predetermined depth in the desired region.
V, 1 × 10 ¹³ / cm ² implantation, first well region 1
No. 03 bottom region 103A and the fourth well regions 106a to 106c bottom regions 106A ₀ to 1 are formed.
To form 06C ₀ . At this time, the impurity concentration of the bottom region 103A and the bottom regions 106A _{0 to} 106C ₀ has a peak of the impurity concentration at a position of 1.7 μm in depth from the surface of the second semiconductor layer 102, as shown by the solid line C ₃ in FIG. (1 x 10
¹⁵ to 1 × 10 ¹⁸ / cm ³ ). The region where the P-channel MOS transistor of the peripheral circuit is formed, that is, the fourth well region 1
Ion implantation is also performed to form 06a to 106c, but ion implantation may not be particularly performed in this region.

Then, the first well region 103 at this time
The conditions for forming the bottom region 103A are determined as follows. That is, the LSS theory is used as a general solution of implanted ions in ion implantation of impurities in the LSI process. The projective range Rp and its variance ΔRp based on the LSS theory are “Projected Range St
atistics in Semiconductors "(by JFGibbons eta
l.), the injection distribution N (x) can be easily approximated by a Gaussian distribution having a mean value Rp and a variance ΔRp, and the following expression (2) is obtained. ) Is the Gaussian distribution. N (x) = (NI / √ (2πΔRp)) × exp (− (x−Rp) ² / 2ΔRp ² ) (2) where NI is the ion implantation amount per unit area and x is the second.
Is the distance (depth) from the surface of the semiconductor layer 102.

On the other hand, in consideration of the impurity concentration required for the first well region 103 and the junction breakdown voltage of the PN junction surface at the bottom of the first well region 103, the peak impurity concentration of the first well region 103 is Second semiconductor layer 10
It was found that it is necessary to take the difference of the density with 2 from about 2 digits. Therefore, the bottom surface of the first well region 103 and the first well region 103
The second semiconductor layer 102 is formed between the second semiconductor layer 102 and the surface of the semiconductor layer 101.
In order to intervene, that is, to leave even a little, the peak concentration of the first well region 103 (in the seventh embodiment, it is located inside the second semiconductor layer 102, for example, at a depth of 1.7 μm) is 2 or more. The second semiconductor layer 10 has a depth that drops by a digit.
It must be less than 2 thickness.

That is, (Rp + 3ΔRp) must be less than the thickness of the second semiconductor layer 102. (Rp + 3
If ΔRp) is equal to or more than the thickness of the second semiconductor layer 102, the bottom surface of the first well region 103 will come into contact with or overlap the surface of the first semiconductor layer 101. As a result, (Rp + 3ΔR
p) is less than the thickness of the second semiconductor layer 102 so that the second semiconductor layer 102 is interposed between the bottom surface of the first well region 103 and the surface of the first semiconductor layer 101. You can Satisfying such conditions,
Well region 103 is formed.

Thereafter, as shown in FIG. 41, a desired region (a memory cell formation region corresponding to each block unit which is a batch erase unit in the memory cell array and an N channel MOS transistor forming a peripheral circuit are formed. Other than the region), a mask (not shown) is used, and boron [B], which is a P-type impurity, is implanted into the desired region through the mask at 100 keV, 1 × 10 ¹² to 1 × 10 ¹³ / cm ^2. , Boron implantation layers 104A, 104B, 105A, 10
5B and 105C are formed. Then remove the mask,
Boron injection layer 104A, 104B, 105A, 105
B and 105C are masked (not shown), and phosphorus [P], which is an N-type impurity, is applied through the mask to regions other than the boron implantation layers 104A, 104B, 105A, 105B, and 105C at 150 keV and 1 × 10 5. ¹² ~ 1 x 10 ¹³ / c
Implantation is performed at m ² to form phosphorus implantation layers 106A to 106D.

In this state, in a nitrogen atmosphere, 1130 to 1
Heat treatment is performed at 180 ° C. for several hours to form the boron-implanted layer 104.
A, 104B, 105A, 105B, 105C and boron [B] and phosphorus [P] in the phosphorus injection layers 106A to 106D are thermally diffused, and as shown in FIG.
A first well region 103 having a thickness of 5 μm, a depth of approximately 1 μm on the surface of the first well region 103, and an impurity concentration of 1 × 10.
^The P-type second well regions 104a and 104b having a density of ¹⁵ to 1 × 10 ¹⁸ / cm ³ are formed on the surface of the second semiconductor layer 102 to a depth of approximately 1.5 μm and an impurity concentration of 1 × 10 ¹⁵ to 1 × 10.
¹⁸ / cm ³ P-type third well regions 106a-1
06c, depth approximately 2.5 μm, impurity concentration 1 × 10 ¹⁵
˜1 × 10 ¹⁸ / cm ³ N-type fourth well region 1
06a-106c are formed, respectively. The impurity concentration of boron [B] at this time is as shown by the dotted line D in FIG.

In the semiconductor substrate 100 thus configured, the impurity profile shown in the section AA 'in FIG. 42 is as shown in FIG. Figure 44
As is apparent from the above, the second well region 104a is formed from the surface of the second semiconductor layer 102 to a depth of about 1 μm, and the depth of the second well region 104a is about 2.5 from the bottom surface of the second well region 104a.
The first well region 103 is provided between the first well region 103 and the first semiconductor layer 101 from the bottom surface of the first well region 103.
The second semiconductor layer 102 is interposed up to the surface of. In addition, the bottom surface of the second well region 104a and the second
One peak of the impurity in the first well region 103 exists between the semiconductor layer 102 and the semiconductor layer 102. That is, since (Rp + 3ΔRp) is ion-implanted to a predetermined depth of the second semiconductor layer 102 based on the ion-implantation conditions that satisfy the condition that (Rp + 3ΔRp) is less than the thickness of the second semiconductor layer 102, it is possible to reliably perform the first ion implantation. A low-concentration second semiconductor layer 102 is interposed between the bottom surface of the well region 103 and the surface of the high-concentration first semiconductor layer 101, and 1 is formed under the second well region 104.
It has two peak concentrations.

The impurity profile shown in the section BB 'in FIG. 42 is as shown in FIG. As is clear from FIG. 45, the second semiconductor layer 102
From the surface of the third well region 10 to a depth of about 1.5 μm
5a is formed, and the second semiconductor layer 102 is formed from the bottom surface of the third well region 105a to the surface of the first semiconductor layer 101.
Is intervening.

Furthermore, the impurity profile shown in the section CC 'in FIG. 42 is as shown in FIG. As is apparent from FIG. 46, the second semiconductor layer 10
The second well region 1 from the surface of 2 to a depth of approximately 2.5 μm
06a are formed, and the second semiconductor layer 10 is formed from the bottom surface of the fourth well region 106a to the surface of the first semiconductor layer 101.
2 is interposed. The fourth well region 106 has a peak of the impurity concentration at the surface layer of the second semiconductor layer 102 and at a position at a depth of 1.7 μm from the second semiconductor layer 102.

The seventh embodiment thus formed has the same effect as that of the first embodiment, and also has the first well region 103 (and the fourth well regions 106a to 106a).
At the time of forming c), since the ion implantation method which has the peak of the impurity concentration at a predetermined depth is adopted,
This has the advantage that the center depth of the bottom region of the first well region 103 and the thickness in the depth direction can be freely selected.

In the first to sixth embodiments, the specific thickness of the second semiconductor layer 102 is 5 μm, and in the seventh embodiment, the second semiconductor layer 102 has the second thickness. As a specific value of the thickness of the semiconductor layer 102, 3
μm is shown, but the present invention is not limited to this.
It may be in the range of 1 to 10 μm. However, due to the difference in the thickness of the second semiconductor layer 102, specific optimum values such as the impurity implantation amount, the ion implantation acceleration energy, the heat treatment temperature for impurity diffusion, and the heat treatment time may be changed. is there.

In the first to seventh embodiments described above, the epi layer for forming the second semiconductor layer 102 (the first conductivity type impurities are not implanted by ion implantation). Impurity concentration of 1 × 10 ¹⁵ / c
m ³ is shown, but it is not limited to this.
The impurity concentration of the epi layer for forming the second semiconductor layer 102 can be freely selected from 1 × 10 ¹¹ / cm ³ to 1 × 10 ¹⁶ / cm ³ which is sufficiently lower than the concentration of the well region. However, due to the difference in the impurity concentration of the second semiconductor layer 102, specific optimum values such as the impurity implantation amount, the ion implantation acceleration energy, the heat treatment temperature for impurity diffusion, and the heat treatment time may of course be changed. is there.

Further, although the impurity concentration of the first semiconductor layer 101 is 1 × 10 ¹⁹ / cm ³ in the examples 1 to 7 described above, the present invention is not limited to this. The impurity concentration of the first semiconductor layer 101 is 1 × 10 ¹⁸ / cm ³ to 1 ×, which is sufficiently higher than the concentration of the well region.
It can be freely selected up to 10 ²⁰ / cm ³ .

[0140]

According to the first aspect of the present invention, a first semiconductor layer of the first conductivity type and a first semiconductor layer on the surface of the first semiconductor layer are provided.
A second semiconductor layer of the first conductivity type epitaxially grown having an impurity concentration lower than that of the second semiconductor layer, and a second semiconductor layer on the surface of the second semiconductor layer and on the surface of the first semiconductor layer. A second well region of the second conductivity type formed with the semiconductor layer interposed therebetween, a second well region of the first conductivity type formed on the surface of the first well region,
A third well region of the first conductivity type formed on the surface of the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer, and a first well region separated from the surface of the second semiconductor layer. A semiconductor substrate having a fourth well region of the second conductivity type formed by the above, a first semiconductor element formed in the second well region of the semiconductor substrate, and a third well region of the semiconductor substrate. A second semiconductor element formed on the semiconductor substrate and a third semiconductor element formed on a fourth well region of the semiconductor substrate, and the first well region is formed from the surface of the semiconductor substrate.
A concentration peak and a concentration peak are formed in the depth direction toward the first semiconductor layer.
At a position deeper than the concentration peak from the surface of the semiconductor substrate
First, including the part where the concentration drops by two digits from the concentration peak value
It has a distribution of impurities of two conductivity types and has a semi-conducting part where it falls by two digits.
The depth from the surface of the body substrate is less than or equal to the thickness of the second semiconductor layer.
Since the low concentration second semiconductor layer is interposed between the first semiconductor layer of the first well region and a high concentration, and improved latch-up immunity, the second well region and the second The punch-through breakdown voltage with the semiconductor layer is improved, and the junction breakdown voltage between the first well region and the second semiconductor layer is improved.

According to a second aspect of the present invention, a first semiconductor layer of the first conductivity type is epitaxially grown on the surface of the first semiconductor layer with an impurity concentration lower than that of the first semiconductor layer. A second semiconductor layer of the first conductivity type,
A second well region of the second conductivity type formed on the surface of the second semiconductor layer with the second semiconductor layer interposed between the surface of the first semiconductor layer and the first semiconductor layer, and the first well region of the second conductivity type. A second well region of the first conductivity type formed on the surface of the well region;
A third well region of the first conductivity type formed on the surface of the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer, and a first well region separated from the surface of the second semiconductor layer. A non-volatile memory cell formed in the second well region of the semiconductor substrate, and the third well region of the semiconductor substrate. Second conductivity type MOS formed in
A transistor and a first conductivity type MOS transistor formed in a fourth well region of the semiconductor substrate ;
The well region extends from the surface of the semiconductor substrate to the first semiconductor layer
Concentration peak in the depth direction toward and from this concentration peak
The concentration peak value at a deep position from the surface of the semiconductor substrate.
Impurity of the second conductivity type, including the part where the concentration drops by two digits
From the surface of the semiconductor substrate that has a distribution of
Is less than or equal to the thickness of the second semiconductor layer, the low-concentration second semiconductor layer is interposed between the first well region and the high-concentration first semiconductor layer, and the latch-up resistance is increased. Is improved,
The punch-through breakdown voltage between the second well region and the second semiconductor layer is improved, the junction breakdown voltage between the first well region and the second semiconductor layer is improved, and the impurity or defect density of the gate insulating film is improved. This has the effect that a non-volatile semiconductor memory device having a small number of pixels can be obtained.

A third aspect of the present invention provides a memory cell array having a plurality of memory cells, writing information in the memory cells of the memory cell array, reading information stored in the memory cells, and storing information stored in the memory cells. A P-type first semiconductor in which a plurality of memory cells of a memory cell array are divided into a plurality of blocks each including a peripheral circuit for erasing, and the erasing operation is collectively performed in each block. A layer, a P-type second semiconductor layer epitaxially grown on the surface of the first semiconductor layer having an impurity concentration lower than that of the first semiconductor layer, and a surface of the second semiconductor layer, The N-type first well region formed by interposing the second semiconductor layer between the surface of the first semiconductor layer and the surface of the first well region are spaced apart from each other. A plurality of second well region P-type formed Te, formed on the surface of the second semiconductor layer, a second
Having an impurity concentration higher than that of the semiconductor layer of
The first well on the third well region of the mold and on the surface of the second semiconductor layer.
A well region and an N-type fourth well region formed separately from each other, and each block unit corresponds to one of the plurality of second well regions. A memory cell is formed in the corresponding second well region, and at least some N-channel MOS transistors of the plurality of N-channel MOS transistors forming the peripheral circuit are formed in the third well region, forming the peripheral circuit. At least a part of the plurality of P-channel MOS transistors is formed in the fourth well region, and the first well region is a half well.
Depth direction from the surface of the conductor substrate to the first semiconductor layer
The concentration peak and the concentration peak of the semiconductor substrate
The concentration drops by two digits from the concentration peak value at a deep position from the surface.
Has a distribution of N-type impurities including
The second semiconductor layer has a depth from the surface of the semiconductor substrate
Since the thickness of the first well region can be independently applied to the second well region,
Is interposed between the first well region and the high-concentration first semiconductor layer to improve the latch-up resistance, and the punch-through breakdown voltage between the second well region and the second semiconductor layer is improved. Is improved, the junction breakdown voltage between the first well region and the second semiconductor layer is improved, and a nonvolatile semiconductor memory device in which the density of impurities and defects in the gate insulating film is small can be obtained.

According to a fourth aspect of the present invention, a memory cell array having a plurality of memory cells, information is written in the memory cells of the memory cell array, information stored in the memory cells is read out, and information stored in the memory cells is read. A peripheral circuit for erasing, a plurality of memory cells of the memory cell array are divided into a plurality of blocks, and an erasing operation is collectively performed in block units. A semiconductor layer, a P-type second semiconductor layer epitaxially grown on the surface of the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer, and a surface of the second semiconductor layer; , A plurality of N-type first wells formed so as to be separated from each other and having a second semiconductor layer interposed between the first well and the surface of the first semiconductor layer. A band, a plurality of first well region a plurality of second well region of P-type which are formed on each surface, is formed on the surface of the second semiconductor layer,
A P-type third well region having an impurity concentration higher than that of the second semiconductor layer, and an N-type fourth well region formed on the surface of the second semiconductor layer away from the first well region. A semiconductor substrate having a well region and corresponding to one of the plurality of second well regions for each block unit, a plurality of memory cells of each block unit are formed in the corresponding second well region, A plurality of N channel MOs forming a circuit
At least a portion of the S-channel N-channel MOS transistors are formed in the third well region, and at least a portion of the P-channel MOS transistors forming the peripheral circuit are formed in the fourth well region. And a plurality of first wells
The region extends from the surface of the semiconductor substrate toward the first semiconductor layer.
Concentration peak in the depth direction of and half more than this concentration peak
Concentration from the value of the concentration peak deeper than the surface of the conductor substrate
The distribution of N-type impurities including
However, the depth from the surface of the semiconductor substrate where it falls by two digits is the first
Since the thickness of the second semiconductor layer is not more than the thickness of the second semiconductor layer , the first well region can independently apply a potential to the second well region,
The low-concentration second semiconductor layer is interposed between the first well region and the high-concentration first semiconductor layer, and the latch-up resistance is improved, and the second well region and the second semiconductor layer are formed. The punch-through breakdown voltage between the two is improved, the junction breakdown voltage between the first well region and the second semiconductor layer is improved, and a nonvolatile semiconductor memory device in which the impurity and defect densities of the gate insulating film are small can be obtained. Is to have.

According to a fifth aspect of the present invention, a memory cell array having a plurality of memory cells, information is written in the memory cells of the memory cell array, information stored in the memory cells is read out, and information stored in the memory cells is read. A peripheral circuit for erasing, wherein the peripheral circuit has a booster circuit that receives a power supply potential applied to a power supply potential node and outputs a boosted potential higher than this power supply potential. A first semiconductor layer, a second semiconductor layer of the first conductivity type epitaxially grown on the surface of the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer, and the second semiconductor layer. A first well region of the second conductivity type formed on the surface of the first semiconductor layer with a second semiconductor layer interposed between the first well region and the surface of the first semiconductor layer; A second well region of the first conductivity type formed, and a third well region of the first conductivity type formed on the surface of the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer. The first semiconductor layer on the surface of the second semiconductor layer.
And a semiconductor substrate having a second well region of the second conductivity type formed apart from the well region, a semiconductor element forming an output stage of the booster circuit is formed in the second well region, and At least a part of the MOS transistors of the second conductivity type forming the circuit are formed in the third well region, and at least a part of the MOS transistors of the first conductivity type forming the peripheral circuit. Since the MOS transistor is formed in the fourth well region, the low-concentration second semiconductor layer is interposed between the first well region and the high-concentration first semiconductor layer,
Latch-up resistance is improved, punch-through breakdown voltage between the second well region and the second semiconductor layer is improved, and the first well region and the second semiconductor for the semiconductor element forming the output stage of the booster circuit are improved. This has the effect of improving the junction breakdown voltage with the layer.

[0145]

The sixth invention of the present invention is the first invention, which has an impurity concentration lower than that of the first semiconductor layer by epitaxial growth on the surface of the first semiconductor layer of the first conductivity type.
A step of forming a second conductive type semiconductor layer, and a step of ion-implanting a second conductive type impurity so that an impurity concentration peak is located at a predetermined depth from the surface of the second semiconductor layer. Forming a second well region of the second conductivity type on the surface of the second semiconductor layer, and a peak position of the impurity concentration at a predetermined position in the first well region on the surface of the first well region. Forming a second well region of the first conductivity type further above, and forming an impurity concentration higher than that of the second semiconductor layer on the surface of the second semiconductor layer.
A step of forming a conductive type third well region, a step of forming a second conductive type fourth well region on the surface of the second semiconductor layer away from the first well region, and a second A step of forming the first semiconductor element in the well region, a step of forming the second semiconductor element in the third well region, and a step of forming the third semiconductor element in the fourth well region are provided. Therefore, the low-concentration second semiconductor layer is interposed between the first well region and the high-concentration first semiconductor layer, the latch-up resistance is improved, and the second well region and the second semiconductor layer are improved. The punch-through breakdown voltage between the first well region and the second semiconductor layer is improved, and the peak impurity concentration is formed at a predetermined depth from the surface of the second semiconductor layer. Ion implantation is performed so that the defect at the bottom of the first well region is Those having the effect that the profile of the object density can be freely selected.

According to a seventh aspect of the present invention, a step of forming an epi layer by epitaxial growth on the surface of the first semiconductor layer of the first conductivity type and impurities at a predetermined depth from the surface of the epi layer. Forming a second semiconductor layer of a first conductivity type having an impurity concentration lower than that of the first semiconductor layer by ion-implanting an impurity of the first conductivity type so that a concentration peak is located; and Forming a second well region of the second conductivity type on the surface of the second semiconductor layer; forming a second well region of the first conductivity type on the surface of the first well region; Forming on the surface of the second semiconductor layer a third well region of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer; and forming a second conductivity type of the second well layer on the surface of the second semiconductor layer. The fourth well region is formed separately from the first well region. And that step, the first to the second well region
Since the step of forming the semiconductor element, the step of forming the second semiconductor element in the third well region, and the step of forming the third semiconductor element in the fourth well region are provided, The second semiconductor layer has a first well region and a high concentration of the first well region.
Intervening between the first well region and the second semiconductor layer, the latch-up resistance is improved, and the punch-through breakdown voltage between the second well region and the second semiconductor layer is improved. The junction breakdown voltage with the layer is improved, and ion implantation is performed so that the peak of the impurity concentration is located in the second semiconductor layer at a predetermined depth from the surface of the epi layer. The effect is that the profile of the impurity concentration can be freely selected.

An eighth aspect of the present invention is the step of forming an epi layer by epitaxial growth on the surface of the first semiconductor layer of the first conductivity type, and the step of forming impurities at a predetermined depth from the surface of the epi layer. Forming a second semiconductor layer of a first conductivity type having an impurity concentration lower than that of the first semiconductor layer by ion-implanting an impurity of the first conductivity type so that a concentration peak is located; and The second impurity concentration peak should be located at a predetermined depth from the surface of the second semiconductor layer.
A step of implanting a conductivity type impurity by ion implantation, wherein a peak position of the second semiconductor layer is interposed between the surface of the second semiconductor layer and the surface of the first semiconductor layer; A step of forming a first well region, a step of forming a second well region of the first conductivity type on the surface of the first well region, and a step of forming a second semiconductor layer on the surface of the second semiconductor layer. Forming a third well region of the first conductivity type having an impurity concentration higher than the impurity concentration; and separating a fourth well region of the second conductivity type from the first well region on the surface of the second semiconductor layer. Forming step, forming a first semiconductor element in the second well region, forming a second semiconductor element in the third well region, and forming a third semiconductor element in the fourth well region. Since the step of forming a semiconductor element is provided,
Is interposed between the first well region and the high-concentration first semiconductor layer, the latch-up resistance is improved, and the punch-through breakdown voltage between the second well region and the second semiconductor layer is improved. Is improved, the junction breakdown voltage between the first well region and the second semiconductor layer is improved, and ion implantation is performed so that the peak of the impurity concentration is located at a predetermined depth from the surface of the second semiconductor layer. Therefore, the impurity concentration profile at the bottom of the first well region can be freely selected, and the second semiconductor layer is ion-implanted so that the impurity concentration peak is located at a predetermined depth from the surface of the epi layer. Therefore, there is an effect that the profile of the impurity concentration at the bottom of the second semiconductor layer can be freely selected.

[0149]

[0150]

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor substrate 100 applied to Example 1 of the present invention.

FIG. 3 is a cross-sectional view of essential parts showing Embodiment 1 of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the first embodiment of the present invention in the order of steps.

5A to 5C are cross-sectional views showing the manufacturing process of the semiconductor substrate 100 applied to the first embodiment of the present invention in process order.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the first embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the first embodiment of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the first embodiment of the present invention in the order of steps.

FIG. 9 is a diagram showing individual impurity profiles in the manufacture of the semiconductor substrate 100 applied to the first embodiment of the present invention.

10 is a diagram showing a profile of impurities in the AA ′ cross section of FIG. 8;

FIG. 11 is a diagram showing a profile of impurities in a BB ′ cross section of FIG. 8;

FIG. 12 is a diagram showing an impurity profile in a CC ′ cross section of FIG. 8;

FIG. 13 is a sectional view showing another example of the semiconductor substrate 100 applied to the first embodiment of the present invention.

FIG. 14 is a sectional view showing still another example of the semiconductor substrate 100 applied to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view of a main part showing a second embodiment of the present invention.

FIG. 16 is a circuit diagram showing a booster circuit of a high voltage generation circuit applied to Embodiment 3 of the present invention.

FIG. 17 is a main-portion cross-sectional view showing an example in which a booster circuit of a high voltage generation circuit applied to Embodiment 3 of the invention is incorporated in a semiconductor substrate.

FIG. 18 is a cross-sectional view showing the sequence of steps in manufacturing a semiconductor substrate 100 applied to Example 4 of the invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the fourth embodiment of the present invention in the order of steps.

FIG. 20 is a cross-sectional view showing the process step of manufacturing a semiconductor substrate 100 applied to the fourth example of the present invention.

FIG. 21 is a diagram showing individual impurity profiles in the manufacture of the semiconductor substrate 100 applied to the fourth embodiment of the present invention.

22 is a diagram showing the profile of impurities in the AA ′ cross section of FIG. 20.

FIG. 23 is a diagram showing an impurity profile in a BB ′ cross section of FIG. 20;

FIG. 24 is a diagram showing an impurity profile in a CC ′ cross section of FIG. 20;

FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the fifth embodiment of the present invention in the order of steps.

FIG. 26 is a cross-sectional view showing the process in order of manufacturing the semiconductor substrate 100 applied to the fifth embodiment of the present invention.

FIG. 27 is a diagram showing individual impurity profiles in the manufacture of the semiconductor substrate 100 applied to the fifth embodiment of the present invention.

FIG. 28 is a diagram showing an impurity profile in the AA ′ cross section of FIG. 26;

FIG. 29 is a diagram showing an impurity profile in a BB ′ cross section of FIG. 26;

FIG. 30 is a diagram showing an impurity profile in a CC ′ cross section of FIG. 26.

FIG. 31 is a cross-sectional view showing the process step of manufacturing a semiconductor substrate 100 applied to the sixth embodiment of the present invention.

FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the sixth embodiment of the present invention in the order of steps.

FIG. 33 is a sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the sixth embodiment of the present invention in the order of steps.

FIG. 34 is a cross-sectional view showing the process of manufacturing the semiconductor substrate 100 applied to the sixth embodiment of the present invention in the order of steps.

FIG. 35 is a diagram showing individual impurity profiles in the manufacture of the semiconductor substrate 100 applied to the sixth embodiment of the present invention.

FIG. 36 is a diagram showing a profile of impurities in the AA ′ cross section of FIG. 34.

FIG. 37 is a diagram showing an impurity profile in a BB ′ cross section of FIG. 34;

FIG. 38 is a diagram showing an impurity profile in a CC ′ cross section of FIG. 34.

FIG. 39 is a sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the seventh embodiment of the present invention in the order of steps.

FIG. 40 is a cross-sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the seventh embodiment of the present invention in the order of steps.

41A to 41D are cross-sectional views showing a sequence of process steps in the manufacture of a semiconductor substrate 100 applied to the seventh embodiment of the present invention.

FIG. 42 is a sectional view showing the manufacturing process of the semiconductor substrate 100 applied to the seventh embodiment of the present invention in the order of steps.

FIG. 43 is a diagram showing individual impurity profiles in the manufacture of the semiconductor substrate 100 applied to the seventh embodiment of the present invention.

FIG. 44 is a diagram showing an impurity profile in the AA ′ cross section of FIG. 42;

45 is a diagram showing a profile of impurities in the BB ′ cross section of FIG. 42;

FIG. 46 is a diagram showing a profile of impurities in a CC ′ cross section of FIG. 42.

[Explanation of symbols]

1 ₁₁ to 1 ₄₁ memory cells, 2a to 2b blocks, 3 ₁
To 3 ₄ word lines, ₄₁ to ₂ word lines, 5 _1a to 5 _2b
Main bit line, 7a to 7b source line, 100 semiconductor substrate, 101 first semiconductor layer, 102 second semiconductor layer, 103 first well region, 104a to 104b
Second well region, 105a to 105c Third well region, 106a to 106b Fourth well region.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-77153 (JP, A) JP-A-62-85460 (JP, A) JP-A-3-105971 (JP, A) JP-A-3- 290960 (JP, A) JP 5-326858 (JP, A) JP 6-216380 (JP, A) JP 5-55530 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/10 491 H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] 1. A first semiconductor layer of a first conductivity type and an epitaxially grown first conductivity type having an impurity concentration lower than that of the first semiconductor layer on the surface of the first semiconductor layer. The second semiconductor layer is formed on the surface of the second semiconductor layer, and the second semiconductor layer is formed between the second semiconductor layer and the surface of the first semiconductor layer.
Second conductivity type first well region formed with the semiconductor layer interposed therebetween, a first conductivity type second well region formed on the surface of the first well region, and the second A third well region of the first conductivity type formed on the surface of the semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer; and the first well region on the surface of the second semiconductor layer. A semiconductor substrate having a second well region of the second conductivity type formed separately from the semiconductor substrate, a first semiconductor element formed in the second well region of the semiconductor substrate, and a third well of the semiconductor substrate a second semiconductor element formed in the region, a third semiconductor element formed on a fourth well region of the semiconductor substrate, the first well region from the surface of the semiconductor substrate said first Towards the semiconductor layer
Concentration peak in the depth direction of and above this concentration peak
The value of the above concentration peak at a position deep from the surface of the semiconductor substrate
Of the second conductivity type including a portion where the concentration drops by two digits from
The semiconductor having a distribution of impurities and falling by two digits.
The depth from the surface of the substrate is less than or equal to the thickness of the second semiconductor layer.
Is a semiconductor integrated circuit device. 2. A first semiconductor layer of a first conductivity type, and an epitaxially grown first conductivity type having an impurity concentration lower than that of the first semiconductor layer on a surface of the first semiconductor layer. The second semiconductor layer is formed on the surface of the second semiconductor layer, and the second semiconductor layer is formed between the second semiconductor layer and the surface of the first semiconductor layer.
Second conductivity type first well region formed with the semiconductor layer interposed therebetween, a first conductivity type second well region formed on the surface of the first well region, and the second A third well region of the first conductivity type formed on the surface of the semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer; and the first well region on the surface of the second semiconductor layer. A semiconductor substrate having a second well region of the second conductivity type formed separately from the semiconductor substrate, and a diffusion of the second conductivity type formed in the second well region of the semiconductor substrate and connected to a corresponding source line. A source region made of a layer, a drain region made of a second conductive type diffusion layer formed apart from the source region and connected to a corresponding bit line, and a drain region located between the source region and the drain region. Tunneling acid on the second well region Nonvolatile memory having a floating gate electrode formed via a gate oxide film made of an oxide film, and a control gate electrode arranged to face the floating gate electrode via an interlayer insulating film and connected to a corresponding word line A cell, a source region formed in the third well region of the semiconductor substrate and formed of a second conductive type diffusion layer, and a drain region formed of a second conductive type diffusion layer separated from the source region. , A second conductivity type MOS having a gate electrode formed on the third well region located between the source region and the drain region via a gate oxide film.
A transistor, a source region formed in the fourth well region of the semiconductor substrate and formed of a diffusion layer of the first conductivity type, and a drain region formed of a diffusion layer of the first conductivity type formed apart from the source region. A gate electrode formed on the fourth well region located between the source region and the drain region via a gate oxide film.
A conductive type MOS transistor is provided , and the first well region extends from the surface of the semiconductor substrate toward the first semiconductor layer.
Concentration peak in the depth direction of and above this concentration peak
The value of the above concentration peak at a position deep from the surface of the semiconductor substrate
Of the second conductivity type including a portion where the concentration drops by two digits from
The semiconductor having a distribution of impurities and falling by two digits.
The depth from the surface of the substrate is less than or equal to the thickness of the second semiconductor layer.
A non-volatile semiconductor memory device. 3. A source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information, and a control gate electrode connected to a corresponding word line. A memory cell array having a plurality of memory cells having the memory cell; and a peripheral circuit for writing information to the memory cell of the memory cell array, reading information stored in the memory cell, and erasing the information stored in the memory cell, In a memory cell array in which a plurality of memory cells are divided into a plurality of blocks and an erase operation is collectively performed in block units, a P-type first semiconductor layer and a first semiconductor layer An epitaxially grown P-type second layer having an impurity concentration lower than that of the first semiconductor layer is formed on the surface. A conductor layer, an N-type first well region formed on the surface of the second semiconductor layer with the second semiconductor layer interposed between the surface of the first semiconductor layer, and A plurality of P-type second well regions formed separately from each other on the surface of the first well region and the impurity concentration of the second semiconductor layer formed on the surface of the second semiconductor layer A semiconductor substrate having a P-type third well region having a high impurity concentration and an N-type fourth well region formed on the surface of the second semiconductor layer so as to be separated from the first well region. Each of the plurality of second well regions is provided for each block unit.
A plurality of memory cells of each block unit are formed in the corresponding second well region, and at least a part of the plurality of N-channel MOS transistors forming the peripheral circuit is the above-mentioned A plurality of P's which are formed in the well region of 3 and constitute the peripheral circuit.
At least a portion of the P-channel MOS transistor channel MOS transistor is formed in the fourth well region, the first well region, toward the surface of the semiconductor substrate to said first semiconductor layer
Concentration peak in the depth direction of and above this concentration peak
The value of the above concentration peak at a position deep from the surface of the semiconductor substrate
N-type impurities including the part where the concentration drops by 2 digits
Of the semiconductor substrate, which has a distribution of
A non-volatile semiconductor memory device characterized in that the depth from the surface is equal to or less than the thickness of the second semiconductor layer . 4. A source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information, and a control gate electrode connected to a corresponding word line. A memory cell array having a plurality of memory cells having the memory cell; and a peripheral circuit for writing information to the memory cell of the memory cell array, reading information stored in the memory cell, and erasing the information stored in the memory cell, In a memory cell array in which a plurality of memory cells are divided into a plurality of blocks and an erase operation is collectively performed in block units, a P-type first semiconductor layer and a first semiconductor layer An epitaxially grown P-type second layer having an impurity concentration lower than that of the first semiconductor layer is formed on the surface. The conductor layer and the surface of the second semiconductor layer are formed separately from each other, and the second semiconductor layer is formed between the surface of the first semiconductor layer and the conductor layer. N
Type first well regions, a plurality of P type second well regions respectively formed on the surfaces of the plurality of first well regions, and a surface of the second semiconductor layer. A P-type third well region having an impurity concentration higher than that of the second semiconductor layer;
A semiconductor substrate having an N-type fourth well region formed separately from the first well region on the surface of the semiconductor layer, and one of the plurality of second well regions is provided for each block unit.
A plurality of memory cells of each block unit are formed in the corresponding second well region, and at least a part of the plurality of N-channel MOS transistors forming the peripheral circuit is the above-mentioned P-channel MOS transistors formed in the third well region and forming the peripheral circuit, at least some of the P-channel MOS transistors are formed in the fourth well region, and the plurality of first well regions are From the surface of the semiconductor substrate to the first semiconductor layer
Concentration peak in the depth direction of and above this concentration peak
The value of the above concentration peak at a position deep from the surface of the semiconductor substrate
N-type impurities including the part where the concentration drops by 2 digits
Of the semiconductor substrate, which has a distribution of
A non-volatile semiconductor memory device characterized in that the depth from the surface is equal to or less than the thickness of the second semiconductor layer . 5. A source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information, and a control gate electrode connected to a corresponding word line. A memory cell array having a plurality of memory cells having the memory cell; and a peripheral circuit for writing information to the memory cell of the memory cell array, reading information stored in the memory cell, and erasing the information stored in the memory cell, The peripheral circuit receives the power supply potential applied to the power supply potential node,
In a device having a booster circuit that outputs a boosted potential higher than the power supply potential, a first conductivity type first semiconductor layer and an impurity concentration of the first semiconductor layer on the surface of the first semiconductor layer An epitaxially grown second semiconductor layer of the first conductivity type having a low impurity concentration, and the second semiconductor layer interposed between the surface of the second semiconductor layer and the surface of the first semiconductor layer. Formed on the surface of the first semiconductor region, the second well region of the first conductivity type formed on the surface of the first well region, and the first well region of the second conductivity type formed on the surface of the second semiconductor layer. A third well region of the first conductivity type which is formed and has an impurity concentration higher than that of the second semiconductor layer;
A semiconductor substrate having a first well region and a second well region of the second conductivity type formed apart from the first well region on the surface of the semiconductor layer, and the semiconductor element forming the output stage of the booster circuit is Second
Surface of the second well region formed in the well region of
The diffusion region of the second conductivity type formed in the
The second well region as a base region,
The well region of the
Diode-connected diode that is electrically connected to the
At least a part of the plurality of second-conductivity-type MOS transistors forming the peripheral circuit , which are bipolar transistors, are formed in the third well region, and the plurality of first-conductivity forming the peripheral circuits are provided. Type MOS transistor, at least a part of the MOS transistor is formed in the fourth well region. 6. A second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer is epitaxially grown on the surface of the first semiconductor layer of the first conductivity type. A step of forming on the surface of the first semiconductor layer, and a step of ion-implanting an impurity of the second conductivity type so that a peak of the impurity concentration is located at a position of a predetermined depth from the surface of the second semiconductor layer. Forming a second well of the second conductivity type on the surface of the second semiconductor layer with the second semiconductor layer interposed between the surface of the first semiconductor layer and the surface of the first semiconductor layer; Forming a second well region of the first conductivity type on the surface of the first well region above the peak position of the impurity concentration at a predetermined position in the first well region; and on the surface of the second semiconductor layer. The impurity concentration of the second semiconductor layer is higher than that of the second semiconductor layer. Forming a third well region of a first conductivity type having a pure substance concentration, and separating a fourth well region of a second conductivity type on the surface of the second semiconductor layer from the first well region. Forming step, forming a first semiconductor element in the second well region, forming a second semiconductor element in the third well region, and forming a third semiconductor element in the fourth well region A method of manufacturing a semiconductor integrated circuit device, the method including the step of forming. 7. A step of forming an epi layer by epitaxial growth on the surface of a first semiconductor layer of the first conductivity type, wherein an impurity concentration peak is located at a predetermined depth from the surface of the epi layer. Ions are implanted with an impurity of the first conductivity type to form a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer on the surface of the first semiconductor layer. A step of forming a second well of the second conductivity type on the surface of the second semiconductor layer with the peak position of the second semiconductor layer interposed between the surface of the second semiconductor layer and the surface of the first semiconductor layer. A step of forming a second well region of the first conductivity type on the surface of the first well region, and an impurity concentration higher than that of the second semiconductor layer on the surface of the second semiconductor layer. Form a third well region of the first conductivity type A step of forming a fourth well region of the second conductivity type on the surface of the second semiconductor layer separately from the first well region, and forming a first semiconductor element on the second well region. A step of forming a second semiconductor element in the third well region, and a step of forming a third semiconductor element in the fourth well region. 8. A step of forming an epitaxial layer on the surface of a first semiconductor layer of the first conductivity type by epitaxial growth, so that the peak of the impurity concentration is located at a predetermined depth from the surface of the epitaxial layer. Ions are implanted with an impurity of the first conductivity type to form a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer on the surface of the first semiconductor layer. A step of ion-implanting a second conductivity type impurity so that an impurity concentration peak is located at a predetermined depth from the surface of the second semiconductor layer, A step of forming a first well region of the second conductivity type with the peak position of the second semiconductor layer interposed between the first well region and the surface of the first semiconductor layer; The position of the first well region is not A step of forming a second well region of the first conductivity type above a peak position of the pure substance concentration; a first impurity layer having a higher impurity concentration than that of the second semiconductor layer on the surface of the second semiconductor layer; Forming a conductive type third well region, and forming a second conductive type fourth well region on the surface of the second semiconductor layer separately from the first well region,
Forming a first semiconductor element in the second well region, forming a second semiconductor element in the third well region, forming a third semiconductor element in the fourth well region A method of manufacturing a semiconductor integrated circuit device comprising: