JP3256122B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a MOS type mask ROM capable of obtaining multiple output levels.

[0002]

2. Description of the Related Art Conventionally, as a method of changing a threshold voltage of a transistor, a method of changing a thickness of a gate insulating film and a method of changing an impurity concentration of a channel region are known. In general, writing to a mask ROM is performed by implanting impurity ions into a channel region (hereinafter, referred to as “writing implantation”).

In the above-described conventional mask ROM writing method, a binary output level is produced by changing the impurity concentration of the channel depending on whether or not write injection is performed once for a desired transistor. . Further, in the case of a mask ROM having a ternary output level, two implantations with different implantation amounts of impurities are required. Therefore, ROM
In order to realize a ternary output level in order to increase the capacity of the device and reduce the chip area, at least one or more impurity ion implantation steps and / or gates are performed on a desired transistor according to the output level. The number of steps for changing the thickness of the oxide film must be increased, and a photomask for ion implantation is also required, resulting in a long delivery time and high cost.

[0004] For example, IEEE VOL. SC, 19. NO.2 APRIL 1
984, “A FOUR-State ROM Using Multilevel Process Te
The first transistor (threshold voltage: 0 to 0.5 V) using three ROM data write masks for "chnology"
Does not perform ROM data write injection, the second transistor (threshold voltage 0.5 to 1.0 V) implants boron + phosphorus ions, and the third transistor (threshold voltage 1.5
A method of writing quaternary values by implanting boron ions into the fourth transistor (with a threshold voltage of 15 V or more) by forming a gate oxide film by field oxidation has been disclosed.

In this method, ROM data writing is also used as a mask in another process, so that the number of masking processes is not substantially increased. However, data writing in the ROM is performed at the first stage of field oxide film formation. Therefore, there is a very problem in shortening the delivery time of the ROM. Also,
Another method for obtaining a multi-value output is disclosed in Japanese Unexamined Patent Publication No. 59-1483.
No. 60 and Japanese Unexamined Patent Publication (Kokai) No. 61-263263 disclose a method of manufacturing a semiconductor device in which impurity ions are selectively implanted into channel regions of a plurality of transistors constituting a memory cell to make the effective channel width different. ing.
However, these methods have an advantage that multi-level writing can be performed by one ROM writing implantation, but since the resist serving as a mask for ion implantation needs to be patterned in accordance with the channel width, the capacity is increased. In addition, reduction in chip area cannot be realized. That is, for example, when obtaining a ternary output level, the channel width Wf needs to be about three times that of the minimum impurity ion implanted region even if it is formed with the minimum resolution. Therefore, even if 2-bit multi-valued information is stored in the memory cell, it is actually impossible to increase the capacity and the chip area as a result.

[0006]

According to the present invention, there is provided (i) a MOS having a gate oxide film and a gate electrode on a semiconductor substrate and a source / drain region inside the surface of the semiconductor substrate.
A plurality of memory cells consisting of
i) changing the impurity concentration of a channel region of a desired transistor among the transistors to form a transistor having a high threshold voltage; and (iii) forming a desired transistor among the transistors having a high threshold voltage. A multi-level output level mask RO formed by applying a hot carrier stress to form a transistor having a higher threshold voltage.
A method for manufacturing a semiconductor device having M is provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, first, a process
In (i), a plurality of memory cells including a MOS transistor having a gate oxide film and a gate electrode on a semiconductor substrate and a source / drain region inside the surface of the semiconductor substrate are formed. The semiconductor substrate is not particularly limited, but is preferably a silicon substrate. It is preferable that the semiconductor substrate be doped with an impurity for adjusting a threshold voltage as appropriate before forming a transistor or the like. The gate oxide film, the gate electrode, and the source / drain regions constituting the transistor can be formed by known methods. As these transistors, for example, a flat cell in which a gate electrode and a source / drain region are formed in parallel or perpendicular to each other, or a NOR type X cell or the like (see FIG. Writing is performed by controlling the threshold voltage of a transistor such as a memory cell M including an electrode 34 and a source / drain region 32, a bit line 31, and a contact portion 33 connected to the bit line 31). It includes all the transistors that make up the ROM.

Next, in step (ii), a transistor having a high threshold voltage is formed by changing the impurity concentration of a channel region of a desired transistor among the obtained transistors. Specifically, a transistor having a high threshold voltage is formed by forming a resist pattern having an opening over a desired transistor by a photolithography process and performing ion implantation using the resist pattern as a mask. The ion implantation at this time uses impurity ions of the same conductivity type as that of the semiconductor substrate,
Energy is injected into the channel region through the gate electrode and the gate oxide film of the transistor in a region where the resist pattern does not exist and where the resist pattern does not exist, and at a dose sufficient to obtain a desired threshold voltage. Is preferred. The energy and dose vary depending on the thickness of the resist pattern to be formed, the threshold value of the transistor to be obtained, and the like. However, when B ⁺ ions are used, about 120 to 200 keV, 3.5 to 5.5 × 1
About 0 ¹³ cm ^-2 is mentioned. If the dose amount of the ion implantation is too large, the deterioration is remarkable with respect to the application of hot carrier stress performed in a later step, so that the reliability of the transistor is ensured at the voltage applied to the drain region during normal operation. It needs to be considered. By performing the step of implanting ions into the channel region of the transistor in this manner, a threshold voltage can be set higher than that of a transistor not implanting ions into the channel region by, for example, about 2.5 to 3.5 V. .

The ion implantation step can be performed two or more times by changing the dose. Thus, three or more kinds of transistors having different threshold voltages can be obtained. Further, in step (iii),
Of the high threshold voltage transistors obtained in the step (ii), a desired transistor is subjected to hot carrier stress to form a transistor having a higher threshold voltage. Through such steps, as described above, a semiconductor device having a mask ROM with a multi-level output level can be manufactured.

As a specific method of applying the hot carrier stress, there is a method of applying a desired voltage to a drain region and a gate electrode of a transistor to be written. As described above, by applying the hot carrier stress, hot carriers can be injected into the gate electrode, and the hot carriers can be trapped in the gate insulating film. Therefore, the threshold voltage can be further increased without forming a floating gate. Transistors with different voltages can be manufactured.

At this time, the voltage applied to the drain region is
It is preferable that the on-state breakdown voltage be equal to or lower than the on-state breakdown voltage of the transistor before the application of stress. In addition, the voltage applied to the gate electrode is preferably such that the probability of hot carriers being trapped is increased by selecting a voltage at which the substrate current is maximized at a predetermined drain voltage, so that the shift of the threshold voltage becomes faster, which is preferable. . Specifically, the voltage applied to the drain region is preferably about 4.0 to 5.0 V, and the voltage applied to the gate electrode is preferably about 9.0 to 10.0 V. Further, at this time, the transistors that do not perform writing include:
It is necessary to apply the same voltage to both the source / drain regions so as not to apply stress. For example, both the source / drain regions include GND or Vd.

The voltage applied to the drain region and the gate electrode can be increased in the application time so that the threshold voltage can be increased. Therefore, the application time is appropriately adjusted according to the desired threshold voltage. can do. For example, when a voltage is applied at room temperature, it is preferably from several seconds to about 100 seconds. In the above-described hot carrier stress application, the shift amount of the threshold voltage during a predetermined application time increases as the amount of impurity ions implanted into the channel region increases. Also, the threshold voltage cannot be shifted efficiently. Therefore, in the step (ii), when two or more transistors having different threshold voltages are manufactured by performing write injection twice or more (that is, there are three or more transistors having different threshold voltages). If) those transistors have
By applying the same stress application time and the same stress application voltage, transistors having two or more different threshold voltages (that is, quaternary or quinary output) can be manufactured. In addition, by applying the hot carrier stress twice or more at different times and with different applied voltages or the like, a transistor having a further different threshold voltage can be manufactured.

The above-mentioned hot carrier stress is:
When the semiconductor substrate temperature is applied at a low temperature of 0 ° C. or less, the stress application time can be reduced. Furthermore, even when the hot carrier stress is applied while applying a bias voltage to the substrate, the time for applying the stress can be shortened. In this case, the bias voltage is preferably equal to or less than the junction withstand voltage of the drain region (for example, when a stress voltage of 4 V is applied to the drain region, the junction withstand voltage of the drain region of the flat cell transistor is about 7 V). About 0.5 to -2.0 V is preferable.

In the present invention, by performing the above steps, for example, by combining one write injection necessary for obtaining a binary output level and one hot carrier stress application, a ternary output A level mask ROM can be realized. In such a way,
The delivery time can be shortened as compared with the case where two writing injections are performed to obtain a ternary output level, and the number of writing injection masks can be reduced by one, so that the storage capacity per memory cell size can be increased at low cost ( Ternary output). Therefore, a large capacity and a small chip area can be realized.

In order to realize a quaternary output level, three write injections were conventionally required, but according to the above method, two write injections and one hot carrier stress are required. In order to realize a quinary output level, a combination of application or one write injection and two hot carrier stress applications, two write injections, two hot carrier stress applications, and two write operations Injection and one-time application of hot carrier stress to transistors having two different threshold voltages, one-time injection and application of three hot-carrier stresses, or three-time injection and application of one-time hot carrier stress And can be combined. Hereinafter, a specific example of a method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.

Embodiment 1 First, as shown in FIG. 1A, a P-type semiconductor substrate 1 is formed.
A gate oxide film 3 of about 180 ° is formed thereon, and a plurality of gate electrodes 4 facing the channel are formed on the gate oxide film 3 in parallel with each other. Further, a plurality of N-type source / drain regions 2 are formed inside the surface of the semiconductor substrate 1 and include a first transistor to a third transistor (T1 to T3) each having the same channel length and channel width. Is formed.

Next, as shown in FIG. 1B, a first information writing resist pattern 5 is formed on the gate oxide film 3 and the gate electrode 4 by photolithography. Subsequently, using this resist pattern 5 as a mask,
For example, ROM data writing is performed by implanting impurity ions into the channel regions 7 and 8 of the second transistor (T2) and the third transistor (T3). At this time, for example, B ⁺
The treatment is performed at a dose of about keV and about 3.5 to 5.5 × 10 ¹³ cm ⁻² . As a result, a memory cell transistor in which ROM writing is not performed and a transistor having a threshold voltage Vth of 3.0 to 3.7 V are formed.

After forming the binary output memory cell as described above, as shown in FIG. 1C, for example, Vd = 4.0 is applied to the drain region 2a of the third transistor (T3).
V, a stress of Vg = 9.0 V is applied to the gate electrode 4a for about 5
Add for 0 seconds. Thus, a transistor having a threshold voltage Vth of 6 V or more is formed at T3. In this manner, the ternary output transistors T1, T2,
T3 can be formed. Therefore, resist coating, exposure, development, inspection,
ROM writing ion implantation and resist removal
By performing the process twice, the step of forming a mask can be omitted as compared with the case of forming a transistor of three-value output, and the processing time can be reduced and the manufacturing cost can be reduced.

After forming a binary output memory cell by the same method as described above, stress was applied for hot carrier injection at various times. The result is shown in FIG. As is clear from FIG. 2, the threshold voltage increases as the time of applying the hot carrier stress increases.

Embodiment 2 A semiconductor device was manufactured in the same manner as in Embodiment 1, except that a hot carrier stress was applied at a low temperature of 0 ° C. or less after forming a binary output memory cell. FIG. 3 shows various channel lengths (○ = 0.8 μm, ● = 1.0 μm, Δ =
4 shows the relationship between the stress application temperature and the lifetime of a transistor having a thickness of 1.4 μm). The life in this case is
The time when the triode Beta is lowered by about 10% is shown.
When the temperature at the time of applying the stress is changed from room temperature to about −50 ° C., the lifetime of the transistor is about 1/100. From this, it can be considered that the time during which the threshold voltage shifts high is also about 1/100, and therefore, the hot carrier stress application time can be reduced to about 1/100.

Embodiment 3 Terminals connected to a substrate are formed in advance and hot
When applying a bias to the substrate when applying carrier stress,
Outside, a semiconductor device was manufactured in the same manner as in the first embodiment. Figure
Reference numeral 4 denotes a track in which writing and injection of ROM data were not performed.
Transistor (●), 1.7 × 10¹³cm^-2With writing injection
Transistor (▲), 3.5 × 10 ¹³cm^-2so
Write-injected transistor (■)
In the case where the substrate bias Vsub is variously changed,
The change of the threshold voltage Vth is shown. According to this,
The bias voltage applied to the substrate when applying carrier stress.
The larger the threshold, the higher the threshold voltage during aging
Indicates that

For example, in the case of a transistor having a threshold voltage of 3 to 3.7 V, when a substrate bias of about 0.5 to 1 V is applied and a hot carrier stress is applied, the threshold voltage at the time of aging is reduced. It becomes about 4-4.7V. That is, this indicates that the lifetime is reduced to about 1/100, and therefore, the hot carrier stress application time can be reduced to 1/100.

Embodiment 4 First, as shown in FIG. 5A, a P-type semiconductor substrate 1 is formed.
A plurality of N-type source / drain regions 12 are formed at equal intervals on one. Then, about 1
Forming a gate oxide film 13 of 80 °;
A plurality of gate electrodes 14 which are perpendicular to the source / drain regions 12 are formed in parallel with each other. Thereby, on the matrix of the plurality of source / drain regions 12 and the gate electrode 14, the first to third transistors (T
1 to T3) are formed (see FIG. 6).

Next, as shown in FIG. 5B, a first information writing resist pattern 15 is formed on the gate oxide film 13 and the gate electrode 14 by photolithography. Subsequently, using this resist pattern 15 as a mask, for example, ROM data writing is performed by implanting impurity ions into the channel regions 17 and 18 of the second transistor (T2) and the third transistor (T3). At this time, for example, B ⁺ ions are
About ^{0~200keV, 3.5~5.5 × 10 1 3 cm} -2
Perform at a moderate dose. As a result, a memory cell transistor in which ROM writing is not performed and a transistor having a threshold voltage Vth of 3.0 to 3.7 V are formed.

After forming the binary output memory cell as described above, as shown in FIG. 5C, for example, Vd = 4.V in the drain region 12a of the third transistor (T3).
A stress of 0 V and Vg = 9.0 V is applied to the gate electrode 14 at room temperature for several tens of seconds. Thus, a transistor having a threshold voltage Vth of 6 V or more is formed at T3. At this time, it is necessary to equalize the voltage applied to the source / drain regions 12 so that no stress is applied to the transistors in which writing is not performed (both the source / drain regions 12 are GND or the source / drain regions 12). The drain region 12 is both Vd).

As shown in FIG. 7, the hot carrier is injected into the stress applying device by the write address buffer A.
And input the write bit line and the word line. Then, one bit line is turned on, the word line selected for the bit line is read from the address buffer A, and the word lines are collectively applied with hot carrier stress. Repeat this for all bit lines. For example, in the case of a 16M mask ROM, there are 256 bit lines per block, and 8 blocks of memory cells (M
21 to M28) If applied simultaneously, writing can be performed with a maximum of 256 stress applications. Assuming that one stress application time is about 50 seconds, it takes about 4 hours for one chip. However, in order to form a transistor having a ternary output by batch processing a plurality of chips, resist coating,
Mass production becomes possible in a shorter time than performing the steps of exposure, development, inspection, ROM writing ion implantation, and resist removal. Further, since the number of photo steps is reduced by one, masks for performing photo can be reduced.

[0027]

According to the present invention, a semiconductor device having three or more output levels can be manufactured by combining write injection and hot carrier stress application. That is, for example, a semiconductor device having three output levels is formed by one writing injection and one hot carrier stress application, and a ROM writing mask necessary for forming a ternary output level has one mask. Since the number of sheets can be reduced and the steps of photo, development, inspection, ROM writing ion implantation, and resist removal are replaced by hot carrier threshold application, a short delivery time and low cost can be realized. Also, in order to realize an output level of four or more values, it is possible to combine one or more writing injections and one or more hot carrier stress applications.

Further, in the present invention, when a hot carrier stress is applied in a low temperature state where the semiconductor substrate temperature is 0 ° C. or less, or when a bias voltage is applied to the substrate while applying a bias voltage, the stress application time is shortened. By shortening the application time, it is possible to further prevent erroneous writing in the ratio-selected memory cell, that is, a memory cell to which writing is not desired due to stress application, thereby improving the reliability of the semiconductor device itself. Becomes

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a graph showing a relationship between a hot carrier stress application time and a threshold voltage in the present invention.

FIG. 3 is a graph showing a relationship between a substrate temperature at the time of hot carrier stress and a lifetime of a transistor in the present invention.

FIG. 4 is a graph showing a relationship between a substrate bias voltage and a threshold voltage during hot carrier stress in the present invention.

FIG. 5 is a manufacturing process diagram showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a plan view of the semiconductor device shown in FIG. 5;

FIG. 7 is a schematic view for explaining a method of applying a hot carrier stress in the present invention.

FIG. 8 is a schematic plan view for explaining an example of a memory cell in which ROM can be written in the semiconductor manufacturing method of the present invention.

[Explanation of symbols]

1, 11 Semiconductor substrate 2, 12, 32 Source / drain region 2a, 12a Hot carrier stress Vd applied source / drain region 3, 13 Gate oxide film 4, 14, 34 Gate electrode 4a, 14a Hot carrier stress Vg applied gate electrode 5 , 15 resist pattern 6, 7, 8, 16, 17, 18 channel region 31 bit line 33 contact portion M memory cell M21 to M28 memory cell block A write address buffer B word line stress application C bit line stress application

Claims (4)

(57) [Claims] (I) forming a plurality of memory cells comprising a MOS transistor having a gate oxide film and a gate electrode on a semiconductor substrate and a source / drain region inside the surface of the semiconductor substrate; Changing the impurity concentration of the channel region of a desired transistor to form a transistor having a high threshold voltage, (iii)
A method of manufacturing a semiconductor device having a mask ROM with a multi-level output level, comprising applying a hot carrier stress to a desired transistor among the high threshold voltage transistors to form a transistor having a higher threshold voltage. 2. The method according to claim 1, wherein the hot carrier stress is applied by applying a desired voltage to the drain region and the gate electrode. 3. The method according to claim 1, wherein the hot carrier stress is applied at a low temperature of 0 ° C. or lower. 4. The method according to claim 1, wherein the hot carrier stress is applied while applying a bias voltage to the substrate.