KR20120069111A - Method of testing a semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for testing a semiconductor memory device is provided to improve the reliability of a test by changing a condition of the test according to the properties of memory cells with data. CONSTITUTION: Data is saved in even memory cells included in an even page. Data is saved in odd memory cells included in an odd page. A thermal process is performed after an even program operation and an odd program operation are performed. A first read voltage(Vrde) is applied to the even memory cells for checking whether the data saved in the even memory cells is changed. A second read voltage(Vrdo) is applied to the odd memory cells for checking whether the data saved in the odd memory cells is changed.

Description

Method of testing a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a semiconductor memory device, and more particularly, to a test method for a semiconductor memory device for measuring reliability related to data storage capability.

After the semiconductor memory device is manufactured, a test operation for checking whether the semiconductor memory device operates normally is performed. This test operation also includes a reliability test that measures the data retention ability to maintain stored data. In the case of a nonvolatile memory device, data must be preserved without being deleted even when the power supply is interrupted, and typically data must be stored for 5 to 10 years. However, you can't wait a few years for these reliability tests after you save your data. To this end, reliability tests are conducted by applying stress to a memory device that stores data within a short time to be stressed for 5 to 10 years. Hot temperature data retention (HTDR) is a method of baking a memory device at a high temperature to apply a significant stress in a short time.

If the reliability test is performed under the same conditions without considering the characteristics of the memory cells storing the data in the process of testing the memory device by the above method, the defective rate due to the error increases.

The embodiment of the present invention can change the condition of the reliability test according to the characteristics of the memory cells in which data is stored, thereby reducing the defective rate due to an error and improving the reliability of the test.

A test method of a semiconductor memory device according to an embodiment of the present invention includes performing an even program operation for storing data in even memory cells included in an even page of a selected memory block, and an odd page of the selected memory block. Performing an odd program operation for storing data in the odd memory cells, performing an thermal process to stress using heat after the even program operation and the odd program operation are performed, and Performing a first read operation by applying a first read voltage to the even memory cells to confirm whether the stored data has changed, and performing a second read to the odd memory cells to confirm whether the data stored in the odd memory cells has changed. Applying a voltage to perform a second read operation. And also, the first read voltage is higher than the second read voltage is applied to a lower level than a voltage obtained by adding the threshold voltage rise of Ibn memory cells due to the interference phenomenon that occurs when odd programming operation to the second read voltage.

A test method of a semiconductor memory device according to another embodiment of the present invention includes performing an odd program operation for storing data in odd memory cells included in an odd page of a selected memory block, and including the even page in a selected memory block. Performing an even program operation for storing data in the even memory cells, performing an thermal process to stress using heat after the odd program operation and the even program operation are performed, and the even memory cells Performing a first read operation by applying a first read voltage to the even memory cells to confirm whether the data stored in the second memory cell is changed, and performing a first read operation on the second memory cells to confirm whether the data stored in the odd memory cells has changed. Applying a read voltage to perform a second read operation And comprising a second read voltage is higher than the first read voltage, Ibn program is applied to a lower level than a voltage obtained by adding the threshold voltage rise of the odd memory cell in a first read voltage by interference generated in operation.

Data stored in even memory cells and data stored in odd memory cells may be the same.

The threshold voltage rise can be determined in a range greater than 0V and less than 1V.

The second read operation may be performed before the first read operation.

The embodiment of the present invention can change the condition of the reliability test according to the characteristics of the memory cells in which data is stored, thereby reducing the defective rate due to an error and improving the reliability of the test.

1 is a circuit diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.
3A to 3B are views for explaining a test method according to an embodiment of the present invention.
4A and 4B are diagrams for describing a test method according to another exemplary embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a circuit diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.

Referring to FIG. 1, a semiconductor memory device is configured to perform a program operation, a read operation, or an erase operation of a memory array 110 including a plurality of memory blocks 110MB, and memory cells included in the memory block 110MB. Control circuit group 120, 140, 150, 160, 170, control circuit group 120, 140, 150, 160, 170. In the case of the NAND flash memory device, the operation circuit group includes the voltage supply circuits 130 and 140, the page buffer group 150, the column selection circuit 160, and the input / output circuit 170.

The memory blocks 110MB of the memory array 110 include a plurality of memory cells and will be described in detail as follows.

Referring to FIG. 2, each memory block 110MB includes a plurality of strings ST0,..., STk connected between the bit lines BL1 to BLk and the common source line CSL. That is, the strings ST1,..., And STk are respectively connected to the corresponding bit lines BL1,..., And BLk and commonly connected to the common source line CSL. Each string ST1 includes a source select transistor SST having a source connected to the common source line CSL, a plurality of memory cells Ca0,..., Can, and a drain connected to the bit line BL1. It consists of a drain select transistor DST. The gate of the source select transistor SST is connected to the source select line SSL, the gates of the memory cells Ca0, ..., Can are connected to the word lines WL0, ..., WLn, respectively. The gate of the drain select transistor DST is connected to the drain select line DSL.

In the NAND flash memory device, memory cells included in a memory cell block may be divided into physical page units or logical page units. Pages (or even pages and odd pages) become basic units of a program operation or a read operation.

For example, memory cells Ca0,..., Ck0 connected to one word line (eg, WL0) constitute one physical page PAGE0. Further, even-numbered memory cells Ca0, Cc0, ..., Ck-10 connected to one word line (eg, WL0) constitute one even physical page, and odd-numbered memory cells Cb0, Cd0,. .., Ck0) may constitute a single physical page.

Referring back to FIG. 1, the control circuit 120 outputs an internal command signal CMDi for a program operation, a read operation, or an erase operation in response to a command signal CMD input from an external source, and controls the type of operation. Accordingly, control signals PS SIGNALS for controlling the page buffers included in the page buffer group 150 are output. In addition, the control circuit 120 outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD.

The voltage supply circuits 130 and 140 select the operating voltages Vpgm, Vpv, Vread, and Vpass necessary for the program operation or the read operation of the memory cells in response to the internal command signal CMDi of the control circuit 120. The drain select line DSL, the word lines WL0,..., WLn and the source select line SSL of the block are supplied. This voltage supply circuit includes a voltage generator circuit 130 and a row decoder 140.

The voltage generation circuit 130 outputs operating voltages for program operation or read operation of the memory cells as global lines in response to the internal command signal CMDi of the control circuit 120. When performing a program operation or a read operation, a program voltage Vpgm, a program verify voltage Vpv, or a read voltage Vread for applying to selected memory cells is output, and a pass voltage Vpass for applying to unselected memory cells. ) As global lines.

In response to the row address signals RADD of the control circuit 120, the row decoder 140 may select operating voltages generated by the voltage generation circuit 130 to select one of the memory cell blocks of the memory cell array 110. Transfers to the local lines DSL, WL0 to WLn, SSL of block 110MB.

The page buffer group 150 includes a plurality of page buffers (not shown). The page buffers may be connected to the bit lines BL1 to BLk, and may be connected to each pair of bit lines including the even bit line and the odd bit line. Each page buffer stores the data in the cells Ca0, ..., Ck0 or reads the data from the cells according to the control signals PB SIGNALS of the control circuit 120. Adjust the voltage of BLk).

The column selection circuit 160 selects the page buffers included in the page buffer group 150 in response to the column address signal CADD output from the control circuit 120. Data for storing in the memory cell is input to the page buffer selected by the column selection circuit 160, or data sensed from the memory cell is output from the selected page buffer.

The input / output circuit 170 transfers data to the column selection circuit 160 under the control of the control circuit 120 to input data input from the outside into the page buffer group 150 for storage in memory cells during a program operation. do. The column selection circuit 160 sequentially transfers the transferred data to the page buffers of the page buffer group 150, and the page buffers store the input data in an internal latch. In addition, during the read operation, the input / output circuit 170 outputs data transferred through the column select circuit 160 from the page buffers of the page buffer group 150 to the outside.

After the semiconductor memory device including the above components is manufactured, a test operation for checking whether the semiconductor memory device operates normally is performed. In particular, a reliability test is performed that measures the data retention capacity of storing data in memory cells and then retaining the stored data. Referring to the process of performing the reliability test as follows.

3A to 3B are views for explaining a test method according to an embodiment of the present invention.

1, 2, and 3A, after a semiconductor memory device including the memory array 110, the operation circuit groups 130, 140, 150, 160, and 170 and the control circuit 120 is manufactured, a test is performed. For operation, test data is stored in memory cells included in a selected page (eg, PAGE0) of the memory block 110MB. In this case, a program operation for storing test data in the memory cells Ca0 to Ck0 may include an even program operation for storing test data in the memory cells Ca0, Cc0, and Ck-1 of the even page and a memory of the odd page. The operation is divided into an odd program operation for storing test data in the cells Cb0, Cd0, and Ck.

Meanwhile, when two bits of data are respectively stored in the memory cells, threshold voltage distributions of the memory cells are divided into four levels. The test scheme described below can be equally applied at each threshold voltage level. That is, the same may be applied regardless of data stored in the memory cells.

In order to store the test data in the memory cells, an even program operation for storing the test data in the even pages memory cells Ca0, Cc0, and Ck-1 is first performed. Accordingly, the threshold voltage distribution 310e of the even memory cells Ca0, Cc0, and Ck-1 is higher than the threshold voltage distribution 310o of the odd memory cells Cb0, Cd0, and Ck.

1, 2, and 3B, after an even program operation is completed, an odd program operation is performed to store test data in memory cells Cb0, Cd0, and Ck of an odd page. Accordingly, the threshold voltage distribution 310o of the odd memory cells Cb0, Cd0, and Ck also increases. In this case, the same data as the data stored in the even memory cells Ca0, Cc0, and Ck-1 may be stored in the odd memory cells Cb0, Cd0, and Ck.

At this time, since the odd program operation is performed after the data is stored in the even memory cells Ca0, Cc0, and Ck-1 by the even program operation, the even memory cells Ca0, Cc0, and Ck-1 in the odd program operation are performed. ), An interference phenomenon occurs, and the threshold voltage distribution 310e of the even memory cells Co ˜Cn increases.

1, 2 and 3C, the semiconductor memory device is baked at high temperature such that significant stress is applied to the semiconductor memory device in a short time to test the data retention characteristics. As a result, electrons injected into the floating gate of the memory cells are emitted to the outside by a program operation, and threshold voltages of the memory cells are lowered. Even after the threshold voltages are lowered, the threshold voltages of the even memory cells Ca0, Cc0, and Ck-1 remain higher than the threshold voltages of the odd memory cells Cb0, Cd0, and Ck.

Thereafter, an operation (eg, a read operation) of detecting threshold voltage levels of the memory cells is performed to detect whether data stored in the memory cells has changed. The read operation is divided into an even read operation for detecting threshold voltages of the even memory cells Ca0, Cc0, and Ck-1 and an odd read operation for detecting threshold voltages of the odd memory cells Cb0, Cd0, and Ck. In the even read operation and the odd read operation, a read voltage Vrd is applied to the memory cells to sense whether threshold voltages of the memory cells are higher or lower than the read voltage Vrd.

Even and odd memory cells Ca0 to Ck0 when threshold voltage distribution 310e of even memory cells Ca0, Cc0, and Ck-1 is higher than threshold voltage distribution 310o of odd memory cells Cb0, Cd0, and Ck. ) And the read operation may be performed by applying the same read voltage Vrd to. That is, the threshold voltages of the even memory cells Ca0, Cc0, and Ck-1 may be higher than the read voltage Vrd, so that stored data may be maintained. However, a memory cell having a threshold voltage lower than the read voltage Vrd among the odd memory cells Cb0, Cd0, and Ck may be detected. In such a case, even if the data retention characteristic satisfies the minimum condition, it may be determined that it is not.

Accordingly, the condition of the test operation is considered in consideration that the threshold voltage distribution 310e of the odd memory cells Cb0, Cd0, and Ck is lower than the threshold voltage distribution 310e of the even memory cells Ca0, Cc0, and Ck-1. It is desirable to set differently. This will be described in detail as follows.

4A and 4B are diagrams for describing a test method according to another exemplary embodiment of the present invention.

1, 2 and 4A, when the baking process of the semiconductor memory device is performed at a high temperature such that significant stress is applied to the semiconductor memory device in a short time to test the data retention characteristic, the threshold voltages of the memory cells are lowered.

Thereafter, an even read operation of detecting threshold voltage levels of the even memory cells Ca0, Cc0, and Ck-1 is performed to detect whether data stored in the even memory cells Ca0, Cc0, and Ck-1 has changed. In the even read operation, the first read voltage Vrde is applied to the even memory cells Ca0, Cc0, and Ck-1. When the threshold voltages of the even memory cells Ca0, Cc0, and Ck-1 are sensed to be higher than the first read voltage Vrde, the data stored in the even memory cells Ca0, Cc0, and Ck-1 remain unchanged. I think it is.

Referring to FIGS. 1, 2 and 4B, an odd node detecting threshold voltage levels of the odd memory cells Cb0, Cd0, and Ck to detect whether data stored in the odd memory cells Cb0, Cd0, and Ck has been changed. Read operation is performed. Since the threshold voltage distribution 310o of the odd memory cells Cb0, Cd0, and Ck is relatively lower than the threshold voltage distribution 310e of the even memory cells Ca0, Cc0, and Ck-1, an even read operation is performed in the odd read operation. The second read voltage Vrdo at a level lower than the first read voltage Vrde applied to the even memory cells Ca0, Cc0, and Ck-1 is applied to the odd memory cells Cb0, Cd0, and Ck. When the threshold voltages of the odd memory cells Cb0, Cd0, and Ck are sensed to be higher than the second read voltage Vrdo, it is determined that the data stored in the odd memory cells Cb0, Cd0, and Ck remain unchanged. .

Meanwhile, as described above, the first read voltage Vrde applied in the read operation of the even memory cells Ca0, Cc0, and Ck-1 and the read operation of the odd memory cells Cb0, Cd0, and Ck are applied. The second read voltage Vrdo is applied at different levels. In this case, the first read voltage Vrde is higher than the second read voltage Vrdo, and the threshold voltage rise width ΔV of the even memory cells Ca0, Cc0, and Ck-1 due to the interference phenomenon is determined as the second read voltage (Vrde). It is preferable to apply at a level lower than the voltage (Vrdo + DELTA V) plus Vrdo. At this time, the threshold voltage rising width ΔV may be measured by another test. As another example, the threshold voltage rise may be determined in a range greater than 0V and less than 1V without measuring by a test.

Although the even read operation is performed before the odd read operation, the odd read operation may be performed before the even read operation.

In addition, the odd program operation may be performed first and the even program operation may be performed. In this case, since the threshold voltage distribution of the odd memory cells Cb0, Cd0, and Ck is increased due to an interference phenomenon generated during the even program operation, the second read voltage Vrdo is higher than the first read voltage Vrde and the interference It is preferable to apply the threshold voltage rising width ΔV of the odd memory cells Cb0, Cd0, and Ck due to the phenomenon to a level lower than the voltage Vrde + ΔV plus the first read voltage Vrde.

When two or more bits of data are stored in the memory cell, the threshold voltage distribution is 2 ⁿ (n is the number of bits of data stored in the memory cell). Even in this case, when the read operation is performed in each threshold voltage distribution, the even read operation and the odd read operation are performed under the above conditions.

110: memory array 110 MB: memory block
120: control circuit 130: voltage generating circuit
140: row decoder 150: page buffer group
160: column selection circuit 170: input and output circuit

Claims (5)

Performing an even program operation for storing data in even memory cells included in an even page of a selected memory block;
Performing an odd program operation for storing data in odd memory cells included in an odd page of the selected memory block;
Performing a thermal process to apply stress using heat after the even program operation and the odd program operation are performed;
Performing a first read operation by applying a first read voltage to the even memory cells to determine whether data stored in the even memory cells has changed; And
Performing a second read operation by applying a second read voltage to the odd memory cells to determine whether data stored in the odd memory cells has changed;
The first read voltage is higher than the second read voltage, and the semiconductor memory device is applied at a level lower than a voltage obtained by increasing the threshold voltage of even memory cells due to an interference phenomenon generated during the odd program operation to the second read voltage. Test method.
Performing an odd program operation for storing data in odd memory cells included in an odd page of a selected memory block;
Performing an even program operation for storing data in even memory cells included in an even page of the selected memory block;
Performing a thermal process to apply stress using heat after the odd program operation and the even program operation are performed;
Performing a first read operation by applying a first read voltage to the even memory cells to determine whether data stored in the even memory cells has changed; And
Performing a second read operation by applying a second read voltage to the odd memory cells to determine whether data stored in the odd memory cells has changed;
The second read voltage is higher than the first read voltage, and the semiconductor memory device is applied at a level lower than a voltage obtained by increasing the threshold voltage of the odd memory cells due to the interference generated during the even program operation to the first read voltage. Test method.
The method according to claim 1 or 2,
The method of claim 1, wherein the data stored in the even memory cells and the data stored in the odd memory cells are the same.
The method according to claim 1 or 2,
And the threshold voltage rise is greater than 0V and less than 1V.
The method according to claim 1 or 2,
And the second read operation is performed before the first read operation.

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