CN109346119A - A kind of semiconductor memory burn-in test core board - Google Patents
A kind of semiconductor memory burn-in test core board Download PDFInfo
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- CN109346119A CN109346119A CN201811006057.7A CN201811006057A CN109346119A CN 109346119 A CN109346119 A CN 109346119A CN 201811006057 A CN201811006057 A CN 201811006057A CN 109346119 A CN109346119 A CN 109346119A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
Abstract
The invention belongs to semiconductor memory degradation testing technique fields, disclose a kind of semiconductor memory burn-in test core board, test vector is generated in real time according to the parameter configuration of host computer, export various types of test signals, various resolution charts, and the processing that delay adjustment is carried out to test signal, reinforces driving, waveform control, and power supply signal is compensated, generate the power supply signal for more accurately testing signal；User is improved to the customized ability of test waveform and flexibility；Test core plate has the memory of subregion, the data subregion that real time contrast in test process is tested saves, control and failure analysis are carried out to failure DUT test process by the data of partitioned storage, realize the control and failure analysis in burn-in test to single DUT test process；The sufficiently long test information of each IO of every DUT is saved by the memory memory space that for example DRAM is provided, and so as to make DUT manufacturer for statistical analysis to each batch failure DUT, is improved yield, is promoted product reliability.
Description
Technical field
The invention belongs to semiconductor memory degradation testing technique fields, more particularly, to a kind of semiconductor memory
Burn-in test core board.
Background technique
Semiconductor memory has certain failure probability, and the relationship between failure probability and access times meets bathtub song
The characteristic of line, the failure probability of memory is high when beginning to use, when failure probability is greatly reduced after certain access times, directly
To after being close to or up to its service life, the failure probability of memory can increase again.So far dare to neglect without any memory manufacturer
The slightly Problem of Failure of semiconductor memory generally accelerates to store by burn-in test (Test During burn-in, TDBI)
The appearance of device failure probability directly allows it to enter product stationary phase to solve the problems, such as this.
The overall plan of semiconductor memory burn-in test is to supply power supply signal and test to tested semiconductor memory
Signal, allows time of tested semiconductor memory uninterruptedly operation setup under high/low temperature or room temperature, this process is known as
Aging (burn-in), thus carrys out the failure of accelerated semiconductor memory device, filters out non-defective unit.Burn-in test belongs to semiconductor core
The reliability test of piece, only need to do basic functional test can meet the requirements, and the working frequency of general chip can be reduced to
10MHz reduces testing cost to reduce the complexity of test macro.Since there are many type of semiconductor memory, it is widely used,
Amount is big, performance is higher and operating temperature range is wide, it is therefore desirable to have that a set of capacity is flexible, scalability is good, wide temperature range, function
It can enrich, the ageing testing method and system that framework reliability and cost performance are high are just able to satisfy practical application.Existing semiconductor
The technology of memory ageing testing method and device is more, for example:
The Chinese patent of Publication No. CN107305792A discloses a kind of method and apparatus for testing memory, is storing
Device has been internally integrated test circuit, only needs external equipment hair trigger command that can complete aging, but the technical solution of the disclosure
The burn in test circuit for not being related to high/low temperature aging testing apparatus, and integrating such as can only be written and read, wipe at the basic behaviour
Make, test result cannot be recorded and be analyzed, it can not positioning failure.
The Chinese patent of Publication No. CN102385933A discloses a kind of aging test device for memory, and disclosed deposits
Reservoir aging equipment includes an inner decoder and three concatenated counters, is surveyed for reducing testing cost and reduction aging
The time is tried, but the device is without reference to the management to test process and result, also without reference to high/low temperature burn-in test scheme.
The Chinese patent of Publication No. CN205680445U discloses a kind of static random access memory aged test plate
And device is not involved with specific testing scheme and system, test pair although being related to burn-in board and test device
Specific memory as being only limitted to specific company stores, i.e. IDT (Integrated Device Technology) company
SRAM (Static Random Access Memory) Static RAM, and without test board in clear ageing oven and survey
Specific connection and interaction between test-run a machine.
The Chinese patent of Publication No. CN102903395A discloses the method for testing reliability of memory, but relates generally to
The test of memory data holding capacity, without reference to memory burn-in test scheme.
The Chinese patent of Publication No. CN204269773U, CN105319494A disclose a kind of IC chip from
The driving template of IC chip burn-in test and the test template for putting chip are combined into one by dynamic ageing tester
Device is not needed using dedicated tester；But its function is simple, can only do basic aging, and cannot be in burn-in test
Data carry out record and administrative analysis, be unfavorable for chip yield promotion, be not suitable with the burn-in test of present semiconductor memories
Demand.
The Chinese patent of Publication No. CN204269774U, CN105319495A discloses a kind of in-building type ic core
Piece automatic aging test device, similar with the Chinese patent of Publication No. CN 204269773U, difference is test module collection
At memory inside has been arrived, without using dedicated tester, it is also not directed to the record and administrative analysis to test data.
The Chinese patent of Publication No. CN102467973A discloses a kind of method for testing memory and device, is referred to and deposits
Aging temperature is controlled using the heat that oneself power consumption generates when reservoir aging, to solve to lead to Temperature Distribution with external heating method
Uneven and temperature error, it is also mentioned memory is tested using controller and signal generator, mainly uses ranks square
Battle array control mode；But it is not directed to record and administrative analysis to test process, and this mode is not suitable for low temperature aging survey
Examination, there is certain limitation.
The Chinese patent of Publication No. CN107271879A discloses semiconductor chip ageing tester and method, is one
The method that kind reduces test clock signal transmission distortion, mainly moves on to the high frequency crystal oscillator for generating clock signal tested
Near chip carrier socket, and multiple clock sources can choose by multiplexer, chip is allowed to do durability aging at normal temperature
Test；It does not refer to high/low temperature burn-in test scheme, analysis is not managed to test process and result yet.
Summary of the invention
Extremely a little less in aiming at the above defects or improvement requirements of the prior art, the present invention provides a kind of semiconductors to deposit
Reservoir burn-in test core board, its object is to realize the test to tested device (Device Under Test, DUT)
Process control and failure analysis.
To achieve the above object, according to one aspect of the present invention, a kind of semiconductor memory burn-in test core is provided
Core, including
Central processing unit (CPU) receives external upper for realizing the communication between test core plate and external host computer
The test of machine instructs, and instructs other each functional units on control test core plate according to test, makes each functional unit according to upper
The test instruction that machine issues is tested, and the test result that functional unit each on test core plate returns is uploaded to host computer；
There is the power clock module of connection with central processing unit；For for test core plate provide working power and when
Clock is also used to provide power supply for DUT；
There is the test logic module of communication connection with central processing unit；Test vector is generated for instructing according to test,
It instructs according to central processing unit with specific timing and waveform output test signal；And for the test result of each DUT to be distinguished
Store the corresponding subregion of memory；And for carrying out preliminary failure analysis to test result, to assist host computer to be rapidly completed
The operation of test result；And after the analysis is complete transmit fail message to central processing unit, host computer is uploaded to by it；
Test logic module preferably uses Field Programmable Logic Array (FPGA)；
Preliminary failure analysis preferably includes: it collected data will be compared with preset data from DUT I/O pin,
Judge data whether mistake, and by the information preservations such as data, address of mistake to memory block；Judge whether data sampling window closes
Reason, and provide sampling location and adjustment direction；Judgement be applied to test time of signal on DUT IO, level whether with it is default
Unanimously, and measurement deviates and is supplied to host computer calibration；Classified to data, arranged, be packaged, canonical function interface side is provided
Just it calls；
There is the memory of communication connection with test logic module, there is subregion in the memory, it is slow to preferably include pin
Rush memory block, bad block memory block, data failure memory block and/or data buffering memory block；
There is the device power source power supply unit of connection with test logic module, device power source power supply unit has for connecting DUT
Interface, for give DUT provide working power；Preferably, device power source power supply unit receives the control that test logic module is sent
The voltage and current that information and power clock module provide, is adjusted received voltage and current in the case where controlling information function
It is output to the power pin of DUT afterwards；The voltage and current that device power source power supply unit is also used to acquire in DUT power pin is surveyed
Amount, sends the result to test logic module；Device power source power supply unit also has the function of power supply test, for the power supply to DUT
The voltage and current of pin.
There is the comparator of connection with test logic module, comparator has the input interface for receiving DUT signal, for adopting
Collect the voltage and current in DUT I/O pin and be compared with preset reference level, low and high level letter is exported according to comparison result
Number give test logic module；Judged whether by test logic module it is consistent with desired value, and will be inconsistent when DUT failure letter
Breath is all saved in memory, including but not limited to DUT number, fail address, fail data and/or failure voltage current value.
Preferably, above-mentioned semiconductor memory burn-in test core board further includes having connection with test logic module
Precision measurement unit, precision measurement unit has input interface for receiving DUT signal, for the input and output to DUT
Electric current is accurately tested, and is able to satisfy biggish voltage and current measurement range, maximum in a preferred embodiment to support
The current measuring capabilities of each DUT I/O pin 80mA.
Preferably, above-mentioned semiconductor memory burn-in test core board further includes having connection with test logic module
Pin driver circuit, pin driver circuit has interface for connecting DUT；The pin driver circuit is used for test logic
The test signal of module output increases driving and accurately time delay adjusts, and the test signal for being applied to DUT, which has, adequately to be adjusted
Whole nargin, to do various limit burn-in tests to DUT.
Preferably, above-mentioned semiconductor memory burn-in test core board, the number between test logic module and memory
According to transmission use DDR3/DDR4/DDR5 control interface, memory using dynamic random access memory (Dynamic RAM,
Data width uses 8bit/16bit when DRAM), using small outline dual memory modules (Small Outline Dual In-
Line Memory Module, SO-DIMM) when data width use 64bit/128bit, their interfaces clock frequency
In 800MHz or more, to guarantee the real-time of data processing.
Preferably, above-mentioned semiconductor memory burn-in test core board, test logic module include
Cyclelog, the test for receiving CPU transmission, which instructs and carries out decoding, is converted to executable data, and for survey
Examination timing and process are controlled；
Algorithm pattern generator, input terminal receives the output signal of cyclelog, for the parameter according to host computer
Configuration generates test vector in real time；Various resolution charts can be generated in real time, for example chessboard grid pattern, propulsion pattern, leapfrog pattern；
And for promoted the randomness of resolution chart it is preferably also built-in there are many random signal generator polynomials, and it is customized to preserve user
Resolution chart, it is also necessary to increase storage unit in high speed for example DRAM outside the test logic module of core board, it is old to be promoted
Change the coverage rate of test, the closest various application scenarios of energy most efficiently accelerate DUT failure probability, to promote the reliable of DUT
Property；
Waveshape monitor, and act on the clock generator of waveshape monitor；When clock generator is for generating test
Sequence；Waveshape monitor carries out waveform coding to test vector according to parameter setting and test sequence, forms final test letter
Number；
Input-output unit, the test signal for generating waveshape monitor are sent to DUT；And for receiving DUT's
Feedback signal；
Comparing function unit, the DUT feedback signal for sending input-output unit are compared with desired value, judgement
It is whether consistent with desired value, and will be inconsistent when the information of DUT be all saved in memory, including but not limited to DUT number,
Fail address, fail data and/or failure voltage current value；
Memory function test cell, the input terminal of memory function test cell receive the output letter of comparing function unit
Number, it is analyzed for the failure likelihood to DUT, including bad block, fail data, fail address, failure voltage electric current, and will
The fail message of every DUT is respectively stored into corresponding memory block；Test logic mould is utilized by memory function test cell
Memory outside block is managed burn-in test process, and carries out data analysis to test result.
Preferably, above-mentioned semiconductor memory burn-in test core board, test logic module further includes acting on algorithm
The scrambling unit of pattern generator improves test coverage, accelerates DUT failure probability, with drop for being randomized test vector
Low testing cost promotes the reliability of semiconductor memory.
Preferably, above-mentioned semiconductor memory burn-in test core board, test logic module further include repairing in the figure period
Change device, the output signal of input terminal receiving algorithm pattern generator can be with test period for selecting resolution chart data
Unit selects different resolution charts, further promotes the randomness of test data.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, can obtain down and show
Beneficial effect:
(1) semiconductor memory burn-in test core board provided by the invention, produces in real time according to the parameter configuration of host computer
Raw test vector exports various types of test signals, various resolution charts, and carries out delay adjustment to test signal, reinforces
The processing that driving, waveform control, and power supply signal is compensated, generate the power supply signal for more accurately testing signal, packet
Rising edge and the failing edge position that signal is tested in each test period are included, minimum precision can accomplish within 1ns, improve use
Family is to the customized ability of test waveform and flexibility；It on the other hand, will by test core plate to test result partitioned storage
The data that real time contrast tests in test process save, the information for the DUT that especially fails, including DUT number, failure ground
Location, fail data, failure voltage current value, by the data of these partitioned storages to the control of failure DUT test process and failure
Analysis, realizes the control and failure analysis function in burn-in test to single DUT test process；Pass through memory for example DRAM
The memory space of offer saves the sufficiently long test information of each IO of every DUT, so as to allow DUT manufacturer to each batch
The DUT that fails is for statistical analysis, finds rule, improves yield, promotes product reliability.
(2) semiconductor memory burn-in test core board provided by the invention, preferred embodiment is default, and there are many random letters
Number generator polynomial preferably can also be made by oneself with generating random resolution chart by external storage unit in high speed to save user
The resolution chart of justice, the significant increase randomness of resolution chart play the role of the coverage rate for promoting burn-in test, can be maximum
Degree simulates various practical application scenes, efficient acceleration DUT failure, to promote the reliability of the DUT by burn-in test.
(3) semiconductor memory burn-in test core board provided by the invention, figure period included by preferred embodiment
Modifier, waveshape monitor, clock generator can produce and more accurately test signal, including letter is tested in each test period
Number rising edge and failing edge position, minimum precision can accomplish within 1ns, improve user to the customized energy of test waveform
Power and flexibility.
Detailed description of the invention
Fig. 1 is the system block diagram of semiconductor memory；
Fig. 2 is the functional block diagram of one embodiment of test core plate provided by the invention；
Fig. 3 is Field Programmable Logic Array provided by the invention (FPGA) functional block diagram；
Fig. 4 is testing process schematic diagram.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
Not constituting a conflict with each other can be combined with each other.
Referring to Fig.1~3, semiconductor memory burn-in test core board (Core Board) and its working principle are explained
It states.
Semiconductor memory burn-in test core board includes central processing unit (CPU), for being led to external host computer
Letter controls test process according to instruction, for example jumps, recycles, assignment etc., controlling the customized generation of test vector.Embodiment
In, central processing unit include 32/64 ARM (Advanced RISC Machine, advanced reduced instruction set machine) and including
Program running memory DRAM, gigabit ethernet interface circuit, eMMC data storage circuitry, Nor Flash program storage circuit, string
The peripheries such as row communication interface circuit circuit unit.Central processing unit is also using the SOC for including FPGA and ARM functional module
(System on Chip, piece superior system) is realized.Central processing unit has to be connect for connecting the Ethernet of Ethernet switch
Mouthful, Ethernet switch is connected to by the Ethernet interface；When test, the Ethernet of Ethernet switch and external host computer
Interface is connected, and realizes the communication of test core plate and external host computer.The survey of external host computer is received by Ethernet switch
Examination instruction is transferred to the central processing unit (CPU) of test core plate, and test result is fed back to external host computer by CPU with into one
The analysis of stepping row data.
When test, test vector, process and parameter are editted by the man-machine interface of host computer；Host computer is to test
Vector, process and parameter are compiled, and are translated into the data that test core plate can identify, are downloaded to by Ethernet interface
CPU on test core plate；CPU controls each functional unit on test core plate, makes each functional unit according to the number of compiling
According to being tested, the test result that functional unit each on test core plate returns is uploaded into host computer；Number is completed by host computer
According to statistics, it analyzes, outputs test result.
Semiconductor memory burn-in test core board includes the power clock module for having connection with CPU, for being test
Core board provides working power and clock；It is also used to provide power supply for DUT, the general power of power supply is according to true with the quantity for surveying DUT
It is fixed.
When aging testing system configure muti-piece core board when, due to the Ethernet interface of each piece of core board be all connected to
Too network switch, therefore each test core plate can be communicated independently with host computer, tester, which can individually control, to be appointed
One block of test core plate of anticipating overcomes traditional aging and surveys so that aging testing system may be implemented Slot/Site and individually control
Test system can only accomplish that whole Slot/Site are controlled, together using not convenient, flexible enough defect.
Semiconductor memory burn-in test core board includes test logic module, uses field programmable logic in embodiment
Array (FPGA) realizes the test logic module；There is communication connection between the FPGA and CPU；For generate test vector,
And according to cpu instruction with specific timing and waveform output test signal；And for the test result of each DUT to be respectively stored into
The corresponding subregion of memory；Preliminary analysis is done after the completion of all tests, then by the test result taking-up of storage, it is upper to assist
The operation of test result is rapidly completed in machine；It is transmitted again after the completion of analysis to CPU, host computer is uploaded to by it and does final point
Analysis.
Semiconductor memory burn-in test core board includes the memory (Memory) between FPGA with communication connection,
DRAM device can be used in memory, for example DDR3/DDR4/DDR5, can also use SO-DIMM (Small Outline Dual
In-line Memory Module, small outline dual memory modules).The capacity and speed grade of memory are tested according to user
Demand is determined, if DUT is more with number is surveyed, uses large capacity and the device of high-speed with meet demand as far as possible.In embodiment,
Data transmission between FPGA and memory uses special DDR3/DDR4/DDR5 control interface, and the data width of DRAM is general
8bit/16bit is used, and the data width of SO-DIMM generally uses 64bit/128bit, their interfaces clock frequency
In 800MHz or more, the real-time of data processing ensure that.
In a preferred embodiment, semiconductor memory burn-in test core board includes having drawing for connection with FPGA
Foot driving circuit, pin driver circuit have the interface for connecting DUT；The test that the driving circuit is used to export to FPGA is believed
Number increase driving and accurately time delay adjusts, the test signal for being applied to DUT has adequately adjustment nargin, thus convenient pair
DUT does various limit burn-in tests.
Semiconductor memory burn-in test core board includes the device power source power supply unit (Device for having connection with FPGA
Power Supply, DPS), device power source power supply unit has the interface for connecting DUT；The DPS is used to provide work to DUT
Power supply.Specifically, DPS receives the control information that FPGA is sent and the voltage that test core on board supply clock module provides
Electric current exports after being adjusted under controlling information function to received voltage and current to the power pin of DUT；DPS unit is also
Have the function of that power supply test, DPS also have the function of power supply test, the voltage and current for the power pin to DUT measures；
The voltage and current that DPS is also used to acquire in DUT power pin measures, and sends the result to FPGA.
Semiconductor memory burn-in test core board includes the comparator (Comparator) for having connection with FPGA, the ratio
There is the input interface for receiving DUT signal compared with device, for acquiring the voltage and current in DUT I/O pin and with preset with reference to electricity
It is flat to be compared, low and high level signal export to FPGA according to comparison result, judges whether, and general consistent with desired value by FPGA
The fail message of DUT when inconsistent is all saved in memory, includes DUT number, fail address, fail data, failure electricity
Piezoelectricity flow valuve etc..
In a preferred embodiment, core board includes the precision measurement unit (Precision for having connection with FPGA
Measure Unit, PMU), precision measurement unit has the input interface for receiving DUT signal；PMU is used for the defeated of DUT
Enter to export electric current and more accurately be tested, and is able to satisfy biggish voltage and current measurement range.Due to aging testing system pair
Power supply test it is of less demanding, and DPS unit also has a power supply test function, and PMU unit is apolegamy module, need microvolt or
The module is configured when microampere order voltage and current measurement precision below, and the hardware and software of core board supports the choosing of the module
Match.
The inner function module of the test logic module of the test core plate of embodiment offer is provided in conjunction with Fig. 3.
It include cyclelog (Sequencer) receiving the test instruction that CPU is sent to go forward side by side inside test logic module
Row decoding is converted to executable data, and control algolithm pattern generator, which generates, instructs corresponding test vector, and to entire test
Timing and process are controlled；
Cyclelog preferably includes the control of test sequence and process: issuing time parameter according to host computer, passes through
Clock module, logical operation module inside test logic module and delay adjustment module, generate digital signal rising edge, under
Drop is along position, and generates the test waveform of desired format, is then output to PE (Pin Electronic) driving element, finally
DUT IO is connected to by the device；Row control includes single of stopping/continuation and the test of all DUT, the reality of test vector
When generate control, and to the preservation of test result, upload.
It include algorithm pattern generator (ALPG, Algorithmic Pattern inside test logic module
Generator), input terminal receives the output signal of cyclelog, for address, data needed for generating test vector and
Control bit, their data bit width are all larger than equal to 24bit, guarantee all memory spaces for traversing DUT.
It include the scrambling for acting on algorithm pattern generator inside test logic module in a preferred embodiment
(Scramble) unit improves test coverage, accelerates DUT failure probability, to reduce test for being randomized test vector
Cost and the reliability for promoting semiconductor memory.
In a preferred embodiment, include inside test logic module figure period modifier (Cycle Pallet,
CYP), the output signal of input terminal receiving algorithm pattern generator can be with test period for selecting resolution chart data
Unit selects different resolution charts, further promotes the randomness of test data.
Waveshape monitor (Format Controller, FC) inside test logic module, and act on waveshape monitor
Clock generator (Timing Generator, TG)；The input terminal of waveshape monitor receives the output of cycle of images modifier
Signal；Clock generator is converted to test sequence signal for generating test sequence, by test vector logic, generate when
Sequence information is supplied to waveshape monitor, carries out waveform coding to test vector according to parameter setting by waveshape monitor, is formed most
Whole test signal.
It include input-output unit (Buffer) that input-output unit receives waveshape monitor and produces inside test logic module
Raw test signal is sent to DUT.
It include comparing function unit inside test logic module, input terminal receives the output signal of input-output unit,
DUT feedback signal for will be transmitted by input-output unit is compared with desired value, judge whether it is consistent with desired value, and
The information of DUT when will be inconsistent is all saved in memory, including DUT number, fail address, fail data, failure voltage
Current value etc..
It include memory function test cell inside test logic module, the input terminal of memory function test cell receives
The output signal of comparing function unit, for analyzing for the failure likelihood to DUT, including but not limited to bad block, failure
Data, fail address, failure voltage electric current, and the fail message of each DUT is respectively stored into outside FPGA illustrated in Figure 3
Portion memory block.
The external memory area FPGA includes pin buffer storage (Pin Buffer Memory, PBM), bad block memory block
(Bad Block Memory, BBM), data failure memory block (Data Fail Memory, DFM), data buffering memory block
(Data Buffer Memory, DBM)；By memory function test cell using FPGA external memory to burn-in test mistake
Journey is managed, and can to test result carry out data analysis, this be also be different from existing degradation testing technique improvement it
One.
It is to carry out semiconductor by the aging testing system for being provided with the test core plate of embodiment offer to deposit referring to Fig. 4
The process of reservoir burn-in test.
(1) by the test macro in test board (Burn-In Board, BIB) the insertion case for carrying DUT, fastening is simultaneously
Case chamber door is shut after the isolation of confirmation humidity province, is then powered on, starting box and external host computer are started to work.
(2) ageing time of case and the temperature parameter in the area Xiang Neige are set by host computer, and configured burn-in test
The parameters such as test vector, DUT supply voltage electric current and the DUT IO voltage and current of system are simultaneously compiled into loading of executed file and arrive
Test core plate.
(3) CPU of test core plate generates test instruction and control information according to the executable file received, makes core
Each unit orderly function on plate.
(4) the control information that the FPGA of test core plate is provided according to CPU carries out the test sent to CPU instruction progress
Decoding generates test vector, timing, waveform, output test signal.
(5) pin driver circuit of test core plate and device power source power supply unit to the DUT on test board apply signal and
Power supply starts burn-in test；Test first powers up when starting, then plus signal；First powered-down source, then OFF signal at the end of test；
Specifically:
After pin driver circuit carries out delay adjustment and reinforce driving to the test signal that FPGA is sent, export to DUT's
I/O pin；
The control information that device power source power supply unit is sent according to FPGA unit is to the electricity that power module provides from core board
Output makes DUT enter burn-in test state to the power pin of DUT after current voltage compensates；Specifically, it is managed by DUT IO
The voltage and current test value of foot calculates the decaying in transmission path, is compensated, makes to the decaying in power module outlet
The voltage and current for the signal that the I/O pin of DUT receives is consistent with the voltage and current value being arranged by upper computer software；
(6) it the voltage and current in the comparator acquisition DUT I/O pin of test core plate and is carried out pair with preset standard
Than exporting low and high level signal to FPGA according to comparison result；DPS unit then acquire the voltage and current in DUT power pin into
Row measurement, sends the result to FPGA unit.
(7) FPGA of test core plate judge level in DUT I/O pin, power pin voltage and current value whether with
What is be arranged in step (2) is consistent, if then entering step (9)；Otherwise, the fail message of DUT is all sent to FPGA, includes
DUT number, fail address, fail data, failure voltage current value, and enter step (8)；
(8) fail message is saved in corresponding memory block outside piece by the FPGA on test core plate respectively；And to failure
DUT does insulation blocking processing, the purpose for the arrangement is that retaining scene, is convenient for the specific failure cause of tester's analyzing and positioning, excellent
Change device to design and produce.
(9) judge whether all DUT on test board complete burn-in test, if otherwise entering step (5), if into
Enter step (10).
(10) FPGA of test core plate carries out preliminary analysis to test data, then according to scheduled agreement for example TCP/
IP agreement is packaged, and is uploaded to host computer by CPU.
(11) it is analyzed by host computer according to data of the test request to all DUT on current test board, exports aging
Test result, and classification is identified to failure DUT, upload to external production management system.
In a preferred embodiment, further include following steps:
It is further old to the DUT of present lot or all batches based on fail message by host computer according to test request
Change test data to be analyzed, data analysis especially is carried out to fail message, export chart-information, decides through consultation that position is lost for chip factory
The failure of DUT is imitated, failure regularity is found, is effectively improved yield.In this step, it is each that the basis of analysis is stored in test core plate
The complete fail message of memory block；This depends on each memory block on test core plate, for example pin buffer storage (Pin
Buffer Memory, PBM), bad block memory block (Bad Block Memory, BBM), data failure memory block (Data Fail
Memory, DFM), data buffering memory block (Data Buffer Memory, DBM), memory space is the bottle of aging testing apparatus
Neck, it is same to survey DUT quantity much limited storage spaces on test core plate, therefore limit with survey number；Bigger storage is empty
Between then have bigger competitive advantage, the size of memory space, subregion can be depending on testing requirements.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of semiconductor memory burn-in test core board, which is characterized in that including
Central processing unit receives the test of external host computer for realizing the communication between test core plate and external host computer
Instruction instructs other each functional modules on control test core plate according to test, and functional unit each on test core plate is returned
The test result returned uploads to host computer；
There is the power clock module of connection with central processing unit, for providing working power and clock for test core plate；
There is the test logic module of communication connection with central processing unit, generate test letter for instructing according to central processing unit
Number；And for sending corresponding memory block for the test result of each measured device；And for carrying out failure point to test result
Analysis, sends central processing unit for fail message and is uploaded to external host computer；
There is the memory of communication connection with test logic module, the memory has subregion, preferably includes pin buffering and deposits
Storage area, bad block memory block, data failure memory block and/or data buffering memory block；
There is the device power source power supply unit of connection with test logic module, the device power source power supply unit has tested for connecting
The interface of device；The device power source power supply unit provides working power to measured device by the interface；
There is the comparator of connection with test logic module, the comparator has the input interface for receiving measured device signal,
For acquiring the voltage and current in measured device I/O pin and being compared with preset reference level, exported according to comparison result high
Low level signal to test logic module, judged whether by test logic module it is consistent with desired value, and will be inconsistent when quilt
The fail message subregion for surveying device is saved in the memory.
2. semiconductor memory burn-in test core board as described in claim 1, which is characterized in that the device power source supply
Device receives the voltage and current that the control information that test logic module is sent and power clock module provide, and believes in the control
Power pin of the output to measured device after being adjusted under breath effect to received voltage and current；The device power source power supply unit
It is also used to acquire the voltage and current in measured device power pin to measure, sends the result to test logic module.
3. semiconductor memory burn-in test core board as claimed in claim 1 or 2, which is characterized in that further include and test
Logic module has the precision measurement unit of connection, and precision measurement unit has to be connect for receiving the input of measured device signal
Mouthful, it is measured for the input and output electric current to measured device.
4. semiconductor memory burn-in test core board as claimed in claim 1 or 2, which is characterized in that further include and test
Logic module has the pin driver circuit of connection, and pin driver circuit has the interface for connecting measured device；It is described to draw
Foot driving circuit is used to carry out the test signal that test logic module exports driving increase, time delay adjusts.
5. semiconductor memory burn-in test core board as claimed in claim 1 or 2, which is characterized in that the test logic
Data transmission between module and memory uses DDR3/DDR4/DDR5 control interface, the data when memory uses DRAM
Width uses 8bit/16bit, uses 64bit/128bit using data width when SO-DIMM.
6. semiconductor memory burn-in test core board as claimed in claim 1 or 2, which is characterized in that the test logic
Module includes
Cyclelog, the test for receiving central processing unit transmission, which instructs and carries out decoding, is converted to executable data, and is used for
Test sequence and process are controlled；
Algorithm pattern generator receives the output signal of cyclelog, generates test in real time according to the parameter configuration of host computer
Vector；
Waveshape monitor and the clock generator for acting on waveshape monitor, when the clock generator is for generating test
Sequence；The waveshape monitor is used to carry out waveform coding to test vector according to parameter setting and test sequence, is formed final
Test signal；
Input-output unit, the test signal for generating waveshape monitor are sent to measured device；And it is tested for receiving
The feedback signal of device；
Comparing function unit, the measured device feedback signal for sending input-output unit compare with desired value, sentence
It is disconnected whether consistent with desired value, and will be inconsistent when measured device information preservation to memory.
7. semiconductor memory burn-in test core board as claimed in claim 6, which is characterized in that the algorithm figure generates
Device is also built-in, and there are many random signal generator polynomial and/or the customized resolution charts of user.
8. semiconductor memory burn-in test core board as claimed in claims 6 or 7, which is characterized in that the test logic
Module further includes memory function test cell, and the input terminal of memory function test cell receives the output of comparing function unit
Signal is analyzed for the failure likelihood to measured device, and the fail message of every measured device is respectively stored into
Corresponding memory block.
9. semiconductor memory burn-in test core board as claimed in claims 6 or 7, which is characterized in that the test logic
Module further includes the scrambling unit for acting on algorithm pattern generator, for being randomized test vector.
10. semiconductor memory burn-in test core board as claimed in claims 6 or 7, which is characterized in that the test logic
Module further includes figure period modifier, the output letter of the input terminal receiving algorithm pattern generator of the figure period modifier
Number, for selecting resolution chart data.
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