CN111370050B - Diagnostic calibration system and method for test equipment - Google Patents

Diagnostic calibration system and method for test equipment Download PDF

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Publication number
CN111370050B
CN111370050B CN202010151266.1A CN202010151266A CN111370050B CN 111370050 B CN111370050 B CN 111370050B CN 202010151266 A CN202010151266 A CN 202010151266A CN 111370050 B CN111370050 B CN 111370050B
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module
calibration
upper computer
item
computer
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CN111370050A (en
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张芾
邓标华
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Wuhan Jinghong Electronic Technology Co ltd
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Wuhan Jinghong Electronic Technology Co ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402Internal storage of test result, quality data, chip identification, repair information

Abstract

One aspect of the present invention provides a diagnostic calibration system and method for a test device, including: the system comprises an upper computer, a communication module and K lower computers, wherein K is more than or equal to 1; the host computer includes: the upper computer is electrically connected with the K lower computers through the communication module; the lower computer comprises a plurality of types of calibration modules to be diagnosed; the items to be executed comprise the diagnosis of the electrical characteristics and/or the memory read-write characteristics of the calibration module to be diagnosed; and the upper computer is also used for calibrating the calibration module to be diagnosed according to the project execution condition. The invention provides a scheme for executing diagnosis and calibration in a mode of no difficulty in use and convenient operation, thereby saving labor and time.

Description

Diagnostic calibration system and method for test equipment
Technical Field
The invention belongs to the technical field of photoelectric detection, and particularly relates to a diagnosis and calibration system and method of test equipment.
Background
Semiconductor memories are composed of a large number of identical memory cells and input and output circuits, etc., and are important components in modern digital systems, particularly computer systems. A semiconductor memory test apparatus is an apparatus that performs a severe test on a semiconductor memory device in both operating environment and electrical performance to determine whether the semiconductor memory device has developed a failure. The reliability of the test equipment is related to the reliability of the semiconductor memory device, and in order to ensure the judgment of the reliability of the semiconductor memory device, the test equipment still has good performance in the use process of the semiconductor memory device for a long period of time.
In the long-time use process, if the test equipment has problems, the electrical parameters input into the semiconductor memory are not accurate any more, the problems are found out manually by one device and one module, time and labor are wasted, the process of the aging test of the semiconductor memory and the accuracy of a test result are influenced, and more manpower and longer time are inevitably required to be invested if a plurality of assemblies are required to be diagnosed and calibrated in a traditional mode. Therefore, a need exists for a fast, convenient, operationally friendly, automated diagnostic calibration system for semiconductor memory test equipment.
Disclosure of Invention
The invention provides a diagnosis and calibration system and method of test equipment, which solve the problems that the test equipment can only be found out if the electrical characteristic parameter deviation exists in the hardware aspect or the FPGA logic aspect of the test equipment or if the memory read-write is inconsistent and the like by labor and time; the scheme for executing the diagnosis and calibration in a mode of no difficulty in use and convenient operation is provided, so that the labor and the time are saved, the result is displayed clearly, and the recording is convenient.
One aspect of the present invention provides a diagnostic calibration system for a test apparatus, comprising: the system comprises an upper computer, a communication module and K lower computers, wherein K is more than or equal to 1;
the host computer includes: the system comprises a display item module, a selection item module and an item execution result display module, wherein the display item module is used for displaying items to be executed of each calibration module to be diagnosed, the selection item module is used for selecting an item execution instruction, and the item execution result display module is used for displaying an execution result of an item;
the upper computer is electrically connected with the K lower computers through the communication module;
the lower computer comprises a plurality of types of calibration modules to be diagnosed;
the calibration module to be diagnosed comprises one or more of an integrated board (SLOT), a power supply module (VS), an analog-to-digital conversion module (ADC), a digital-to-analog conversion module (DAC), a first board module (SITE), a second board module (BIB) and a third board module (FT);
the item to be executed comprises the step of diagnosing the electrical characteristics and/or the memory read-write characteristics of the calibration module to be diagnosed;
and the upper computer is also used for calibrating the calibration module to be diagnosed according to the project execution condition.
Optionally, the integration board (SLOT) is configured to integrate the first board module (SITE) and the second board module (BIB); the first board module (SITE) is connected with the second board module (BIB); the power supply module (VS), the analog-to-digital conversion module (ADC) and the digital-to-analog conversion module (DAC) are connected in sequence.
Optionally, the host computer still includes: the system comprises an item running log management module and a storage module, wherein the item running log management module is used for managing item running logs, and the storage module is used for storing execution results in a binary system mode.
Optionally, the upper computer further comprises a screening and sorting module, and the screening and sorting module is used for rapidly finding the specified diagnosis items through a screening and filtering function.
Optionally, the upper computer further includes a state detection module, and the state detection module is configured to determine whether the lower computer is in an idle state and whether a semi-automatic project exists.
Optionally, the lower computer further comprises a scheduling module, and the scheduling module is used for performing thread scheduling.
In another aspect, the present invention provides a diagnostic calibration method applied to the test equipment of the above diagnostic calibration system, including the following steps:
step 1: selecting the item to be executed and the item execution instruction on the upper computer;
step 2: the lower computer executes the project;
and step 3: the lower computer feeds back a project execution result to the upper computer;
and 4, step 4: and the upper computer calibrates the calibration module to be diagnosed according to the project execution condition.
Optionally, the selecting, by the upper computer, the item to be executed and the item execution instruction specifically include:
a user selects a project needing diagnosis or calibration through the upper computer, and the upper computer judges whether the selected project is to be executed or not according to the idle state of the lower computer and whether a semi-automatic project exists or not.
Optionally, the lower computer performs project execution specifically as follows:
and the lower computer receives data and puts the data into a receiving queue, the data are scheduled through a receiving thread, the lower computer maps corresponding command words into function information codes and node information codes according to instructions sent by the upper computer, so that the diagnosis and calibration of functions corresponding to the function information codes are executed on hardware structures corresponding to the node information codes, the execution results are put into a sending queue after the execution is finished, and the sending thread is used for scheduling.
Optionally, the calibrating, by the upper computer, the calibration module to be diagnosed according to the item execution condition specifically includes:
when the corresponding part of the test equipment has no problem, the upper computer displays that the part passes;
when the parameters of the diagnosis power module (VS), the analog-to-digital conversion module (ADC), the digital-to-analog conversion module (DAC) and the second plate module (BIB) deviate from the normal value range, executing a calibration program to enable the parameters of the corresponding modules to reach the normal value range;
and when the number of the bad blocks of the first plate module (SITE), the second plate module (BIB) and the third plate module (FT) exceeds a certain threshold value, replacing corresponding hardware.
The invention has the advantages that:
the invention provides a diagnosis and calibration system and a method of test equipment, which change the defect that only one part of the test equipment can be diagnosed and calibrated at one time in the traditional mode, and the system saves the cost because more manpower and longer time are inevitably required for diagnosing and calibrating a plurality of assemblies in the traditional mode.
The results are clearly evident. In the diagnosis item, if the corresponding part of the test equipment has no problem, the display is passed; if there is a problem, it is indicated as failed. The user can conveniently calibrate the failed item or replace the corresponding hardware.
A variety of results viewing modes are provided. The result of the diagnosis calibration can be checked from the upper computer, and the specific execution condition of specific diagnosis items can be acquired from the printed detailed information; the current diagnostic calibration result can be saved and viewed by loading next time.
Provides a more convenient and friendly operation mode. The user only needs to interact with the upper computer interface, and does not need to care what way the lower computer adopts and what flow is executed.
The plurality of lower computer diagnosis items can be executed in parallel without mutual interference, the states can be different from each other, and the results are collected respectively and displayed in the upper computer in a centralized manner.
And (4) automation. The diagnosis and calibration can be started only by executing issuing operation on an upper computer interface, and partial projects need a user to confirm that hardware conditions are met for the second time, so that redundant operation is greatly reduced.
Hardware components and hardware functions of the test equipment are respectively abstracted into node information codes and function information codes, so that software can be conveniently realized.
Drawings
FIG. 1: a system block diagram;
FIG. 2: a system block diagram of an upper computer;
FIG. 3: a state execution flow diagram;
FIG. 4: a lower computer calibration system block diagram;
FIG. 5: and the lower computer processes the interactive flow chart.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The specific implementation mode of the invention is a system based on a Client/Server structure, which consists of an upper computer and a plurality of lower computers (figure 1), wherein the lower computers are borne on an integrated board (SLOT) and consist of hardware and software on each SLOT single board. And the communication between the upper computer and the lower computer is carried out by a self-defined TCP/IP protocol.
As shown in fig. 1 and fig. 2, the system is a scheme in which an upper computer operates to issue an instruction to display a result, and a lower computer receives, processes, and executes the instruction to return the result. The system comprises at least one server (upper computer) and a plurality of clients (lower computers).
The host computer includes: the system comprises a display item module, a selection item module and an item execution result display module, wherein the display item module is used for displaying items to be executed of each calibration module to be diagnosed, the selection item module is used for selecting an item execution instruction, and the item execution result display module is used for displaying an execution result of an item;
the lower computer comprises a plurality of types of calibration modules to be diagnosed;
the calibration module to be diagnosed comprises one or more of an integrated board (SLOT), a power supply module (VS), an analog-to-digital conversion module (ADC), a digital-to-analog conversion module (DAC), a first board module (SITE), a second board module (BIB) and a third board module (FT);
the item to be executed comprises the step of diagnosing the electrical characteristics and/or the memory read-write characteristics of the calibration module to be diagnosed;
and the upper computer is also used for calibrating the calibration module to be diagnosed according to the project execution condition.
As shown in fig. 4, the lower computer of the diagnosis system includes: an integrated board (SLOT), a first board module (SITE), a second board module (BIB), a third board module (FT);
the upper computer is connected with the communication modules, and the communication modules are respectively connected with the K lower computers in sequence; the first board module (SITE) is connected with the second board module (BIB); the power supply module (VS), the analog-to-digital conversion module (ADC) and the digital-to-analog conversion module (DAC) are connected in sequence.
The integrated board (SLOT) is a general name of a set module formed by connecting a first board module (SITE) and a second board module (BIB);
the first plate module (SITE, main control board) is used for integrating a network interface of a lower computer, a power supply module (VS), an analog-to-digital conversion module (ADC), a digital-to-analog conversion module (DAC) and a microprocessor.
The second board module (BIB, burn-in board) is connected to the third board module (FT) and is connected to the SITE board through three bridge boards, as shown in fig. 4.
The third plate module (FT, feed through plate), the effect of FT board in semiconductor test equipment is used for bearing the chip that awaits measuring, and a plurality of FT boards are inserted on the BIB board, and the chip that awaits measuring is inserted on the FT board. The FT board is provided with a connection storage module, a phase-locked loop module and a FT board power supply.
The power supply module (VS) is used for providing power supply for the BIB board; the analog-to-digital conversion module (ADC) is used for performing analog-to-digital conversion; the digital-to-analog conversion module (DAC) is used for performing digital-to-analog conversion.
The single boards and the modules are abstracted into node information codes in the system, the electrical characteristics of the hardware structures, memory reading and writing and the like are abstracted into function information codes, and the execution items are abstracted into the function information codes corresponding to the node information codes in the system. Specifically, the upper computer sends an instruction, the lower computer receives and processes the instruction to diagnose whether parameters of a power supply module (VS), a DAC/ADC and a BIB board are in a normal value range, and if the parameters deviate from the normal value range, calibration is executed; and diagnosing whether bad blocks exist in the memory read-write of the SITE board, the FT board and the BIB board. In some implementations, the diagnostics on SITE include diagnostics of microprocessor memory on the SITE board (read and write to memory, pressure testing), and determining its electrical characteristics for VS, ADC/DAC. The diagnosis of the BIB board is to diagnose whether the 12V voltage is in a normal range or not and to diagnose whether the BIB board information can be read from an interface on the BIB board or not.
Optionally, the plurality of lower computers include a plurality of SLOTs, the plurality of SLOTs work in parallel without mutual interference, for example, the sit single board of the SLOT2 can be diagnosed while the SLOT1 power module is diagnosed.
As shown in fig. 2, the upper computer is triggered to operate by the user. The user selects items needing diagnosis or calibration and sends the items to the lower computer to start execution, and meanwhile, the user operates the upper computer to determine which item the lower computer diagnoses or calibrates, and the lower computer starts to execute circular execution or stops executing. The automatic project can be executed after being selected by a user, and the semi-automatic project can be executed after the semi-automatic project is ensured by the user to meet the hardware execution condition and after secondary confirmation. After the project execution is stopped or finished, the user can see the execution result of the diagnosis calibration project displayed in the upper computer, and the result can be diagnosis pass, namely the project has no problem; or failure, i.e., the item has a problem, requiring calibration or hardware replacement; or not supported, i.e. the lower computer current iteration version is not supported yet. The specific execution situation can be seen by looking at the printed log in the execution process.
And the log management module of the upper computer automatically stores all printing information in the program running process. The system comprises connection state information of a lower computer and detailed information of diagnosis and calibration executed by the lower computer.
And the data storage module of the upper computer manually stores the execution result information. And saving the selection state of the selection module by using a binary file, and issuing a specific diagnosis calibration item, an execution result of the diagnosis calibration and a color mark at the time.
As shown in fig. 3, the lower computer may be in three states: idle, running, unavailable (i.e., the lower computer is disconnected from the upper computer). An idle state: the instruction execution is completed or the instruction is waited to be executed; in the operation: executing the instruction issued by the upper computer; not available: the connection is broken. Only the lower computer is in the idle state and can execute the instruction issued by the lower computer.
The specific method for judging the state of the lower computer by the upper computer is as follows:
judging whether the lower computer is in an unavailable state, and obtaining the state from the TCP connection state of the upper computer and the lower computer, wherein the TCP connection state is normal and is not in the unavailable state; the TCP connection state is abnormal and is in an unavailable state.
Not in an unavailable state. When the upper computer issues an execution starting command, a starting state mark is stored in the upper computer; and the lower computer sends an end state mark to the upper computer when the execution of the project is finished. And when the starting state mark exists in the upper computer but the ending state mark is not received yet, the lower computer is in the running state. And when the upper computer has no starting state mark but has an ending state mark, the lower computer is in an idle state.
The upper computer displays specific diagnosis and calibration items by reading the function information table and the node information table which are configured in the database file, and specifically displays which modules can be diagnosed and calibrated. The node information codes in the node information table in the configuration file correspond to hardware modules of a lower computer, such as a power supply module; the function information codes in the function information table correspond to function items, such as current values, voltage values, temperature values and the like. The upper computer and the lower computer maintain the same function information table and node information table. Meanwhile, the upper computer provides a screening, filtering and sorting function, a user can quickly find the diagnosis items with the appointed functions of the appointed modules through the screening and filtering function, the user can sort the items needing to be diagnosed and calibrated from the interface of the upper computer, and the sorted items can be preferentially executed by the lower computer.
The screening and sorting module of the upper computer is composed of a screening module, a selecting function module and a sorting module.
The screening module is used for selecting the lower computer to be calibrated and diagnosed and screening out the lower computer to be diagnosed and calibrated;
the selection function module is used for screening out the lower computers to be diagnosed and calibrated according to the screening module and further selecting a module for diagnosing and calibrating from the lower computers to be diagnosed and calibrated.
The sorting module is used for sorting by a user to enable the sorted previous diagnosis calibration items to be executed in advance.
The user can save the current diagnosis result to the computer by operating the result saving function in the upper computer, and can also operate the result loading function in the upper computer to redisplay the loaded result to the upper computer. The result of the diagnosis and calibration can be checked for the second time conveniently.
As shown in fig. 5, the upper computer of the diagnosis and calibration system is operated by a user to determine which modules are issued and executed, and which items are diagnosed or calibrated. Data is transmitted through a TCP/IP protocol, and TCP is a connection-oriented network transmission protocol and has reliability. The lower computer (client) receives the data and then puts the data into a receiving queue, the receiving thread schedules the data, then the lower computer specifically executes diagnosis or calibration on the designated module, the execution result is put into a sending queue after the execution is finished, the sending thread schedules the data, and the result is also transmitted through a TCP/IP protocol and fed back to the upper computer (server) for display.
The receiving queue and the sending queue can ensure that the sequencing function of the upper computer is effective, the sequencing is executed before the front sending and after the back sending. At the same time, the use of queues ensures that an execution instruction is not missed.
When the execution instruction is processed, the lower computer maps the corresponding command word into the function information code and the node information code according to the instruction sent by the upper computer, so that the diagnosis and calibration of the function corresponding to the function information code are executed on the hardware structure corresponding to the node information code, and meanwhile, the detailed log is printed and the processing result is returned.
Another aspect of the present application also provides a diagnostic calibration method applied to the test equipment of the above diagnostic calibration system, including the following steps:
step 1: selecting the item to be executed and the item execution instruction on the upper computer;
step 2: the lower computer executes the project;
and step 3: the lower computer feeds back a project execution result to the upper computer;
and 4, step 4: and the upper computer calibrates the calibration module to be diagnosed according to the project execution condition.
In some implementations, the upper computer performs calibration according to the project execution condition as follows:
when the corresponding part of the test equipment has no problem, the upper computer displays that the corresponding part passes;
when the parameters of the diagnosis power module (VS), the analog-to-digital conversion module (ADC) and the digital-to-analog conversion module (DAC) deviate from the normal value range, executing a calibration program to enable the parameters of the corresponding modules to reach the normal value range;
and when the number of the bad blocks of the first plate module (SITE) and the third plate module (FT) exceeds a certain threshold value, replacing corresponding hardware.
In some implementations, the first and second sensors may, in particular,
the calibration of the power supply module (VS) and the analog-to-digital conversion module (ADC) is as follows:
the reference power supply is used as an input theoretical value, an actual measurement value is obtained through an analog-to-digital conversion module (ADC), a linear function of the input theoretical value and the actual measurement value is fitted, calibration is the correction of the linear function, and parameters reach a normal range.
Calibration of the power supply module (VS): a user inputs a theoretical value, the theoretical value is sampled by a digital-to-analog conversion module (DAC), a power supply module (VS) and an analog-to-digital conversion module (ADC) to obtain an actual measurement value, a linear function of the input theoretical value and the actual measurement value is fitted, and calibration is to correct the linear function so that parameters reach a normal range.
The upper computer carries out calibration according to the project execution condition and further comprises: the system comprises an upper computer calibration analog-to-digital conversion module, an upper computer calibration power supply module, an upper computer diagnosis storage module, an upper computer diagnosis phase-locked loop module and an upper computer diagnosis temperature sensor;
the upper computer calibration analog-to-digital conversion module comprises:
the upper computer identifies the analog-to-digital conversion module as a module to be calibrated according to the identification data fed back by the analog-to-digital conversion module in the node feedback table;
the upper computer obtains a proportional coefficient and an offset coefficient in a linear calibration model of the analog-to-digital conversion module through a least square method according to the reference power supply feedback amplitude sequence in the function feedback table and the reference power supply amplitude sequence in the function information table;
and if the user selects the automatic calibration mode through the upper computer, the proportionality coefficient and the offset coefficient in the linear calibration model of the analog-to-digital conversion module are transmitted to the microprocessor through the network switching equipment and the network module and are stored.
If the user selects the semi-automatic calibration mode through the upper computer, after the user performs secondary confirmation on the upper computer, the proportional coefficient and the offset coefficient in the linear calibration model of the analog-digital conversion module are transmitted to the microprocessor through the network exchange equipment and the network module and are stored.
The upper computer calibration power supply module is as follows:
the upper computer identifies the power supply module as a module to be calibrated according to the identification data fed back by the power supply module in the node feedback table;
the upper computer multiplies each power supply amplitude of the power supply module feedback amplitude sequence in the function feedback table by a proportional coefficient in a linear calibration model of the digital conversion module in sequence and superposes a deviation coefficient in the linear calibration model of the digital conversion module to obtain a calibrated power supply module feedback amplitude sequence;
the upper computer feeds back the amplitude sequence of the calibrated power module and the amplitude sequence of the power module in the function information table, and obtains a proportionality coefficient and an offset coefficient in a linear calibration model of the power module through a least square method to finish calibration;
and if the user selects the automatic calibration mode through the upper computer, the proportionality coefficient and the offset coefficient in the linear calibration model of the power module are transmitted to the microprocessor through the network switching equipment and the network module and are stored.
If the user selects the semi-automatic calibration mode through the upper computer, after the user performs secondary confirmation on the upper computer, the proportional coefficient and the offset coefficient in the linear calibration model of the power supply module are transmitted to the microprocessor through the network switching equipment and the network module and are stored.
The upper computer diagnosis storage module is as follows:
the upper computer identifies the storage module as a module to be diagnosed according to the identification data fed back by the storage module in the node feedback table;
and the upper computer compares each stored feedback data in the stored feedback data sequence in the function feedback table with each stored data in the stored data sequence in the function information table in sequence, if the data comparison is consistent every time, the state of the storage module is judged to be normal, otherwise, the state of the storage module is judged to be abnormal, and the storage module is recommended to be replaced.
The upper computer diagnosis phase-locked loop module is as follows:
the upper computer identifies the phase-locked loop module as a module to be diagnosed according to the identification data fed back by the phase-locked loop module in the node feedback table;
and the upper computer compares each group of frequency and phase in the phase-locked loop feedback data sequence in the function feedback table with each group of frequency and phase in the phase-locked loop data sequence in the function information table in sequence, if the error between the frequencies and the error between the phase-locked loops are within the normal range in each comparison process, the state of the phase-locked loop module is judged to be normal, otherwise, the state of the phase-locked loop module is judged to be abnormal, and the phase-locked loop module is recommended to be replaced.
The upper computer diagnosis temperature sensor comprises:
the upper computer identifies the temperature sensor as a module to be diagnosed according to the temperature sensor feedback identification data in the node feedback table;
and the upper computer compares the temperature feedback data in the function feedback table with the normal temperature range, if the temperature feedback data is in the normal temperature range, the ambient temperature is normal, and otherwise, the state of the semiconductor memory aging test equipment is judged to be abnormal.
It should be understood that parts of the specification not set forth in detail are well within the prior art.
It should be understood that the above description of the preferred embodiments is given for clarity and not for any purpose of limitation, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. A diagnostic calibration system for a test device, comprising: the system comprises an upper computer, a communication module and K lower computers, wherein K is more than or equal to 1;
the host computer includes: the system comprises a display item module, a selection item module and an item execution result display module, wherein the display item module is used for displaying items to be executed of each calibration module to be diagnosed, the selection item module is used for selecting an item execution instruction, and the item execution result display module is used for displaying an execution result of an item;
the upper computer is electrically connected with the K lower computers through the communication module;
the lower computer comprises a plurality of types of calibration modules to be diagnosed;
the calibration module to be diagnosed comprises one or more of an integrated board (SLOT), a power supply module (VS), an analog-to-digital conversion module (ADC), a digital-to-analog conversion module (DAC), a first board module (SITE), a second board module (BIB) and a third board module (FT);
the item to be executed comprises the step of diagnosing the electrical characteristics and/or the memory read-write characteristics of the calibration module to be diagnosed;
the upper computer is also used for calibrating the calibration module to be diagnosed according to the project execution condition;
the upper computer further comprises a screening and sorting module, and the screening and sorting module can quickly find the designated diagnosis items through the screening and filtering functions;
the lower computer further comprises a scheduling module, and the scheduling module is used for scheduling threads.
2. The diagnostic calibration system for test equipment of claim 1, wherein: the integration board (SLOT) is used for integrating the first board module (SITE) and the second board module (BIB); the first board module (SITE) is connected with the second board module (BIB); the power supply module (VS), the analog-to-digital conversion module (ADC) and the digital-to-analog conversion module (DAC) are connected in sequence.
3. The diagnostic calibration system for test equipment of claim 1, wherein: the host computer still includes: the system comprises an item running log management module and a storage module, wherein the item running log management module is used for managing item running logs, and the storage module is used for storing execution results in a binary system mode.
4. The diagnostic calibration system for test equipment of claim 1, wherein: the upper computer further comprises a state detection module, and the state detection module is used for judging whether the lower computer is in an idle state or not and whether a semi-automatic project exists or not.
5. A diagnostic calibration method applied to a test device of the diagnostic calibration system as set forth in any one of claims 1 to 4, characterized in that: the method comprises the following steps:
step 1: selecting the item to be executed and the item execution instruction on the upper computer;
step 2: the lower computer executes the project;
and step 3: the lower computer feeds back a project execution result to the upper computer;
and 4, step 4: the upper computer calibrates the calibration module to be diagnosed according to the project execution condition;
the lower computer performs project execution specifically as follows:
and the lower computer receives data and puts the data into a receiving queue, the data are scheduled through a receiving thread, the lower computer maps corresponding command words into function information codes and node information codes according to instructions sent by the upper computer, so that the diagnosis and calibration of functions corresponding to the function information codes are executed on hardware structures corresponding to the node information codes, the execution results are put into a sending queue after the execution is finished, and the sending thread is used for scheduling.
6. The diagnostic calibration method for test equipment of claim 5, wherein:
the selecting the item to be executed and the item execution instruction at the upper computer specifically includes:
a user selects a project needing diagnosis or calibration through the upper computer, and the upper computer judges whether the selected project is to be executed or not according to the idle state of the lower computer and whether a semi-automatic project exists or not.
7. The diagnostic calibration method for test equipment of claim 5, wherein: the upper computer calibrates the calibration module to be diagnosed according to the project execution condition, specifically:
when the corresponding part of the test equipment has no problem, the upper computer displays that the part passes;
when the parameters of the diagnosis power module (VS), the analog-to-digital conversion module (ADC), the digital-to-analog conversion module (DAC) and the second plate module (BIB) deviate from the normal value range, executing a calibration program to enable the parameters of the corresponding modules to reach the normal value range;
and when the number of the bad blocks of the first plate module (SITE), the second plate module (BIB) and the third plate module (FT) exceeds a certain threshold value, replacing corresponding hardware.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101098359A (en) * 2006-06-27 2008-01-02 中兴通讯股份有限公司 Time sharing test approach for tester
US7693981B2 (en) * 2001-01-24 2010-04-06 Telecommunication Systems, Inc. System and method to publish information from servers to remote monitor devices
CN106950489A (en) * 2017-04-06 2017-07-14 芯海科技(深圳)股份有限公司 A kind of electric power detection and fail-ure criterion system and method
CN109346119A (en) * 2018-08-30 2019-02-15 武汉精鸿电子技术有限公司 A kind of semiconductor memory burn-in test core board
CN109411007A (en) * 2018-12-11 2019-03-01 武汉精鸿电子技术有限公司 A kind of Common Flash Memory test macro based on FPGA

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2807594B1 (en) * 2012-01-26 2021-08-25 BlackBerry Limited Methods and devices for distributing content to an electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7693981B2 (en) * 2001-01-24 2010-04-06 Telecommunication Systems, Inc. System and method to publish information from servers to remote monitor devices
CN101098359A (en) * 2006-06-27 2008-01-02 中兴通讯股份有限公司 Time sharing test approach for tester
CN106950489A (en) * 2017-04-06 2017-07-14 芯海科技(深圳)股份有限公司 A kind of electric power detection and fail-ure criterion system and method
CN109346119A (en) * 2018-08-30 2019-02-15 武汉精鸿电子技术有限公司 A kind of semiconductor memory burn-in test core board
CN109411007A (en) * 2018-12-11 2019-03-01 武汉精鸿电子技术有限公司 A kind of Common Flash Memory test macro based on FPGA

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