CN112255527A - Testing component and integrated circuit testing machine - Google Patents
Testing component and integrated circuit testing machine Download PDFInfo
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- CN112255527A CN112255527A CN202011018344.7A CN202011018344A CN112255527A CN 112255527 A CN112255527 A CN 112255527A CN 202011018344 A CN202011018344 A CN 202011018344A CN 112255527 A CN112255527 A CN 112255527A
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- 238000012360 testing method Methods 0.000 title claims abstract description 123
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- 238000004088 simulation Methods 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 claims description 4
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- 230000007547 defect Effects 0.000 abstract description 6
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- 238000010586 diagram Methods 0.000 description 6
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- 230000008859 change Effects 0.000 description 3
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- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention provides a test component and an integrated circuit tester, wherein the test component comprises a core logic unit, and the core logic unit outputs a test signal synchronous with the period of a clock signal according to a received data format description file and the clock signal; and can rewrite the internal logic according to an external programmable signal. So configured, the following beneficial effects are produced: 1) minor test task changes can be adapted by changing the data format description file; 2) larger test task changes can be adapted through the programmable signal; 3) by generating test signals synchronized with the period of the clock signal, it is helpful to improve the consistency among a plurality of test modules and eliminate the defect of insufficient time base precision of high-versatility elements. By the beneficial effects, the test component and the integrated circuit tester provided by the invention solve the problems of fixed test function and low universality of the integrated circuit tester in the prior art.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test assembly and an integrated circuit tester.
Background
Referring to fig. 1, fig. 1 is a schematic diagram of an integrated circuit tester, in which a dedicated control circuit has a test signal generation logic therein, and when receiving an external control signal, the dedicated control circuit outputs an initial test signal, and performs conversion by a functional circuit, thereby finally completing the inspection of a chip under test.
In the integrated circuit tester, the dedicated control circuit is designed only for one or one type of chip, and when the chip to be tested changes or the subsequent functional circuit changes, the dedicated control circuit cannot work, or when the test function needs to be updated, the dedicated control circuit cannot be correspondingly changed, so that the universality is not strong. On the other hand, the arrangement of the dedicated control circuit on the integrated circuit testing machine is not independently provided in a certain area of the test load board, but is mixed with the functional circuit and other circuits (the main purpose of fig. 1 is to show the operating principle of the integrated circuit testing machine, so that the dedicated control circuit is mistakenly arranged as being independently understood from what is shown in the figure, but is not actually the case), and therefore, when the dedicated control circuit is also difficult to maintain or update by means of hardware replacement, the universality of the whole integrated circuit testing machine is not strong.
In short, in the prior art, the test function of the integrated circuit tester is fixed, and the universality is not strong.
Disclosure of Invention
The invention provides a test component and an integrated circuit tester, and aims to solve the problems that in the prior art, the test function of the integrated circuit tester is fixed and the universality is not strong.
In order to solve the technical problem, the invention provides a test component for an integrated circuit tester, wherein the test component comprises a core logic unit and a vector memory which are in communication connection, the core logic unit comprises a programmable input end and a core circuit, and the vector memory stores a data format description file of a chip to be tested;
the vector memory is configured to send the data format description file to the core circuit when a preset condition is met;
the core circuit is configured to receive the data format description file and a clock signal and output a test signal synchronous with the period of the clock signal according to self logic;
the core logic unit is configured to receive a programmable signal via a programmable input and to rewrite the core circuitry in accordance with the programmable signal.
Optionally, the core logic unit includes an FPGA chip, and the FPGA chip includes the programmable input terminal and the core circuit.
Optionally, the test component further includes a configuration memory, where the configuration memory stores a core program and is in communication connection with the programmable input terminal, and the configuration memory is configured to, after the test component is powered on, send a programmable signal to the programmable input terminal according to its own core program, and drive the core circuit to be rewritten.
Optionally, the test component further includes an algorithm simulation unit, the vector memory is in communication connection with the core logic unit through the algorithm simulation unit, and the algorithm simulation unit is configured to convert the format of the data format description file into a format that can be analyzed by the core logic unit.
Optionally, the test component further includes a digital signal processing unit, and the digital signal processing unit is in communication connection with the core logic unit and is configured to assist the core logic unit in processing digital signal operation.
Optionally, the test component further includes a capture memory, and the capture memory is configured to receive and store the output signal of the chip to be tested.
Optionally, the capture memory is in communication connection with a vector memory, the vector memory is configured to send the data format description file to the capture memory when a preset condition is met, and the capture memory is configured to perform format conversion on the received output signal of the chip to be tested according to the received data format description file and then store the converted output signal.
Optionally, the test component further includes a scan memory configured to output a test signal independently of the core logic unit.
Optionally, the scan memory includes only one input terminal and one output terminal.
In order to solve the technical problem, the present invention provides an integrated circuit testing machine, which includes a test load board and the test component, wherein the test component is detachably connected to the test load board, a control end of the test load board is in communication connection with the core circuit, and the core circuit is in communication connection with a chip to be tested through a functional circuit on the test load board.
In summary, in the test component and the integrated circuit tester provided by the present invention, the test component includes a core logic unit and a vector memory, which are in communication connection, the core logic unit includes a programmable input terminal and a core circuit, and the vector memory stores a data format description file of a chip to be tested; the vector memory is configured to send the data format description file to the core circuit when a preset condition is met; the core circuit is configured to receive the data format description file and a clock signal and output a test signal synchronous with the period of the clock signal according to self logic; the core logic unit is configured to receive a programmable signal via a programmable input and to rewrite the core circuitry in accordance with the programmable signal. So configured, the following beneficial effects are produced:
1) when the difference between the new chip to be tested and the original chip to be tested is not large, the new chip to be tested can be adapted by changing the data format description file;
2) when the change of a new tested chip is large or a test task is changed, the core circuit is rewritten through the programmable signal so as to adapt to the new tested chip or the new test task;
3) by receiving a clock signal and generating a test signal synchronized with the period of the clock signal, it is helpful to improve the consistency among a plurality of test modules and eliminate the defect of insufficient time base precision of high-versatility elements.
By the beneficial effects, the test component and the integrated circuit tester provided by the invention solve the problems of fixed test function and low universality of the integrated circuit tester in the prior art.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1 is a schematic diagram of an integrated circuit tester;
FIG. 2 is a schematic structural diagram of a test assembly according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an integrated circuit tester according to an embodiment of the invention.
In the drawings:
10-a test assembly; 20-a card;
1, capturing a memory; 2-vector memory; 3-scanning the memory; 4-an algorithm simulation unit; 5-core logic unit; 6-a digital signal processing unit; 7-configuration memory; 8-checking the memory.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "proximal end" and "distal end" generally refer to the corresponding two parts, which include not only the end points, but also the terms "mounted", "connected" and "connected" should be understood broadly, e.g., as a fixed connection, as a detachable connection, or as an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The core idea of the invention is to provide a test component and an integrated circuit tester, which are used for solving the problems of fixed test function and weak universality of the integrated circuit tester in the prior art.
The following description refers to the accompanying drawings.
Referring to fig. 2 to 3, fig. 2 is a schematic structural diagram of a test assembly according to an embodiment of the invention; FIG. 3 is a schematic diagram of an integrated circuit tester according to an embodiment of the invention.
As shown in fig. 2, this embodiment provides a test component 10 for an integrated circuit tester, where the test component 10 includes a core logic unit 5 and a vector memory 2 that are in communication connection, where the core logic unit 5 includes a programmable input end and a core circuit, and the vector memory 2 stores a data format description file of a chip to be tested;
the vector memory 2 is configured to send the data format description file to the core circuit when a preset condition is satisfied;
the core circuit is configured to receive the data format description file and a clock signal and output a test signal synchronous with the period of the clock signal according to self logic;
the core logic unit 5 is configured to receive a programmable signal via a programmable input and to adapt the core circuitry in accordance with the programmable signal.
So configured, the following beneficial effects are produced:
1) when the difference between the new chip to be tested and the original chip to be tested is not large, the new chip to be tested can be adapted by changing the data format description file;
2) when the change of a new tested chip is large or a test task is changed, the core circuit is rewritten through the programmable signal so as to adapt to the new tested chip or the new test task;
3) by receiving a clock signal and generating a test signal synchronized with the period of the clock signal, it is helpful to improve the consistency among a plurality of test modules and eliminate the defect of insufficient time base precision of high-versatility elements.
By the aid of the beneficial effects, the problems that in the prior art, the test function of the integrated circuit test machine is fixed and the universality is not strong are solved.
It should be understood that the data format description file stored in the vector memory 2 can be modified by an external device, and the internal logic of the external device and the communication mode of the vector memory can be set according to the prior art, which is not described in detail herein.
Further, the core logic unit 5 includes an FPGA chip, and the FPGA chip includes the programmable input terminal and the core circuit. The FPGA chip is a product further developed on the basis of programmable devices such as PAL, GAL and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. The technology of the FPGA chip is mature and is suitable for being used as a main component of the core logic unit 5. Of course, the solution of implementing the core logic unit 5 by using other technologies based on the programmable idea should also be considered as the protection scope of the claims of the present application.
The solution in this embodiment is not to simply put the FPGA chip into the test assembly 10. In general, a design tool provided by a manufacturer of a general-purpose FPGA chip cannot satisfy the control of a timing precision (SPC) by an integrated circuit tester, because the integrated circuit tester does not seek to optimize one channel performance, but all the channel performances are consistent to be optimal, and only then has the calibration capability, the general-purpose FPGA chip cannot solve the existing problems mentioned in the introduction of the background art. The inventor makes an improvement on the existing FPGA chip and forces all resources (including the test component 10 and other circuits or components on the integrated circuit tester) to be set to a single step by connecting the FPGA chip with the same clock signal, thereby ensuring the consistency of the performance of all resources and achieving the effect that the time base precision is less than 200 ps. The general standard flow of FPGA development is through writing HDL code, and then generating FPGA internal logic circuit by software. Under the standard process, the generated final FPGA internal function logic circuit is generated and optimized by FPGA tool software, the tool software cannot perfectly understand the intention of developers, so that the optimization degree of the actually generated circuit is insufficient, the generated circuit is influenced when modification is carried out each time, the compiling results of partial same modules are different each time, and the condition of insufficient precision is caused. In the invention, the inventor adopts direct manual editing for part of key logic circuits in the FPGA, and the corresponding key circuits are accurately fixed in a mode of solidifying IP, and the optimization degree of the invention is better than that of tool software. This is one of the reasons why the test module can improve the accuracy of the time base.
Preferably, the test component 10 further includes a configuration memory 7, the configuration memory 7 stores a core program and is in communication connection with the programmable input terminal, and the configuration memory 7 is configured to, after the test component 10 is powered on, send a programmable signal to the programmable input terminal according to its core program and drive the core circuit to be rewritten. The test assembly 10 further includes a verification flash memory 8, and the verification flash memory 8 stores some basic information, such as calibration data, version numbers, serial numbers, and the like. The configuration memory 7 may adjust the rewriting process of the core circuit according to the information of the verification flash memory 8. The configuration memory should be able to retain data after power loss to ensure that the entire process is functioning properly. Preferably, the configuration memory can be implemented by a flash memory chip, and the storage speed can be guaranteed while data is kept. The content of the core program can be generated and edited by a corresponding software tool, and the specific implementation manner of the software tool is not the key point of the description of the specification and is not described in detail herein.
Preferably, the test component 10 further includes an algorithm simulation unit 4, the vector memory 2 is in communication connection with the core logic unit 5 through the algorithm simulation unit 4, and the algorithm simulation unit 4 is configured to convert the format of the data format description file into a format that can be analyzed by the core logic unit 5. The algorithm simulation unit 4 is a tool specially used for generating the memory granules to be tested or the memory test algorithm in the chip to be tested, and no additional compiling is needed. With the configuration, the general part of the special control circuit in the prior art is reasonably abstracted, the content required to be rewritten by the core logic unit 5 is reduced, and the reliability of the system is improved.
Preferably, the test assembly 10 further includes a digital signal processing unit 6, and the digital signal processing unit 6 is communicatively connected to the core logic unit 5, and is configured to assist the core logic unit 5 in processing digital signal operations. Although some DSP (digital Signal processing) cores are integrated inside the FPGA chip, the FPGA chip is not powerful enough and cannot be used for a complex DSP algorithm, but the independent DSP chip can support more complex operation and has higher operation efficiency. With this configuration, the processing speed of the test assembly 10 can be increased, and the working efficiency of the integrated circuit tester can be improved.
In an embodiment, the testing component 10 further includes a capture memory 1, and the capture memory 1 is configured to receive and store an output signal of the chip under test. With such a configuration, the stored output signals can be subsequently output to a computer for analysis, thereby obtaining more test results and performing more complex test tasks.
Preferably, the capture memory 1 is in communication connection with the vector memory 2, the vector memory 2 is configured to send the data format description file to the capture memory 1 when a preset condition is met, and the capture memory 1 is configured to perform format conversion on the received output signal of the chip to be tested according to the received data format description file and then store the converted output signal. With the configuration, firstly, invalid or unimportant data can be discarded in advance through format analysis, and the storage space of the capture memory 1 is effectively utilized, so that the burden of a subsequent analysis process can be reduced, and the analysis process is accelerated.
In one embodiment, the test module 10 further comprises a scan memory 3, the scan memory 3 being configured to output a test signal independently of the core logic unit 5. Further, the scan memory 3 includes only one input terminal and one output terminal. The configuration is beneficial to quickly carrying out simple and universal test and accelerating the test process.
Referring to fig. 3, the present embodiment further provides an integrated circuit tester, where the integrated circuit tester includes a test load board and the test component 10, the test component 10 is detachably connected to the test load board, a control end of the test load board is communicatively connected to the core circuit, and the core circuit is communicatively connected to a chip to be tested through a functional circuit on the test load board. In this embodiment, the integrated circuit tester further includes a plug-in card, the plug-in card includes at least two test assemblies 10, and the test assemblies 10 are detachably connected to the test load board through the plug-in card. So configured, the test assembly 10 can be replaced at any time, further increasing the versatility of the integrated circuit tester. The integrated circuit tester has the same effect as the test assembly 10, since it has the advantageous effect of improving the versatility of the integrated circuit tester. Other components and structures of the integrated circuit tester can be configured by those skilled in the art according to the actual prior art, and the configuration principle and other components of the integrated circuit tester are not described in detail here.
In summary, in the test component 10 and the integrated circuit tester provided in this embodiment, the test component 10 includes a core logic unit 5 and a vector memory 2 that are in communication connection, the core logic unit 5 includes a programmable input end and a core circuit, and the vector memory 2 stores a data format description file of a chip to be tested;
the vector memory 2 is configured to send the data format description file to the core circuit when a preset condition is satisfied;
the core circuit is configured to receive the data format description file and a clock signal and output a test signal synchronous with the period of the clock signal according to self logic;
the core logic unit 5 is configured to receive a programmable signal via a programmable input and to adapt the core circuitry in accordance with the programmable signal.
So configured, the following beneficial effects are produced:
1) when the difference between the new chip to be tested and the original chip to be tested is not large, the new chip to be tested can be adapted by changing the data format description file;
2) when the change of a new tested chip is large or a test task is changed, the core circuit is rewritten through the programmable signal so as to adapt to the new tested chip or the new test task;
3) by receiving a clock signal and generating a test signal synchronized with the period of the clock signal, it is helpful to improve the consistency among a plurality of test modules and eliminate the defect of insufficient time base precision of high-versatility elements.
By the aid of the beneficial effects, the problems that in the prior art, the test function of the integrated circuit test machine is fixed and the universality is not strong are solved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and it is not intended that any changes and modifications that can be made by one skilled in the art based on the above disclosure within the scope of the present invention are included in the claims.
Claims (10)
1. A test component is used for an integrated circuit tester and is characterized by comprising a core logic unit and a vector memory which are in communication connection, wherein the core logic unit comprises a programmable input end and a core circuit, and the vector memory stores a data format description file of a chip to be tested;
the vector memory is configured to send the data format description file to the core circuit when a preset condition is met;
the core circuit is configured to receive the data format description file and a clock signal and output a test signal synchronous with the period of the clock signal according to self logic;
the core logic unit is configured to receive a programmable signal via a programmable input and to rewrite the core circuitry in accordance with the programmable signal.
2. The test assembly of claim 1, wherein the core logic unit comprises an FPGA chip, the FPGA chip comprising the programmable input and the core circuitry.
3. The test assembly of claim 1, further comprising a configuration memory, wherein the configuration memory stores a core program and is communicatively coupled to the programmable input, and wherein the configuration memory is configured to send a programmable signal to the programmable input according to its core program and to drive the core circuit to be rewritten after the test assembly is powered on.
4. The test assembly of claim 1, further comprising an algorithmic simulation unit, the vector memory communicatively coupled to the core logic unit via the algorithmic simulation unit, the algorithmic simulation unit configured to convert the format of the data format description file into a format that the core logic unit is capable of parsing.
5. The test assembly of claim 1, further comprising a digital signal processing unit communicatively coupled to the core logic unit for assisting the core logic unit in processing digital signal operations.
6. The test module of claim 1, further comprising a capture memory for receiving and storing the output signal of the chip under test.
7. The test assembly of claim 6, wherein the capture memory is communicatively coupled to a vector memory, the vector memory is configured to send the data format description file to the capture memory when a predetermined condition is satisfied, and the capture memory is configured to perform format conversion on the received output signal of the chip under test according to the received data format description file and then store the converted output signal.
8. The test assembly of claim 1, further comprising a scan memory configured to output test signals independent of the core logic unit.
9. The test assembly of claim 8, wherein the scan memory includes only one input and only one output.
10. An integrated circuit tester, comprising a test load board and a test assembly as claimed in any one of claims 1 to 9, wherein the test assembly is detachably connected to the test load board, a control terminal of the test load board is communicatively connected to the core circuit, and the core circuit is communicatively connected to a chip under test through a functional circuit on the test load board.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011018344.7A CN112255527A (en) | 2020-09-24 | 2020-09-24 | Testing component and integrated circuit testing machine |
| TW110117201A TWI803871B (en) | 2020-09-24 | 2021-05-13 | Test element and integrated circuit test equipment |
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| CN202011018344.7A CN112255527A (en) | 2020-09-24 | 2020-09-24 | Testing component and integrated circuit testing machine |
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| CN115792584B (en) * | 2023-02-07 | 2023-06-23 | 青岛青软晶尊微电子科技有限公司 | Integrated circuit experimental method and device based on big data |
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| KR100916762B1 (en) * | 2007-12-10 | 2009-09-14 | 주식회사 아이티엔티 | semiconductor device test system |
| US7848899B2 (en) * | 2008-06-09 | 2010-12-07 | Kingtiger Technology (Canada) Inc. | Systems and methods for testing integrated circuit devices |
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| CN1610834A (en) * | 2001-07-05 | 2005-04-27 | 英特泰克公司 | Method and apparatus for optimized parallel testing and access of electronic circuits |
| TW200912936A (en) * | 2007-09-07 | 2009-03-16 | Asix Electronics Corp Ltd | Programmable integrated circuit with built-in self testing circuit and its test method |
| CN102540060A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Digital integrated circuit chip testing system |
| CN108054904A (en) * | 2017-12-20 | 2018-05-18 | 深圳市同安德方科技有限公司 | A kind of transducer power unit firmware online updating method |
| CN109346119A (en) * | 2018-08-30 | 2019-02-15 | 武汉精鸿电子技术有限公司 | A kind of semiconductor memory burn-in test core board |
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| TW202212844A (en) | 2022-04-01 |
| TWI803871B (en) | 2023-06-01 |
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