JPH05107305A - Testing method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce measurement time so as to reduce a cost by precedingly measuring the item for which required measurement time is short and which is strongly related with measurement items, and selectively measuring specific items based on them. CONSTITUTION:The characteristics of individual semiconductor integrated circuits formed on a semiconductor wafer are measured, and the acceptance-or- rejection of these circuits are judged based on the result. In this case, the item for which measurement time is relatively short and the measurement result is strongly related to acceptance rate of other measurement items are precedingly measured. Specific items among the items except the measurement- finished items are selectively measured based on the measured result. Optimum measurement items in compliance with the circuit characteristics are selectively measured among all measurement items for individual semiconductor integrated circuits, the time required for the test of each semiconductor integrated circuit can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test method for determining whether each individual semiconductor integrated circuit formed on a semiconductor wafer can fulfill its intended function.

[0002]

2. Description of the Related Art In the production of ICs (semiconductor integrated circuits), when ICs are formed on a semiconductor wafer,
According to a predetermined test program, an electrical characteristic test is performed to determine whether each IC can perform its intended function. For example, MOS (metal oxide semiconductor transistor)
In the case of IC, the pass / fail judgment of each IC is made according to the test program whose flow is illustrated in FIG.
First, in step S1, an open / short check is performed on each terminal (bonding pad in this case) on the IC chip. In this open / short check, a continuity test is performed between each terminal (bonding pad in this case) and the semiconductor substrate, and based on the result of this continuity test, each terminal and the input circuit connected to it. The presence or absence of disconnection of the wiring between the input terminal or the output terminal of the output circuit is determined, and the presence or absence of a short circuit between each terminal and another wiring or the semiconductor substrate is determined. If the result of this open / short check is unsuccessful, the IC chip is judged to be a defective product and the test is terminated. If it is acceptable, the process proceeds to step S2. Next, in step S2, a functional test of the IC chip is performed by setting the power supply voltage higher than the upper limit of the guaranteed power supply voltage range by a predetermined voltage value. In this functional test, an input signal having a predetermined time-series pattern is supplied to each input terminal of the IC chip, and it is determined whether a normal output signal is obtained from each output terminal. If the result of this function test is unacceptable, it is determined that the IC chip is a defective product, and the test is terminated. If the result is acceptable, the process proceeds to step S3. Next, in step S3, the same function test as that performed in step S2 is performed by setting the power supply voltage lower by the predetermined voltage value than the lower limit of the guaranteed power supply voltage range. If the result of this function test is unacceptable, it is determined that the IC chip is a defective product, and the test is terminated.
Go to 4. Next, in step S4, an output terminal current test is performed. In this output terminal current test, a high level output current IOH flowing from the output terminal to the IC tester side when each output terminal is at the high level, and a high level output current IOH flowing from the IC tester side to the output terminal when each output terminal is at the low level It is determined whether the low level output current IOL and the low level output current IOL both satisfy the standard value. And step S
If the measurement result in 4 is unacceptable, it is determined that the IC chip is a defective product, and the test is terminated. If the result is acceptable, the process proceeds to step S5. Next, proceeding to step S5, a predetermined voltage is applied to each input terminal, and it is determined whether or not the value of the leak current at each input terminal is equal to or less than the predetermined value. If this judgment result is unacceptable, I
When C is judged to be a defective product, the test is ended, and when it is acceptable, the IC is judged to be a good product and the test is ended.

[0003]

By the way, the test carried out at the stage when ICs are formed on a semiconductor wafer targets all of a large number of IC chips formed on the wafer. Further, this test is performed for the purpose of removing a large number of defective IC chips in advance so that they are not put into the assembly process which is the next process.
Therefore, it is preferable that the measurement time for testing one IC is as short as possible. However, the conventional test method described above has a problem in that many measurement items are performed until one good IC chip is determined to be a good product, and the measurement time per IC is long. Especially when the circuit configuration of the IC is large-scale or complicated, the time required for the functional test becomes long and the total measurement time becomes extremely long.
Moreover, since each measurement item is performed in a fixed order, the time loss is large when the final measurement item fails. As described above, the time required to test the IC is long, which causes an increase in manufacturing cost. The present invention has been made in view of the above-mentioned circumstances.
It is an object of the present invention to provide a semiconductor integrated circuit test method that requires a short measurement time for each unit.

[0004]

SUMMARY OF THE INVENTION The present invention is a semiconductor integrated circuit which measures various electrical characteristics of individual semiconductor integrated circuits formed on a semiconductor wafer and judges pass / fail of the semiconductor integrated circuit based on the measurement results. In the circuit test method, the measurement time is relatively short, and the measurement item with a strong correlation between the measurement result and the pass rate of other measurement items is performed in advance, and the measurement result has already been performed. It is characterized in that a specific measurement item is selected and executed from the measurement items other than the measurement item of.

[0005]

According to the above test method, for each semiconductor integrated circuit, the optimum measurement item according to the characteristics of the semiconductor integrated circuit is selected from all the measurement items and executed. Therefore, the time required for the test per semiconductor integrated circuit can be shortened.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a MOSIC test program to which a test method according to an embodiment of the present invention is applied. First, in step S11, an open / short check is performed. If the measurement result is unacceptable, the IC chip is determined to be a defective product and the test is terminated. If the result is acceptable, the process proceeds to step S12. Next, when proceeding to step S12, the high level output current IOH and the low level output current IOL are output for each output terminal.
To measure. If this measurement result is unacceptable, I
The test is terminated by determining that the C chip is defective, and if the test is acceptable, the process proceeds to step S13. Then step S1
In step 3, the values of IOH and IOL measured in step S12 are compared with the predetermined value A. And IO
When H and IOL are A or more, it progresses to step S14, and when it is a value lower than A, it progresses to step S16. In step S14, the function test is performed by setting the power supply voltage higher than the guaranteed power supply voltage range by a predetermined voltage value. If the result of this function test is unacceptable, it is determined that the IC chip is a defective product, and the test is terminated. If the result is acceptable, the process proceeds to step S15. Next, in step S15, the leak current of each input terminal is measured. If this measurement result is unacceptable, the IC is judged to be a defective product and the test is ended, and if it is acceptable, the IC is judged to be a non-defective product and the test is ended. On the other hand, when the process proceeds from step S13 to step S16, the functional test is performed by setting the power supply voltage lower than the guaranteed power supply voltage range by the predetermined voltage value.
If the result of this function test is unacceptable, it is determined that the IC chip is a defective product, and the test is terminated. If the result is acceptable, the process proceeds to step S16. Next, in step S16, the leak current of each input terminal is measured. If this measurement result is unacceptable, the IC is judged to be a defective product and the test is ended, and if it is acceptable, the IC is judged to be a non-defective product and the test is ended.

As described above, in step S13, branching is performed based on the current values of the output currents IOL and IOH, and only one of a functional test with a high power supply voltage and a functional test with a low power supply voltage is performed. Here, the reason why one of the functional tests can be omitted will be described. When the measured output current value is high, it is predicted that the load driving capability of the transistor inside the IC is large and the propagation delay time of each gate inside the IC is short. In such a case, a functional failure is likely to occur due to the increased operating speed of the internal gate. On the other hand, MO
In the case of SIC, the higher the power supply voltage, the higher the load driving capability of each transistor. Therefore, when the output current value is high, the functional failure is likely to occur due to the increase in the operating speed when the power supply voltage value is high, and the IC
Lowers the upper limit of the power supply voltage range in which the can function normally. Therefore, when the output current value is large, only the function test with the high power supply voltage setting is performed. On the other hand, when the measured output current value is low, the load driving capability of the transistor inside the IC is small, and the functional failure due to the slow operation speed of the internal gate is likely to occur. Therefore, when the output current value is low, a functional failure is likely to occur due to the slow operation speed when the power supply voltage value is lowered, and the lower limit of the power supply voltage range in which the IC can normally function is high. Become. Therefore, when the output current value is low, only the function test with the low power supply voltage setting is performed. The reference value A for performing the determination branch in step S13 is determined based on the evaluation result by evaluating the correlation between the output current value and the operable power supply voltage range for various wafers having different manufacturing conditions. ..

[0008]

As described above, according to the present invention, various electrical characteristics of individual semiconductor integrated circuits formed on a semiconductor wafer are measured, and whether the semiconductor integrated circuit is passed or rejected is determined based on each measurement result. In the semiconductor integrated circuit test method to determine, the measurement time is relatively short, and a measurement item having a strong correlation with the relevant measurement result and the pass rate in other measurement items is performed first, and based on the measurement result. Since a specific measurement item is selected from the measurement items other than the already-executed measurement item and the measurement is performed, the measurement time for testing one semiconductor integrated circuit is shortened and the manufacturing cost is reduced. Is obtained.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a method for testing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a conventional test method.

[Explanation of symbols]

S13: Step of deciding the next measurement item to be performed based on the output current value

Claims (1)

[Claims] 1. A method for testing a semiconductor integrated circuit, which comprises measuring various electrical characteristics of an individual semiconductor integrated circuit formed on a semiconductor wafer, and judging whether the semiconductor integrated circuit is acceptable or unacceptable based on each measurement result. The measurement time is short, and the measurement item having a strong correlation with the relevant measurement result and the pass rate in other measurement items is performed first, and based on the measurement result, the measurement items other than the already performed measurement items A test method for a semiconductor integrated circuit, which is characterized in that a specific measurement item is selected and executed.