JPH06209078A - Circuit for evaluating characteristic of element - Google Patents

Abstract

PURPOSE:To provide a circuit for evaluating characteristics of elements from which numerous data can be easily obtained and can easily perform tests when the circuit is used for long-term reliability evaluating tests. CONSTITUTION:N-channel transistors 1a and P-channel transistors 1b arranged in a matrix-like state on a semiconductor substrate are connected to each other through line-wiring L0-L9 respectively having line-wiring pads G0-G9 at their terminating sections and row-wires NL0-NL9 and PL0-PL9 respectively having row-wiring pads DN0-DN9 and DP0-DP9 at their terminating ends and protective circuits 2 are respectively provided immediately after the pads.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device characteristic evaluation circuit.

[0002]

2. Description of the Related Art Currently, it is used for initial evaluation and long-term reliability evaluation of element characteristics in the development stage of a semiconductor device, and for TEG (Test Eremen) used as lot monitoring in the mass production stage.
t Group). This is a transistor with a single unit made by the process that is actually used for prototypes and mass-produced products. By using these, individual electrical characteristic evaluations, long-term reliability evaluation tests such as bias tests, etc. And so on.

[0003]

In the method using a transistor having a single structure as described above, it takes a lot of time and labor to make the number of data uniform because each measurement is performed individually. In addition, when performing a long-term reliability evaluation test at the level of a single transistor, variations in data frequently occur due to external factors such as package handling.

An object of the present invention is to provide a device characteristic evaluation circuit which can easily obtain a large number of data and which can be easily tested when used in a long-term reliability evaluation test.

[0005]

A plurality of evaluation elements arranged in a matrix on a semiconductor substrate, a row wiring for connecting the plurality of evaluation elements for each row, and a plurality of the evaluation elements are provided. The above object is achieved by providing column wirings connected for each column, row wiring pads arranged at the end portions of the row wirings, and column wiring pads arranged at the end portions of the column wirings.

It is preferable that a protection circuit for protecting the evaluation element is provided immediately after the row wiring pad and the column wiring pad, and the evaluation element is preferably a transistor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit for evaluating characteristics of a device according to an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, which is an electric circuit diagram showing the configuration of the present example, the present example uses 100 NchMOS transistors 1a and 10 as evaluation elements.
Zero PchMOS transistors 1b are used. These Nch transistor 1a and Pch transistor 1b are provided on a silicon substrate, and row wirings L0 to L9 are provided.
And column wirings NL0 to NL9 and column wirings PL0 to PL9.
And are wired in a matrix. Note that FIG.
In the above, the Nch transistor 1a group and the Pch transistor 1b group are shown separately in two regions.
Nch transistor 1a as well as MOS transistor
And the Pch transistor 1b may be provided adjacent to each other.
Further, Source and Sub of Nch transistor 1a and Pch transistor 1b are VDD and VSS, respectively.
Properly connected to.

Each of the row wirings L0 to L9 has 10 Nchs.
Transistor 1a and 10 Pch transistors 1
The row wiring pads G0 to G9 are provided at the end portions, respectively, which are connected to the gate b. Also, the column wirings NL0 to N
L9 is 10 Nc each having different row wirings L0 to L9.
The column wiring pads DN0 to DN9 are connected to the drain of the h-transistor 1a and are provided at the terminal end portions, respectively.
Similarly, the column wirings PL0 to PL9 are respectively row wirings L0 to L9.
Are connected to the drains of ten Pch transistors 1b having different widths, and the column wiring pads D are respectively provided at the end portions.
P0 to DP9 are provided. During device evaluation, the row wiring pads G0 to G9 are normally used as input pads, and the column wiring pads DN0 to DN9 and the column wiring pad DP0 are used.
~ DP9 is used as an output pad. Further, during the long-term reliability evaluation test, the row wiring pads G0 to G9, the column wiring pads DN0 to DN9, and the column wiring pads DP0 to
A predetermined bias voltage is applied to DP9. Generally, the chip size is determined by the number of input / output pads, but in this circuit, the row wiring pads G0 to G9 and the column wiring pad DN0 are used.
.About.DN9 and column wiring pads DP0 to DP9, two power supply pads (not shown) are added to have a total of 32 pads, and the chip size of this circuit is about 1.7 mm square. Further, immediately after the row wiring pads G0 to G9, the column wiring pads DN0 to DN9 and the column wiring pads DP0 to DP9, a protection diode 2 as a protection circuit for protecting the Nch transistor 1a and the Pch transistor 1b is provided.

The chip of the element evaluation circuit configured as described above is bonded to, for example, a ceramic package. Here, for example, by applying a voltage to the row wiring pad G0 and obtaining the output of the row wiring pad DN0, N connected to the intersection of the row wiring L0 and the column wiring LN0 is obtained.
Data for characteristic evaluation of the ch transistor 1a can be obtained. Similarly, it is possible to obtain data of 200 transistors including the Nch transistor 1a and the Pch transistor 1b in one package. Further, by mounting these on a predetermined evaluation board and simultaneously testing several tens of packages, characteristic evaluation data of thousands to tens of thousands of transistors can be obtained, and reliability of the test data is improved. Also, the row wiring pad G0
To G9, column wiring pads DN0 to DN9, and column wiring pads DP0 to DP9, by selectively probing a plurality of pads, a circuit such as an inverter can be formed in this circuit to evaluate various circuit characteristics. It is also possible.

Further, in order to provide the characteristic evaluation at the process development stage, it is possible to form transistors having different gate lengths of 1.0 μm and 0.8 μm in a plurality of chips. For these chips, for example, if a stepper is used, several tens of kinds of chips can be formed in one shot. Here, rules other than the evaluation items are allowed to have a margin as much as possible, so that a transistor group in which data variation due to external factors other than process factors is extremely small can be easily configured and evaluated.

Also in the long-term reliability test, when a protection diode using a PN junction is used, the upper limit temperature is 1
A bias test at about 50 ° C is possible.

According to the configuration of this example, the number of data of evaluation elements such as transistors is increased, and it is easy to support an automatic measurement system. Therefore, the labor of element evaluation is reduced and the reliability of data is improved. As a result, process development can be shortened.

In the above example, M is used as the evaluation element.
Although the OS type or CMOS type transistor is used, the present invention is not limited to this, and a bipolar type transistor can also achieve the same effect. Further, it need not be an active element, and may be, for example, a capacitor. Further, in the above example, the number of evaluation elements is set to 200, but the number is not limited to this and can be changed.

[0014]

According to the present invention, the evaluation element provided on the semiconductor substrate is wired in a matrix by the row wiring and the column wiring having the pad at the terminal end. Therefore, it is possible to easily provide a large number of data, and it is possible to provide a device characteristic evaluation circuit that can be easily tested when used in a long-term reliability evaluation test.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing the configuration of a circuit for evaluating characteristics of an element according to an example of the present invention.

[Explanation of symbols]

 1a Evaluation element 1b Evaluation element L0 to L9 row wiring NL0 to NL9 column wiring PL0 to PL9 column wiring G0 to G9 row wiring pad DN0 to DN9 column wiring pad DP0 to DP9 column wiring pad 2 protection circuit

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // H01L 21/66 Y 7630-4M

Claims (3)

[Claims] 1. A plurality of evaluation elements provided on a semiconductor substrate and wired in a matrix, row wirings for connecting the plurality of evaluation elements for each row, and the plurality of evaluation elements for each column. A circuit for evaluating characteristics of an element comprising a column wiring to be connected, a row wiring pad arranged at an end of the row wiring, and a column wiring pad arranged at an end of the column wiring. 2. The circuit for evaluating characteristics of an element according to claim 1, wherein a protection circuit for protecting the evaluation element is provided immediately after the row wiring pad and the column wiring pad. 3. The element characteristic evaluation circuit according to claim 1, wherein the evaluation element is a transistor.