JPS5925258A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To select ICs of different kinds formed onto the same one semiconductor wafer by setting up a first circuit and a second circuit having a function different from one of said circuit to the same substrate. CONSTITUTION:Input signals are inputted to input gates G1, G2, G3, and the information contents of the circuit S constituted by a gate array or an ROM or the like are outputted through amplifying gates A1, A2, A3. Zener diodes ZD, gates G4, G5, memories M and amplifying circuits A3, A4, A5 are added and formed to the dead regions in each IC chip. When voltage is the input signal voltage or more of normal operation, the diode ZD is turned ON from OFF, the gates G4, G5 are operated, and the informations of the memory M are outputted from normal output terminals O1, O2, O3 through the amplifying gates A3, A4, A5. Operation by the normal input signals of the amplifying gates A1, A2, A3 is not conducted by an output from the gate G4 at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and particularly relates to a method for manufacturing a large number of different types of semiconductor integrated circuit devices on the same semiconductor wafer (hereinafter referred to as wafer). The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as an IC) to be provided and manufactured, and a manufacturing method thereof.

(b) Prior art and problems Conventionally, in order to manufacture transistors or ICs, a large number of transistors or ICs are formed on a wafer, divided into square chips, and each chip is then packaged in a semiconductor container. The transistor or IC is formed by encapsulating the material into a transistor or an IC.

In addition, a large number of chips formed on one wafer are all of the same type (hereinafter referred to as a type), and the cost has been reduced by automation through mass production. However, with the advancement of IC technology, LSI and VLS
It has become extremely highly integrated, and its character as an electronic circuit rather than as an electronic component has been strongly expressed. For this reason, while the production quantity is decreasing, the variety is increasing, and a shift is being made to high-mix, low-volume production.

In this way, when it comes to high-mix low-volume production, even if a large number of ICs of the same type are formed on the same web and assembly and testing are performed automatically, the production yield will decrease due to the small production volume. On the contrary, the cost will increase.

This decrease in yield is closely related to the stability of work, and is caused by the lack of familiarity of workers and fluctuations in the conditions of production machines. show. In other words, the band-like shape in the figure shows the width of the yield variation; when the production quantity is small, the yield is low and the variation width is wide, but as the production quantity increases, the yield improves. The figure above shows that the variation width is also reduced.

In particular, recently, logic circuits and memory circuits used in electronic computers, etc., have become extremely highly integrated and miniaturized due to the need to increase response speed.
(small IC) and MSI (medium-sized IC) were mounted on a circuit board, and many of them were stacked to form an electronic circuit.
Currently, several circuit boards are combined into one LSI (large integrated circuit).
C) Or as a VLSI (Very LSI), it is housed in various packages (containers) according to user requirements, and as a result, electronic devices such as computer central processing units and terminals have become extremely small and high-performance. It's coming.

If such LSIs and VLSIs are produced in a wide variety of small quantities as described above, in addition to high costs due to lower production yields, LSIs that are in short supply will be reproduced due to yield fluctuations, further accelerating cost increases. .

For example, the LSIs that make up an electronic device are A, B, C, D,
Assume that one of each of the five varieties of E is required.

Currently, in order to produce LSIs for 100 electronic devices, 10 wafers are required for each type, as shown in Figure 2.
By processing 80 chips for A variety, 280 chips for B variety, 100 chips for C variety, 80 chips for D variety, and 20 chips for E variety, the B variety has a surplus of 180 chips. arise, E
There is a shortage of 80 varieties. However, for the E type, wafer processing must be performed again to replenish the missing quantity, and the cost of the E type LSI doubles. Furthermore, although there was a surplus of B-type LSIs, more than 100 of the electronic devices were unnecessary and had to be disposed of, resulting in a corresponding loss of materials and processing man-hours. FIG. 2 is a diagram that makes this easier to understand, and chip 2 is shown in a diagram corresponding to 20 actual IC chips.

(c) Purpose of the Invention The present invention proposes an IC and its manufacturing method for reducing the production quantity of one type and eliminating high costs due to fluctuations in production yield.

(d) Structure of the Invention The object of the invention is to provide a first circuit having a signal input terminal and an output terminal, which outputs a predetermined output to the output terminal according to the state of the first input signal; and an output terminal, and inhibits the operation of the first circuit when a second input signal is applied to the signal input terminal, and outputs a type signal indicating the type of the first circuit to the output terminal. This can be achieved by an IC having a second circuit and a manufacturing method thereof.

(e) Embodiments of the invention Hereinafter, embodiments will be described in detail with reference to the drawings. Figure 3 shows an example of a logic circuit among functional circuits, which is an AND circuit for a large number of input and output signals.As in this example, an IC has a repeating configuration of the same circuit pattern, and has several hundred or more gates. The manufacturing process is the same even for LSIs (Large Scale Integrated Circuits) that are assembled in several thousand pieces, but the mask pattern used is different when it comes to ICs of the same type, such as bipolar transistors, and when it comes to logic circuits consisting of only active elements of bipolar transistors. However, the manufacturing process of wafer process is almost the same even if the product types are different.

The present invention focuses on this point and forms all or a plurality of LSIs (ICs) constituting one type of electronic device on one wafer. In this way, although the slightly different sizes and wafer process temperatures for each product may need to be slightly changed to make them the same in design, the unification will result in higher volume production and improved yields. Stability is measured.

Furthermore, with such a wafer configuration, variations in production yield due to process variations will be common to all types of electronic equipment, and surplus quantities will be generated, making it possible to reduce the conventional loss of disposal.

However, the problem lies in the selection method; after the wafer process is completed and the ICs are completed, they must be selected in a wafer probe test or a final test after assembly. In the wafer probe test, it is necessary to perform tests for each type of wafer on the same wafer, so it is necessary to identify the type during the test.

For example, if five types A to E are placed on one wafer, resistive elements with different resistance values are installed in the free space of each IC on the wafer or in the dicing line area between the ICs, and Two extra pads are provided to contact the probe during the probe test. Furthermore, the resistance value can be changed by changing the width of the resistor, for example, A, B, C,
Types D and E are 10KΩ, 20KΩ, and 30KΩ, respectively.
, 40KΩ, and 50KΩ. After sorting and probe testing in this way, if resistance is formed in the timing band, it is destroyed by dicing.
It disappears. In addition, if it is formed in an empty area within the IC, it is not destroyed but will not be used for selection in the final test, so no bonding is necessary.

After selecting the type in this way, the type information is transmitted to a test electronic measuring machine, and a probe test unique to the type is performed based on input from the measuring machine to determine the quality of the IC. When ICs are judged to be good or bad and at the same time they are sorted into chips according to type, the production method shown in FIG. 4 is used.

That is, FIG. 4 is a diagram in contrast to FIG. 2 of the conventional production method, in which each type of A, B, C, D, and E provided on a large number of wafers 1 is immediately placed on each chip 2 after the probe test. It is meant to be classified. In this way, the generation of surplus products and the loss of man-hours can be minimized.

Another method is to use a wafer probe test to determine the quality of the ICs as described above, remove defective products, and then bond and seal the ICs in a semiconductor container as they are mixed without sorting by type. FIG. 6 shows the selective production method after completing such an LSI3.

In this case, the selection method for each product in the final test is important, and if there is an extra empty terminal on the external terminal of the semiconductor container, the pads at both ends of the selection resistor element explained above and the external terminal can be bonded and sorted.

However, if there are no empty terminals, or if the connection between the selection resistance element and the empty terminals is undesirable, information must be obtained from the existing terminals to be used for identification. FIG. 6 shows an embodiment in which such a used terminal is shared and a specific circuit from which selection information is output is provided.

FIG. 6 shows an example of a logic circuit diagram. Conventionally, input signals are input to input gates G1, G2, and G3, and the information content of a circuit S consisting of a gate array or ROM (read-only memory), etc. It is assumed that this is a general gate circuit that outputs through amplifying gates A1, A2, and A3, and operates at a threshold pressure (Vrn) of 1.4V and a power supply pressure (Vcc) of 5V.

In the present invention, such a circuit surrounded by a dotted line in the gate circuit diagram E is added. That is, for the Zener diode ZD, gates G4 and G5, and the memory, amplifying circuits A3, A4, and A5 are additionally formed in empty areas in each IC chip, and the operating voltage of the Zener diode ZD is set to 7V or higher.

In this way, when an input signal voltage of 10 V, for example, which is different from the input signal voltage of 3 V or less for normal operation, is input from the conventional input terminal I1, ZD changes from "OFF" to "
ON", gates G4 and G5 operate, and the information in memory M passes through amplified gates A3, A4, A5 and is output from normal output terminals O1, O2, O3. At this time, the output of gate O4 Therefore, the circuit configuration is such that the amplifying gates A1, A2, and A3 do not operate according to normal input signals, and therefore, when a high input signal voltage of 10 V is applied, normal gate operations are not performed. On the other hand, when the input signal is below 5V, the Zener diode ZD does not work in the additional circuit according to the present invention, and the information in the memory M is not outputted from the output terminals O1, O2, and O3.

In the embodiment shown in FIG. 6 above, since type selection information can be obtained from three output terminals, 23
= 8 varieties can be selected.

In other words, if eight or fewer types are provided on the same semiconductor wafer, even if a large number of normal input terminals and output terminals are provided, only one input terminal and three output terminals can be used in common. That's fine. Moreover, if only four types are to be selected, it is sufficient to share two output terminals.

Next, FIG. 7 is a detailed diagram of a circuit group showing in more detail the gate circuit diagram of FIG. 6 as an embodiment of the present invention. First, to explain the conventional input signal operation with reference to the diagram, when an input signal "L" lower than VTH is input from the input terminal I1, the gate U1 converts into a TTL inverter consisting of three transistors T1, T2, and T3. Therefore, the inverted signal “H”
outputs, and conversely, an input signal higher than VTH from I1 “
When the signal "L" is input, the output signal becomes "L". On the other hand, the gate A1 is a gate that only amplifies the signal, and as information of the gate circuit S, when the signal "L" is input, the output signal "L" is output from the output terminal O1. " is output, but at this time, the signal "H", that is, a high voltage is applied to the diodes D1 and D2 in the gate A1, and the transistors T6 and T7 operate normally, and the transistor T8 The signal "H" or "L" input to T4 is output as is.

However, when the signal "L", that is, low power is input to the diodes D1 and D2, the transistors T7 and T8 operate at high impedance, that is, the output becomes a three-state state, and the signal input to the transistor T4 is output to the output terminal O1.
There is no output from. This embodiment has a circuit configuration that utilizes this.

Next, to explain the output of the type classification signal, when 10V, which is a higher voltage than the normal input signal (3V or less), is applied to the input terminal I1, the Zener diode ZD becomes conductive.
TTL gates G4 and G6 operate simultaneously with gate G1. Since gate G4 is an inverter, diode Z
If D is conductive and a high voltage, that is, a signal “H” is input, the signal “
The signal "L" from the gate G1 goes into the diodes D1 and D2 of the gate G1, and as mentioned above, the output of the gate A1 becomes high impedance and is not output.On the other hand, the signal "L" from the gate G4 goes to the next stage. Since it is also an inverter, a signal "H", that is, a high voltage, is applied to the diodes D1 and D2 of the amplifying gate A4, and the high impedance output state is released, and the information in the memory M (implemented) is input to the gate G8. In the example figure, "H") is outputted from the output terminal O1.These are identification signals, and they are similarly outputted from the output terminal O2.The gates G3 and A3 are not shown in FIG.

Although the above is an example, the present invention is not limited to this circuit configuration.In short, this is an example of a circuit that proves that it is possible to select each type by commonly using terminals. be. In addition, even if an extra circuit part is added in this way, the circuit is formed with a fine pattern, and LSI circuits consist of several hundred to several thousand gates, but only a few gates and a small memory can be used. Because it is natural, high density is not hindered. Also, LSI
If there is an empty terminal, a specific identification element or circuit can be connected to the empty terminal, and the product type can be identified using an input signal different from the normal operation input signal, as in the above example.

(f) Effects of the Invention As can be seen from the above explanation, the present invention allows ICs of different types (different types) to be formed on one and the same semiconductor wafer, and the types can also be identified in tests such as wafer probe tests or final tests. The present invention is an IC and its manufacturing method, and is a production method suitable for LSI and VLSI, which are becoming highly integrated and diversified.According to the present invention, production yields are improved and costs are reduced. ,,It is extremely effective in stabilizing quality, and I
This will greatly contribute to the generalization of C.

[Brief explanation of the drawing]

Figure 1 is a diagram of the relationship between production yield and production quantity, Figure 2 is a diagram of a conventional production system, Figure 3 is a diagram of an example of a logic circuit, and Figures 4 and 5 are a production system according to the present invention. The schematic diagrams of FIGS. 6 and 7 are diagrams of example logic circuits including specific circuits according to the present invention. In the figure, 1 is a semiconductor wafer, 2 is a chip, 3 is an LSI,
A, B, C, D, E are types (product types), I1-I3 are input terminals, O1-O3 are output terminals, G1-G5, A1-A5 are gate circuits, ZD, D1, D2 are diodes, T1- T8
indicates a transistor. 2nd (7) Figure 3 Figure 4 Figure 5 Flash A-1c 已-ICノC-1cr)-ICE,
IC Figure 6

Claims (2)

[Claims] (1) a first circuit having a signal input terminal and an output terminal and outputting a predetermined output to the output terminal according to the state of the first input signal; and a first circuit connected between the signal input terminal and the output terminal; a second circuit that, when a second input signal is applied to the signal input terminal, inhibits the operation of the first circuit and outputs a type signal indicating the type of the first circuit to the output terminal; A semiconductor integrated circuit device comprising: (2) A first circuit, a second circuit having a function different from that of the first circuit, and means for accumulating type information of the first and second circuits are formed on the same substrate, and the means 1. A method of manufacturing a semiconductor integrated circuit device, comprising reading type information of a first or second circuit from a semiconductor device and subjecting the first or second circuit to a test corresponding to the first or second circuit.