JP2008171920A - Semiconductor evaluation circuit and evaluation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor evaluation circuit and a semiconductor evaluation method for quickly measuring a large scale semiconductor element in higher accuracy. <P>SOLUTION: The semiconductor evaluation circuit is provided with an evaluation cell array formed by arranging evaluation cells in the row and column directions like a matrix, a first bit line and a second bit line for evaluation cells belonging to each column of the evaluation cell array, a recharge circuit for precharging the first bit line and the second bit line, a detecting means for outputting an output signal by detecting voltage difference between the first bit line and the second bit line, a first switch for connecting and disconnecting the first bit line, precharge circuit, and detecting means, and a second switch for connecting and disconnecting the second bit line, precharge circuit and detecting means. The evaluation cell is constituted with a comparator including a pair-transistor for comparison of an input voltage and the reference voltage to output a comparison result, a third switch for connecting and disconnecting one output terminal of the comparator and the first bit line, and a fourth switch for connecting and disconnecting the other output terminal of the comparator and the second bit line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor evaluation circuit and an evaluation method, and more particularly to a technique for evaluating characteristics of a large number of semiconductor elements.

  When developing micro processes for semiconductors, TEG (Test Element Group) consisting of elements of various dimensions is fabricated in a semiconductor wafer to evaluate and analyze the characteristics of micro elements (transistors, resistor elements, etc.). We are developing devices that can withstand mass production by setting process conditions based on analysis results.

In the process development so far, the optimum process conditions and transistor structure could be set by evaluating and analyzing the characteristics of individual transistors fabricated in the TEG. Can no longer be ignored.
In addition, the phenomenon that the stress applied to the transistor changes depending on the state of the transistor and the characteristics of the transistor change cannot be ignored.

  From such a situation, for example, in a fine process with a processing level of 45 nm, the characteristics of both transistors vary even if they are adjacent transistors. Therefore, a small signal such as SRAM (Static Random Access Memory) is transferred to a pair transistor (adjacent 2 It is predicted that the detection circuit and the amplification circuit that detect with two transistors) have a reduced operating margin or become inoperable.

  In this case, sufficient data cannot be obtained only by evaluating individual transistors. Therefore, the characteristics of a large number of transistors are evaluated, analyzed by statistical processing, and systematic characteristic differences and characteristic differences due to variations are separated. A large-scale TEG that can be analyzed is required.

  Conventionally, as a TEG for performing large-scale element evaluation, for example, there is a DMA (Device Matrix Array) -TEG in which a plurality of transistors are arranged in a matrix as shown in FIG. reference).

  The configuration of the DMA-TEG according to the prior art will be described below with reference to FIG. DUT11 to DUTnm are transistors to be measured. The drains of the transistors under measurement DUT11 to DUT1m are connected to the common drain line D1, and the sources are connected to the common source line S1. The common drain line D1 is connected via a switch SW2 to a common drain force line (Drain Force) to which a drain voltage is supplied. In order to monitor the voltage of the common drain line D1, the drain voltage sense line DS1 is connected to the drain sense line (Drain Sense) via the switch SW1.

  The common source line S1 is connected to a common source power source (Source Force). Further, in order to monitor the voltage of the common source line S1, the common source line S1 is connected to the source sense line (Source Sense) via the switch SW3. The switches SW1 to SW3 are controlled by an output signal of a decoder (not shown).

  With these sets as one set, the transistors to be measured DUTn1 to DUTnm which are the n-th set are provided with the same connection as described above. The gates of the transistors under test DUT11 to DUTn1 are connected to the common gate line G1, and the gates of the transistors under test DUT1m to DUTnm are connected to the common gate line Gm.

Further, either the gate voltage VG1 or the gate non-selection voltage VGX is supplied to the common gate line G1 through the gate selection circuit 100. When the selection signal EN1 becomes high level (selected), the gate voltage VG1 is supplied to the gate line G1, and when the selection signal EN1 becomes low level (non-selected), the gate non-selection voltage VGX is supplied to the gate line G1. The gate non-selection voltage VGX is normally zero volts, but a negative voltage can be set as required.
With the DMA-TEG having such a configuration, the characteristics of m × n transistors DUT11 to DUTnm can be evaluated.

Here, since the m measured transistors DUT11 to DUT1m are connected in parallel to the common drain line D1, if each of the measured transistors has an off-leak current (current that flows without the transistor being completely turned off), Since a leak current flows through the non-selected transistor under measurement, the characteristics of the transistor under measurement to be measured cannot be accurately evaluated. In this case, for example, the gate non-selection voltage VGX is set to about −0.2 V so as to suppress the off-leak current.
FIG. 1B is a circuit diagram of the switches SW1 to SW3.
Yoshiyuki Shimizu, Mitsuo Nakamura, Toshimasa Matsuoka, and Kenji Taniguchi, `` Test structure for precise statistical characteristics measurement of MOSFETs, '' IEEE 2002 Int. Conference on Microelectronic Test Structure (ICMTS 2002), pp. 49-54, April 2002

  However, according to the DMA-TEG according to the above-described prior art, when a large-scale DMA-TEG (for example, m = n = 1024, that is, a TEG capable of evaluating 1M transistors) is configured, the measurement time is very long. There was a problem of becoming.

  For example, when the threshold value is obtained by measuring the static characteristics of a transistor, the drain voltage Vd is 0 point to 0 to 2.0 V, even if the measurement point is rough, and the gate voltage Vg is 0 point to 0 to 2.0 V. Measurement of 20 points is required in 0.1V step.

  In the measurement of the static characteristics, since the current flowing through the transistor is measured by a tester, the measurement time is longer than that in the case of measuring the voltage. In this case, if 1 msec is required to measure one point of the transistor current by the tester, for example, it is necessary to measure 20 × 20 = 400 points for one transistor. × 400 × 1M = 400000 sec (about 111 hours) is required. Therefore, there is a problem that it is not easy to obtain a large amount of measurement data. Alternatively, there is a problem that it is necessary to use a very expensive and high-performance tester that can measure at high speed.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor evaluation circuit and an evaluation method capable of measuring a large-scale semiconductor element with high accuracy and high speed.

The present invention has been made to solve the above problems, and a semiconductor evaluation circuit according to the present invention is a semiconductor evaluation circuit for evaluating transistor characteristics, in which evaluation cells are arranged in a matrix in the row and column directions. An evaluation cell array of n rows and m columns (n and m are positive integers) arranged, m first bit lines for the evaluation cells belonging to each column of the evaluation cell array, and each column of the evaluation cell array The m second bit lines for the evaluation cell belonging to the above, a precharge circuit for precharging the first bit line and the corresponding second bit line, and the first bit line and the corresponding bit line Detecting means for detecting a voltage difference from the second bit line and outputting an output signal; a first switch for connecting and releasing the first bit line; the precharge circuit and the detecting means; and the second bit. Line and the A second switch for connecting and releasing the charge circuit and the detection means, and the evaluation cell includes a pair transistor for comparing the magnitude relationship between the input voltage and the reference voltage, and the comparison result from the two output terminals Connecting the output terminal of the comparator and the first bit line to the first bit line, connecting the third switch to open, and connecting the other output terminal of the comparator and the second bit line, A fourth switch that opens, and the semiconductor evaluation circuit includes a control unit that controls the first switch to the fourth switch, the precharge circuit, the comparator, the input voltage, and the reference voltage. It is characterized by providing.
In the present invention, a comparator is configured with the transistor to be evaluated as a pair transistor, and the third switch and the fourth switch of the evaluation cell to which the pair transistor to be evaluated belongs, and the first switch and the second switch of the column to which the evaluation cell belongs. And closed. Then, an input voltage and a reference voltage are input to the comparator, the comparator is deactivated, and the first bit line and the second bit line of the column to which the pair transistor to be evaluated belongs are precharged by the precharge circuit. .
Since the comparator is activated and the output voltage of the comparator is detected by the detection means, the difference between the threshold values of the pair transistors can be obtained. In addition, since a plurality of the comparators are arranged in a matrix, by performing the above evaluation on each pair transistor in the evaluation cell array, it is possible to obtain a distribution of threshold differences of each pair transistor. Since voltage measurement can be performed faster than current measurement, a semiconductor evaluation circuit capable of measuring a large-scale semiconductor element at high speed and with high accuracy can be realized.

  In the semiconductor evaluation circuit, the comparator includes a pair transistor including a first transistor and a second transistor in which sources are connected to each other, an input voltage is input to one gate, and a reference voltage is input to the other gate. And a current source connected between the source of the pair transistor and the ground.

In the semiconductor evaluation circuit, the comparator includes a third transistor in which a source is connected to a drain of the first transistor, a drain is connected to the third switch, and a constant voltage is applied to a gate; and the second transistor And a fourth transistor having a drain connected to the fourth switch, a drain connected to the fourth switch, and the constant voltage applied to the gate.
According to the present invention, the noise generated by the fourth switch from the first switch is not easily transmitted to the first transistor and the second transistor due to the impedance of the third transistor and the fourth transistor, so that the evaluation can be performed with high accuracy.

The semiconductor evaluation method according to the present invention is a semiconductor evaluation method using the semiconductor evaluation apparatus, wherein the control means includes the third switch and the fourth switch of the evaluation cell to which the pair transistor to be evaluated belongs. A first step of closing the switch, the first switch and the second switch of the column to which the evaluation cell belongs; and the control means supplies the input voltage and the reference voltage to the pair transistor to be evaluated. A second step of applying, and the control means deactivates the comparator, and the precharge circuit precharges the first bit line and the second bit line of the column to which the pair transistor to be evaluated belongs. 3 steps, the control means activates the comparator, the position of the pair transistor to be evaluated in the evaluation cell array, the input voltage, A fourth step of associating a reference voltage with the output signal output from the detection means and storing it in the storage means, and the control means inverts the output signal for each pair transistor to be evaluated. And a fifth step of outputting the relationship between the input voltage and the reference voltage at the time from the output means in association with the position of the pair transistor.
According to the present invention, the input voltage and the reference voltage are input to the comparator configured to include a pair transistor, and the change in the output voltage of the comparator is detected by the detecting means by changing the input voltage. The difference between the threshold values of the pair transistors can be obtained. Further, by performing the above evaluation on each pair of transistors arranged in a matrix, it is possible to obtain a distribution of differences in threshold values of each pair of transistors. Since voltage measurement can be performed faster than current measurement, a semiconductor evaluation circuit capable of measuring a large-scale semiconductor element at high speed and with high accuracy can be realized.

  According to the present invention, a comparator is configured with a transistor to be evaluated as a pair transistor, an input voltage and a reference voltage are input to the comparator, and a change in the output voltage of the comparator is detected by changing the input voltage. Therefore, the difference between the threshold values of the paired transistors can be obtained. Further, since a plurality of the comparators are arranged in a matrix, it is possible to obtain a distribution of threshold difference of each pair transistor by evaluating each pair transistor in the evaluation cell array. Since voltage measurement can be performed faster than current measurement, a semiconductor evaluation circuit capable of measuring a large-scale semiconductor element at high speed and with high accuracy can be realized.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 2 is a circuit diagram of the DMA-TEG according to the embodiment of the present invention.
In the figure, T1 to T5 are NMOS transistors, S1, S2, BS1a and BS1b are switches, 10 is a sense amplifier, 20 is a precharge circuit, DUT Pair is a pair transistor, Cell1-1, Cell1-n, Cellm-1, Cellm-n is an evaluation cell.

  The NMOS transistors T1 and T2 are transistors to be measured that are to be evaluated in the DMA-TEG, and are arranged adjacent to each other to constitute a pair transistor (DUT Pair). The NMOS transistors T1 to T5 and the switches S1 and S2 constitute an evaluation cell Cell1-1.

  This DMA-TEG includes an evaluation cell array in which evaluation cells Cell1-1 including a pair transistor (DUT Pair) are arranged in a matrix of m × n (m and n are positive integers) in the row and column directions. However, for easy understanding, evaluation cells Cell1-1, Cell1-n, Cellm-1, and Cellm-n at four corners of the evaluation cell array are illustrated. In addition, the transistors under measurement T1 and T2 are fine transistors with a low withstand voltage, and other than these transistors are composed of transistors having a withstand voltage of 3 V, for example.

  First, the configuration of the evaluation cell Cell1-1 will be described. The sources of the NMOS transistors T1 and T2 are commonly connected. The input voltage Vin is input to the gate of the NMOS transistor T1, and the reference voltage Vref is input to the gate of the NMOS transistor T2.

  The NMOS transistors T3 and T4 are provided to separate the NMOS transistors T1 and T2 from noise. The source of the NMOS transistor T3 is connected to the drain of the NMOS transistor T1, and the constant voltage signal Bias1 is connected to the gate. Entered. Further, the source of the NMOS transistor T4 is connected to the drain of the NMOS transistor T2, and the constant voltage signal Bias1 is input to the gate.

  The NMOS transistor T5 functions as a current source for allowing a constant current to flow, its drain is commonly connected to the sources of the NMOS transistors T1 and T2, its gate is supplied with a constant voltage signal Bias2, and its source is connected to the ground. The

  The NMOS transistors T1 to T5 constitute a comparator. That is, this comparator includes a pair transistor for comparing the magnitude relationship between the input voltage Vin and the reference voltage Vref, and outputs a comparison result from two output terminals (the drains of the NMOS transistors T3 and T4). . The comparator is activated when the NMOS transistor T5 can pass a constant current by the constant voltage signal Bias2, and is deactivated when the constant voltage signal Bias2 becomes 0 V or the like and cannot flow a constant current. The

  The switches S1 (third switch) and S2 (fourth switch) are connected to the drains (output terminals of the comparators) of the NMOS transistors T3 and T4, respectively, as a common bit line Bit1 (first bit line) and Bit1b (second bit line). ) To connect and release. One end of the switch S1 is connected to the drain of the NMOS transistor T3, and the other end is connected to the common bit line Bit1. One end of the switch S2 is connected to the drain of the NMOS transistor T4, and the other end is connected to the common bit line Bit1b. Further, the X select signal X1 is input to the switches S1 and S2, and the open / close state is controlled.

Evaluation cells having the same configuration as the evaluation cell Cell1-1 constitute n × m evaluation cell arrays. The evaluation cell array includes n X select signals X1 to Xn, m Y select signals Y1 to Ym, m common bit lines Bit1 to Bitm, and m common bit lines Bit1b to Bitmb.
That is, the DMA-TEG includes m first bit lines (common bit lines Bit1 to Bitm) for evaluation cells belonging to each column of the evaluation cell array and m pieces of evaluation cells for evaluation cells belonging to each column of the evaluation cell array. Second bit lines (common bit lines Bit1b to Bitmb).

  The n constant voltage signals Bias1 arranged in the row direction are commonly connected to a bias circuit (not shown). The n constant voltage signals Bias2 arranged in the row direction are commonly connected to a bias circuit (not shown). Further, the input voltage Vin and the reference voltage Vref respectively input to the pair transistors (DUT Pair) belonging to the evaluation cells Cell1-1 to Cellm-n are respectively supplied from bias circuits (not shown). These bias circuits are controlled by a control circuit (control means) not shown.

  One end of the switch BS1a (first switch) is connected to the common bit line Bit1, and the other end is connected to the main bit line MB. One end of the switch BS1b (second switch) is connected to the common bit line Bit1b, and the other end is connected to the main bit line MBb. The Y select signal Y1 is connected to the switches BS1a and BS1b.

  Similarly, one end of the switch BSma is connected to the common bit line Bitm, and the other end is connected to the main bit line MB. One end of the switch BSmb is connected to the common bit line Bitmb, and the other end is connected to the main bit line MBb. The Y select signal Ym is connected to the switches BSma and BSmb.

  The main bit lines MB and MBb are connected to two input terminals of the sense amplifier 10 (detection means). The sense amplifier 10 amplifies the voltage difference between the main bit lines MB and MBb and outputs an output signal Out. In other words, since the main bit lines MB and MBb are electrically connected to either the first bit line or the second bit line, the sense amplifier 10 is connected to the first bit line connected to the main bit lines MB and MBb. The voltage difference with the second bit line is amplified.

  The main bit lines MB and MBb are also connected to the precharge circuit 20. The precharge circuit 20 precharges the main bit lines MB and MBb (that is, the first bit line and the second bit line connected to the main bit lines MB and MBb) according to the precharge signal PreCharge. Its configuration will be described later.

That is, the first switch connects and releases the first bit line, the precharge circuit and the detection means (sense amplifier 10), and the second switch connects and releases the second bit line, the precharge circuit and the detection means. .
The X select signals X1 to Xn and the Y select signals Y1 to Ym are controlled by a decoder (control means) not shown.

Next, the operation of this DMA-TEG will be described with reference to FIG. FIG. 4A is a diagram showing a time change of each signal, and FIG. 4B is a circuit diagram for explaining the operation of one selected evaluation cell.
FIG. 2B also shows the circuit configuration of the precharge circuit 20. In the figure, 21 to 23 are PMOS transistors, and 24 is an inverter.

Hereinafter, a case where the NMOS transistors T1 and T2 are selected as evaluation targets will be described as an example.
First, the X select signal X1 and the Y select signal Y1 are output by a decoder (not shown), and the evaluation cell Cell1-1 is selected by turning on the switches S1, S2, BS1a, BS1b (time t0). . At this time, all other switches are open (off).
That is, the control means closes the third switch and the fourth switch of the evaluation cell to which the pair transistor to be evaluated belongs, and the first switch and the second switch of the column to which the evaluation cell belongs.

At this time, the reference voltage Vref is set to, for example, 0.6V, which is near the threshold value Vth of the NMOS transistors T1 and T2, and the input voltage Vin is also set to around 0.6V. The constant voltage signal Bias1 is set to 1.0V.
That is, the control means applies the input voltage and the reference voltage to the pair transistor to be evaluated.

Here, the constant voltage signal Bias2 is set to 0V, the precharge signal PreCharge is set to a high level, and the precharge circuit 20 precharges the main bit lines MB and MBb to 1.2V (time t0).
That is, the control means deactivates the comparator including the pair transistor to be evaluated, and precharges the first bit line and the second bit line in the column to which the pair transistor to be evaluated belongs.

  This precharge operation will be described below. When the precharge signal PreCharge becomes high level, a low level signal inverted by the inverter 24 is applied to the gates of the PMOS transistors 21 to 23. As a result, the PMOS transistors 21 to 23 are all turned on, and the common bit lines Bit1 and Bit1b electrically connected to the main bit lines MB and MBb, and the parasitic capacitance of the input portion of the sense amplifier 10 and the like are charged from the power supply. To precharge.

  Next, after the precharge is completed, the precharge signal PreCharge is set to a low level, and a voltage of about 0.4 V that allows the NMOS transistor T5 to flow a constant current is applied as the constant voltage signal Bias2 (time t1). ).

  Here, when 0.610 V is input as the input voltage Vin, assuming that the threshold voltages Vth of the NMOS transistors T1 and T2 are equal, the NMOS transistor T1 is turned on because the reference voltage Vref is 0.6 V, and the NMOS transistor T2 Is turned off. As a result, the charge accumulated in the parasitic capacitance of the system electrically connected to the common bit line Bit1 by the above-described precharge is discharged to the ground via the NMOS transistor T1, so that the common bit line Bit1 The voltage is lower than the voltage of the common bit line Bit1b. As a result, the voltage of the main bit line MB is lower than the voltage of the main bit line MBb.

Then, the sense amplifier 10 detects (amplifies) the potential difference between the main bit lines MB and MBb, and outputs a determination result “0” which is a low level voltage as the output signal Out. On the other hand, if the input voltage Vin is 0.59 V, the determination result “1”, which is a high-level voltage, is output as the output signal Out. When the input voltage Vin is 0.6 V which is equal to the reference voltage Vref, the voltages of the main bit lines MB and MBb are indefinite, and the output signal Out outputs either “0” or “1”. These results are stored in, for example, a storage means (not shown) and used when obtaining a threshold distribution described later.
In other words, the control unit activates the comparator, and stores the position in the evaluation cell array of the pair transistor to be evaluated, the input voltage, the reference voltage, and the output signal output from the detection unit in association with each other in the storage unit.

  The time required for this determination is determined by the time for which the parasitic capacitances of the main bit lines MB, MBb, etc. discharge electric charges. The parasitic capacitance Cp of the system electrically connected to the main bit lines MB and MBb is 2 pF, the current difference ΔI flowing through the NMOS transistors T1 and T2 which are pair transistors (DUT Pair) is 100 nA, and the detection sensitivity of the sense amplifier 10 is If ΔV = 50 mV, the determination time t is roughly t = Cp × ΔV / ΔI = 1 μs, and high-speed determination is possible.

  Here, let us consider a case where the threshold voltages Vth of the NMOS transistors T1 and T2, which are pair transistors, are different due to a process variation or the like. For example, when the threshold value Vth of the NMOS transistor T1 is 0.35V and the threshold value Vth of the NMOS transistor T2 is 0.30V, the output signal Out is “0” when the input voltage Vin = 0.36V, and the input voltage Vin = 0. Since the output signal Out becomes “1” at 34 V, the difference between the threshold values of the pair transistors can be determined at high speed from the relationship among the output signal Out, the reference voltage Vref, and the input voltage Vin.

In this way, the series of evaluation methods described above are repeatedly performed on one evaluation cell, the reference voltage Vref is fixed, and the input voltage Vin is changed until the output signal Out is inverted, so that a pair of pair transistors is obtained. The threshold difference can be obtained.
Further, by executing the above-described series of evaluation methods for each evaluation cell in the evaluation cell array, it is possible to obtain the distribution of the difference in threshold values of the pair transistors in the evaluation cell array at high speed and with high accuracy.

FIG. 4 shows the distribution of output signals of this DMA-TEG in the evaluation cell array.
FIGS. 9A to 9E show values of the output signal Out when each pair transistor is selected using the voltage difference ΔV (= input voltage Vin−reference voltage Vref) between the input voltage Vin and the reference voltage Vref as a parameter. ("0" or "1") is shown corresponding to the position in the evaluation cell array of each pair transistor. Here, in order to facilitate understanding, evaluation results of 10 × 10 pair transistors are shown.

As shown in FIG. 6A, when the voltage difference ΔV is +50 mV, the output signal Out is “0” for all the pair transistors, and therefore the difference in threshold values of the pair transistors of the DMA-TEG shown in this example. Are all within +50 mV.
Next, when the voltage difference ΔV is set to +25 mV as shown in FIG. 5B, the output signal Out changes to “1” when some pair transistors such as pair transistors belonging to 3 rows and 2 columns are evaluated. .

  Next, when the voltage difference ΔV is set to 0 mV as shown in FIG. 5C, the output signal Out is undefined in the case of pair transistors having the same threshold value, but the output signal Out is “ A definite value of “0” or “1” is output. Similarly, when the voltage difference ΔV is sequentially changed as shown in FIGS. 4D and 4E, the state of the output signal Out changes from “0” to “1” depending on the magnitude of the variation in the threshold value of the pair transistors. To change.

The figure (f) shows the figure which displayed the evaluation result shown to the figure (a)-(e) collectively. The figure shows the distribution of the threshold difference of the pair transistors by associating the voltage difference ΔV with the numbers from 0 to 4. For example, in the pair transistors belonging to 1 row and 1 column, the output signal Out is inverted from “0” to “1” when the voltage difference ΔV = + 25 mV to 0 mV from FIGS. In FIG. 6F, the voltage difference ΔV = + 25 to 0 mV is represented by “1”. Similarly, in the pair transistor belonging to 1 row and 2 column, the output signal Out is inverted from “0” to “1” when the voltage difference ΔV = −25 mV to −50 mV, so in FIG. It is expressed as “3” indicating a voltage difference ΔV = −25 to −50 mV.
Note that the evaluation results shown in FIGS. 5A to 5E are output by a display, a printer, or the like (output means) so that the user can easily recognize them.
In other words, the control means outputs the relationship between the input voltage and the reference voltage when the output signal is inverted for each pair transistor to be evaluated from the output means in association with the position of the pair transistor.

  As described above, FIG. 5F can express the difference in threshold values of all the pair transistors in the evaluation cell array. Thereby, it can be judged at a glance how much the threshold value varies in which place in the evaluation cell array. This figure can also be represented three-dimensionally.

  According to the DMA-TEG described above, for example, the test time required to evaluate and analyze the variation in threshold values of 1M pairs of transistors is 1 μs × 1M pairs = 1 sec. Therefore, a large amount of data with high accuracy can be acquired at high speed.

In the present invention, the number of sense amplifiers 10 is set to one for all evaluation cells in order to minimize the influence due to the variation in the characteristics of the sense amplifiers. However, when the wiring capacity increases, it becomes a factor that hinders high-speed measurement. There is. When further high-speed measurement is required, a plurality of sense amplifiers are arranged for each switch group (for example, BSma and BSmb), and the common bit lines Bitm and Bitmb are directly connected to the sense amplifiers by omitting the switches BSma and BSmb. The wiring capacity of the main bit lines MB and MBb and the capacity of the switch can be reduced, and the speed can be increased. However, in this case, in order to suppress the variation of the sense amplifiers, it is necessary to devise measures such as setting the dimensions (L and W) of the transistors constituting the sense amplifier to be large to make the variation strong.
The voltage used in the above description is an example.

As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.
For example, the NMOS transistors T3 and T4 may not be provided. Further, the number of pairs of transistor pairs is not limited to the example described above. In addition, the relationship between rows and columns may be interchanged.

It is a circuit diagram of DMA-TEG which concerns on a prior art. It is a circuit diagram of DMA-TEG which concerns on embodiment of this invention. It is a figure for demonstrating operation | movement of DMA-TEG same as the above. It is a figure which shows distribution in the evaluation cell array of the output signal of DMA-TEG same as the above.

Explanation of symbols

  T1-T5 NMOS transistor, S1, S2, BS1a, BS1b switch, 10 sense amplifier, 20 precharge circuit, DUT Pair pair transistor, Cell1-1, Cell1-n, Cellm-1, Cellm-n Evaluation cell

Claims (4)

A semiconductor evaluation circuit for evaluating transistor characteristics,
An evaluation cell array of n rows and m columns (n and m are positive integers) formed by arranging evaluation cells in a matrix in the row and column directions;
M first bit lines for the evaluation cells belonging to each column of the evaluation cell array;
M second bit lines for the evaluation cells belonging to each column of the evaluation cell array;
A precharge circuit for precharging the first bit line and a second bit line corresponding to the first bit line;
Detecting means for detecting a voltage difference between the first bit line and a corresponding second bit line and outputting an output signal;
A first switch for connecting and releasing the first bit line and the precharge circuit and the detection means;
A second switch for connecting and releasing the second bit line and the precharge circuit and the detection means;
The evaluation cell is
A comparator including a pair transistor for comparing the magnitude relationship between the input voltage and the reference voltage, and outputting a comparison result from two output terminals;
A third switch for connecting and opening one output terminal of the comparator and the first bit line;
A fourth switch for connecting and opening the other output terminal of the comparator and the second bit line;
Consisting of
The semiconductor evaluation circuit includes a control means for controlling the first switch to the fourth switch, the precharge circuit, the comparator, the input voltage, and the reference voltage. The comparator is
A pair transistor composed of a first transistor and a second transistor, the sources of which are connected, an input voltage is input to one gate, and a reference voltage is input to the other gate;
A current source for passing a current to the source of the pair transistor;
The semiconductor evaluation circuit according to claim 1, comprising: The comparator is
A third transistor having a source connected to the drain of the first transistor, a drain connected to the third switch, and a constant voltage applied to the gate;
A fourth transistor having a source connected to a drain of the second transistor, a drain connected to the fourth switch, and the constant voltage applied to a gate;
The semiconductor evaluation circuit according to claim 2, further comprising: A semiconductor evaluation method using the semiconductor evaluation apparatus according to any one of claims 1 to 3,
The control means closes the third switch and the fourth switch of the evaluation cell to which the pair transistor to be evaluated belongs, and the first switch and the second switch of the column to which the evaluation cell belongs. The first step;
A second step in which the control means applies the input voltage and the reference voltage to the pair transistor to be evaluated;
A third step in which the control means deactivates the comparator, and the precharge circuit precharges the first bit line and the second bit line of the column to which the pair transistor to be evaluated belongs;
The control means activates the comparator, and associates the position of the pair transistor to be evaluated in the evaluation cell array, the input voltage, the reference voltage, and the output signal output from the detection means in the storage means. A fourth step of storing;
Repeatedly
A fifth step in which the control means outputs from the output means the relationship between the input voltage and the reference voltage when the output signal is inverted for each pair transistor to be evaluated, in association with the position of the pair transistor; ,
Semiconductor evaluation method characterized by including.

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