JP5292906B2 - Semiconductor evaluation circuit and semiconductor evaluation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure the characteristics of large scale transistors to be measured with high precision. <P>SOLUTION: A circuit for evaluating a semiconductor includes n&times;m evaluation cells arranged in matrix of n rows and m columns (n and m are positive integers) and having transistors to be measured, a main source power supply line which supplies the source voltage for the transistors to be measured, a sub-source power supply line provided for each row or column and supplying the source voltage to the transistors to be measured in an evaluation cell belonging to each row or column, a row select line provided in each row and supplying a row select signal for selecting an evaluation cell belonging to each row, a column select line provided for each column and supplying a column select signal for selecting an evaluation cell belonging to each column, and a source power supply line switching circuit provided in correspondence with the sub-source power supply line, and switching connection/non-connection of the sub-source power supply line and the main source power supply line in response to a row select signal or a column select signal belonging, respectively, to the same row or column as the sub-source power supply line. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

 The present invention relates to a semiconductor evaluation circuit, and more particularly to a semiconductor evaluation circuit and a semiconductor evaluation method for evaluating the characteristics of a transistor under measurement which is a DUT (Device Under Test).

  When developing micro processes for semiconductors, TEG (Test Element Group) consisting of elements of various dimensions is fabricated on a semiconductor wafer to evaluate and analyze the characteristics of micro elements (transistors, resistor elements, etc.) We are developing devices that can withstand mass production by setting process conditions based on the results. In the process development so far, the optimum process conditions and transistor structure could be set by evaluating and analyzing the characteristics of individual transistors fabricated in the TEG. Can no longer be ignored. In addition, the phenomenon that the stress applied to the transistor changes depending on the state of the transistor and the characteristics of the transistor change cannot be ignored.

  From such a situation, for example, in a fine process with a processing level of 45 nm, the characteristics of both transistors vary even if they are adjacent transistors. Therefore, a small signal such as SRAM (Static Random Access Memory) is transferred to a pair transistor (adjacent It is predicted that the detection circuit and the amplification circuit that detect with two transistors) have a reduced operating margin or become inoperable. In this case, sufficient data cannot be obtained only by evaluating individual transistors. Therefore, the characteristics of a large number of transistors are evaluated, analyzed by statistical processing, and systematic characteristic differences and characteristic differences due to variations are separated. A large-scale TEG that can be analyzed is required.

  Conventionally, as a TEG for performing large-scale device evaluation, for example, a DMA (Device Matrix Array) -TEG in which a plurality of transistors to be measured are arranged in a matrix of n rows and m columns as shown in FIG. (See Non-Patent Document 1).

  The configuration of the DMA-TEG in the prior art will be described below with reference to FIG. DUT11 to DUTnm are transistors to be measured. The drains of the transistors under measurement DUT11 to DUT1m belonging to the first row are connected to the common drain line D1, and the sources are connected to the common source line S1. The common drain line D1 is connected via a switch SW2 to a common drain force line (Drain Force) to which a drain voltage is supplied. In order to monitor the voltage of the common drain line D1, the drain voltage sense line DS1 is connected to the drain sense line (Drain Sense) via the switch SW1.

  The common source line S1 is connected to a common source power source (Source Force). Further, in order to monitor the voltage of the common source line S1, the common source line S1 is connected to a source sense line (Source Sense) via a switch SW3. The switches SW1 to SW3 are controlled by an output signal of a decoder (not shown).

  With these sets as one set, the transistors to be measured DUTn1 to DUTnm which are sets in the n-th row are connected with the same connection as described above. The gates of the transistors under measurement DUT11 to DUTn1 belonging to the first column are connected to the common gate line G1, and the gates of the transistors under test DUT1m to DUTnm belonging to the mth column are connected to the common gate line Gm. .

Further, either the gate voltage VG1 or the gate non-selection voltage VGX is supplied to the common gate line G1 through the gate selection circuit 500. When the selection signal EN1 becomes high level (selected), the gate voltage VG1 is supplied to the gate line G1, and when the selection signal EN1 becomes low level (non-selected), the gate non-selection voltage VGX is supplied to the gate line G1. The gate non-selection voltage VGX is normally zero volts, but a negative voltage can be set as required.
With the DMA-TEG having such a configuration, the characteristics of the n × m transistors DUT11 to DUTnm can be evaluated.

Here, since the m measured transistors DUT11 to DUT1m are connected in parallel to the common drain line D1, if each of the measured transistors has an off-leak current (current that flows without the transistor being completely turned off), Since a leak current flows through the non-selected transistor under measurement, the characteristics of the transistor under measurement to be measured cannot be accurately evaluated. In this case, for example, the gate non-selection voltage VGX is set to about −0.2 V so as to suppress the off-leak current. FIG. 9B is a circuit diagram of the switches SW1 to SW3.
Yoshiyuki Shimizu, Mitsuo Nakamura, Toshimasa Matsuoka, and Kenji Taniguchi, “Test structure for precise statistical characteristics measurement of MOSFETs”, IEEE 2002 Int. Conference on Microelectronic Test Structure (ICMTS 2002), pp. 49-54, April 2002

  However, according to the above-described conventional DMA-TEG, when a large-scale DMA-TEG (for example, m = n = 512, that is, a TEG capable of evaluating 256K transistors) is configured, the common drain line D1 has 512 transistors are connected. Here, when an off-leakage current of about 10 pA flows through the fine transistor, the total of the leakage currents flowing through the non-selected transistors is 10 pA × 511 = 5.1 nA, and cannot be ignored with respect to the drain current flowing through the selected transistor. Therefore, there was a problem that high-precision measurement could not be performed.

    In addition, since the oxide film of the fine transistor is very thin, a gate leakage current flows to the drain and the source. If -0.2V is applied to the gate to suppress the off-leakage of the transistor, this time, the non-selected transistor 511 columns (G2 to Gm) × 512 rows (S1 to Sn) = 261,632 transistors between the gate and the source There was also a problem that a high-precision measurement could not be performed because this gate leakage current could not be ignored.

    The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor evaluation circuit and a semiconductor evaluation method capable of measuring characteristics of a large-scale transistor under measurement with high accuracy.

  In order to achieve the above object, the present invention provides a semiconductor evaluation circuit for evaluating the characteristics of a transistor under measurement as a first means for solving a semiconductor evaluation circuit, wherein n rows and m columns (n and m are N × m evaluation cells arranged in a matrix of (positive integer) and having a transistor to be measured, a main source power line for supplying a source voltage for the transistor to be measured, and each row or each column A sub-source power supply line for supplying a source voltage to a transistor under measurement of an evaluation cell belonging to each row or column, and a row selection for selecting an evaluation cell belonging to each row. A row selection line for supplying signals, a column selection line for supplying a column selection signal for selecting an evaluation cell belonging to each column, provided for each column, and corresponding to the sub-source power supply line The relevant A source power supply line switching circuit that switches connection / disconnection between the sub-source power supply line and the main source power supply line in response to a row selection signal belonging to the same row as the source power supply line or a column selection signal belonging to the column, It is characterized by providing.

    Further, as a second solving means relating to the semiconductor evaluation circuit, in the first solving means, a main drain power supply line for supplying a drain voltage for the transistor under measurement and a gate voltage for the transistor under measurement are obtained. Main gate power supply line for supply, sub-source power supply line provided for each row or column, and for supplying a drain voltage to the transistor under measurement of the evaluation cell belonging to each row or column, and each row or column A sub-gate power supply line for supplying a gate voltage to the transistor under measurement of the evaluation cell belonging to each row or each column, and provided corresponding to the sub-drain power supply line, In response to a row selection signal belonging to the same row or a column selection signal belonging to a column, connection / disconnection of the sub-drain power supply line and the main drain power supply line is disconnected. A drain power supply line switching circuit and a corresponding subgate power supply line provided in response to a row selection signal belonging to the same row as the subgate power supply line or a column selection signal belonging to a column. And a gate power line switching circuit for switching connection / disconnection between the main gate power line and the main gate power line.

 Further, as a third solving means relating to the semiconductor evaluation circuit, in the first or second solving means, a main drain voltage detection line for detecting a drain voltage of the measured transistor and a source of the measured transistor A main source voltage detection line for detecting a voltage, a main gate voltage detection line for detecting a gate voltage of the transistor under measurement, and provided for each row or each column, of the evaluation cells belonging to each row or each column A sub-drain voltage detection line for detecting the drain voltage of the transistor under measurement and a sub-source voltage for detecting the source voltage of the transistor under measurement of the evaluation cell belonging to each row or each column provided for each row or each column A detection line is provided for each row or each column and detects the gate voltage of the transistor under measurement of the evaluation cell belonging to each row or each column. Corresponding to the row selection signal belonging to the same row as the sub-drain voltage detection line or the column selection signal belonging to the column. A drain detection line switching circuit for switching connection / disconnection between the drain voltage detection line and the main drain voltage detection line, and a sub-source voltage detection line provided in correspondence with the sub-source voltage detection line. A source detection line switching circuit for switching connection / disconnection between the sub-source voltage detection line and the main source voltage detection line according to a row selection signal belonging to the column or a column selection signal belonging to the column; and the sub-gate voltage detection line In response to a row selection signal belonging to the same row as the sub-gate voltage detection line or a column selection signal belonging to a column, the sub-gate voltage detection line and the main gate voltage detection line Characterized in that it comprises a gate detection line switching circuit for switching connection / disconnection.

    Further, as a fourth solving means related to the semiconductor evaluation circuit, in the third solving means, each of the evaluation cells has one input terminal connected to the row selection line belonging to its own row, and the other input. A terminal is connected to the column selection line belonging to its own column, and its own measurement is performed according to a row selection signal supplied to the connected row selection line and a column selection signal supplied to the column selection line A selection circuit that outputs a selection signal indicating selection / non-selection of a transistor, and a connection between the sub-drain power supply line belonging to the same row or column as itself and a drain terminal of the transistor under measurement according to the selection signal The first switch for switching between / not connected and the connection / disconnection between the sub-source power supply line belonging to the same row or column as itself and the source terminal of the transistor under measurement according to the selection signal A second switch for switching, and a third switch for switching connection / disconnection between the sub-gate power supply line belonging to the same row or column as itself and the gate terminal of the transistor under test according to the selection signal And a fourth switch for switching connection / disconnection between the sub-drain voltage detection line belonging to the same row or column as the self and the drain terminal of the transistor under test according to the selection signal, and the selection signal A fifth switch for switching connection / disconnection between the sub-source voltage detection line belonging to the same row or column as the self and a source terminal of the transistor under measurement, and a self-switch according to the selection signal. And a sixth switch for switching connection / disconnection between the sub-gate voltage detection line belonging to the same row or column and the gate terminal of the transistor under test. And wherein the door.

 Further, as a fifth solving means related to the semiconductor evaluation circuit, in any of the first to fourth solving means, a column selection signal is supplied to each column selection line and a row selection signal is supplied to each row selection line. The selection signal supply circuit includes a selection control signal, a clock signal, a column address signal, a row address signal, and two test signals, and is in a state of the two test signals. Accordingly, the process shifts to a normal evaluation mode, a first test mode, or a second test mode. In the normal evaluation mode, the column address signal and the row address are changed according to the state of the selection control signal. A first address mode for generating the column selection signal and the row selection signal based on the signal and a count operation in synchronization with the clock signal, and the column selection based on the count result. A second address mode for generating a signal and the row selection signal, and generating the column selection signal and the row selection signal for selecting all evaluation cells in the first test mode, In the second test mode, the column selection signal and the row selection signal for deselecting all evaluation cells are generated.

 On the other hand, the present invention is a semiconductor evaluation method for evaluating the characteristics of a transistor under measurement as a first solving means related to a semiconductor evaluation method, and uses a semiconductor evaluation circuit having the first solving means. A column selection signal for selecting the evaluation cell to be evaluated is supplied to the column selection line belonging to the column of the evaluation cell to be evaluated, and the evaluation cell to be evaluated is selected to the row selection line belonging to the row. A first step of supplying a row selection signal for performing the evaluation, a second step of supplying a desired source voltage to at least the main source power supply line, and measuring the current flowing through the main source power supply line. And a third step of evaluating the characteristics of the target transistor to be measured.

 According to another aspect of the present invention, there is provided a semiconductor evaluation method for evaluating characteristics of a transistor under measurement as a second solving means relating to a semiconductor evaluation method, wherein the semiconductor includes any one of the second to fourth solving means. The evaluation circuit is used to supply a column selection signal for selecting the evaluation cell to be evaluated to the column selection line belonging to the column of the evaluation cell to be evaluated, and to the row selection line belonging to the row. A first step of supplying a row selection signal for selecting an evaluation cell to be used, supplying a desired drain voltage to the main drain power supply line, supplying a desired source voltage to the main source power supply line, A second step of supplying a desired gate voltage to the main gate power supply line, and a third step of evaluating the characteristics of the transistor under measurement by measuring a current flowing through the main source power supply line. Characterized in that it.

 Further, the present invention provides a semiconductor evaluation method for evaluating characteristics of a transistor under measurement as a third solving means relating to a semiconductor evaluation method, wherein the semiconductor evaluation circuit having the fifth solving means is used, When performing characteristic evaluation using the first address mode of the normal evaluation mode, the state of the two test signals input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the selection signal The state of the selection control signal input to the supply circuit is set to a state corresponding to the first address mode, and a column address signal and a row address signal indicating the position of the evaluation cell to be evaluated are input to the selection signal supply circuit. A first step, supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired source voltage to the main gate power line A second step of supplying a gate voltage, and having a third step for characterization of transistors under measurement in the evaluation target by measuring the current flowing through the main source power line.

 Further, the present invention provides a semiconductor evaluation method for evaluating the characteristics of a transistor under measurement as a fourth solving means relating to a semiconductor evaluation method, wherein the semiconductor evaluation circuit having the fifth solving means is used, When performing characteristic evaluation using the second address mode of the normal evaluation mode, the state of the two test signals input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the selection signal A first step of setting a state of a selection control signal input to the supply circuit to a state corresponding to a second address mode; supplying a desired drain voltage to the main drain power supply line; and supplying a desired drain voltage to the main source power supply line And a second step of supplying a desired gate voltage to the main gate power supply line, and measuring the current flowing through the main source power supply line. And having a third step for characterization of transistors under measurement, the.

 Further, the present invention provides a semiconductor evaluation method for evaluating the characteristics of a transistor under measurement as a sixth solving means relating to the semiconductor evaluation method, using the semiconductor evaluation circuit having the fifth solving means, When performing characteristic evaluation using the first test mode, a first step of setting states of two test signals input to the selection signal supply circuit to a state corresponding to the first test mode; A desired drain voltage is supplied to the main drain power supply line, a desired source voltage is supplied to the main source power supply line, and a desired gate voltage is supplied to the main gate power supply line. And performing a second step.

 Further, the present invention provides a semiconductor evaluation method for evaluating the characteristics of a transistor under measurement as a seventh solving means relating to the semiconductor evaluation method, using the semiconductor evaluation circuit having the fifth solving means, When performing the characteristic evaluation using the second test mode, the first step of setting the states of the two test signals input to the selection signal supply circuit to a state corresponding to the second test mode; A desired drain voltage is supplied to the main drain power supply line, a desired source voltage is supplied to the main source power supply line, and a desired gate voltage is supplied to the main gate power supply line. And a second step of measuring the sum of.

  According to the present invention, it is possible to measure the characteristics of a large-scale transistor under measurement with high accuracy.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a circuit configuration diagram of the semiconductor evaluation circuit according to the first embodiment. As shown in FIG. 1, the semiconductor evaluation circuit according to this embodiment includes n × m evaluation cells C11 to Cnm arranged in a matrix of n rows and m columns (n and m are positive integers). It is a DMA-TEG for evaluating the characteristics of a provided transistor under measurement, and is a 1V N-channel MOS (Metal Oxide Semiconductor) transistor manufactured by a fine process of 45 nm in one evaluation cell. A measurement transistor DUT is provided. The detailed internal circuit configuration of the evaluation cells C11 to Cnm will be described later.

  In FIG. 1, reference numeral DF denotes a main drain force line (main drain power supply line) for supplying a drain voltage for a transistor under measurement, and one end of the drain is connected to an external power supply device (not shown). It is connected to the power supply terminal DFP. Reference numeral GF denotes a main gate force line (main gate power supply line) for supplying a gate voltage for the transistor under measurement, and one end thereof is connected to a gate power supply terminal GFP for connection to an external power supply device. . Reference numeral SF denotes a main source force line (main source power supply line) for supplying a source voltage for the transistor under measurement, and one end thereof is connected to a source power supply terminal SFP for connection to an external power supply device. .

  Reference numerals DF1 to DFm are sub-drain force lines (sub-drain power supply lines) that are provided for each column and supply a drain voltage to the transistor under measurement of the evaluation cell belonging to each column. Specifically, the sub-drain force line DF1 is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the sub-drain force line DFm is connected to the evaluation cells C1m to Cnm belonging to the m-th column. .

  Reference numerals GF1 to GFm are sub-gate force lines (sub-gate power supply lines) that are provided for each column and supply a gate voltage to the transistor under measurement of the evaluation cell belonging to each column. Specifically, the sub-gate force line GF1 is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the sub-gate force line GFm is connected to the evaluation cells C1m to Cnm belonging to the m-th column. .

  Symbols SF1 to SFm are sub-source force lines (sub-source power supply lines) that are provided for each column and supply a source voltage to the transistor under measurement of the evaluation cell belonging to each column. Specifically, the sub source force line SF1 is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the sub source force line SFm is connected to the evaluation cells C1m to Cnm belonging to the m column. .

  Reference sign DS denotes a main drain sense line (main drain voltage detection line) for detecting the drain voltage of the transistor under measurement, and one end of which is a drain sense terminal DSP for connection to an external voltage measuring device (not shown). It is connected. Reference numeral GS denotes a main gate sense line (main gate voltage detection line) for detecting the gate voltage of the transistor under measurement, and one end thereof is connected to a gate sense terminal GSP for connection to an external voltage measuring device. . Reference symbol SS denotes a main source sense line (main source voltage detection line) for detecting the source voltage of the transistor under measurement, and one end thereof is connected to a source sense terminal SSP for connection to an external voltage measuring device. .

  Symbols DS1 to DSn are sub-drain sense lines (sub-drain voltage detection lines) that are provided for each row and detect the drain voltage of the transistor under measurement of the evaluation cell belonging to each row. Specifically, the sub-drain sense line DS1 is connected to the evaluation cells C11 to C1m belonging to the first row, and the sub-drain sense line DSn is connected to the evaluation cells Cn1 to Cnm belonging to the n-th row. .

  Symbols GS1 to GSn are sub-gate sense lines (sub-gate voltage detection lines) that are provided for each row and detect the gate voltage of the transistor under measurement of the evaluation cell belonging to each row. Specifically, the sub-gate sense line GS1 is connected to the evaluation cells C11 to C1m belonging to the first row, and the sub-gate sense line GSn is connected to the evaluation cells Cn1 to Cnm belonging to the n-th row. .

  Symbols SS1 to SSn are sub-source sense lines (sub-source voltage detection lines) that are provided for each row and detect the source voltage of the transistor under measurement of the evaluation cell belonging to each row. Specifically, sub-source sense line SS1 is connected to evaluation cells C11 to C1m belonging to the first row, and sub-source sense line DSn is connected to evaluation cells Cn1 to Cnm belonging to the n-th row. .

  Reference numerals X1 to Xm are column selection lines provided for each column and used to select evaluation cells belonging to each column. One end of each column selection line X1 to Xm is connected to an X select main decoder MDX (not shown in FIG. 1), and an X select signal (column selection signal) XS1 to XS1 supplied from the X select main decoder MDX. XSm is supplied to the evaluation cells belonging to each column via the column selection lines X1 to Xm. Specifically, for example, the column selection line X1 of the first column is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the X selection signal XS1 supplied from the X selection main decoder MDX is the column selection line X1. To the evaluation cells C11 to Cn1. Similarly, for example, the column selection line Xm of the m-th column is connected to the evaluation cells C1m to Cnm belonging to the m-th column, and the X selection signal XSm supplied from the X selection main decoder MDX passes through the column selection line Xm. Are supplied to the evaluation cells C1m to Cnm.

  Symbols Y1 to Yn are row selection lines provided for each row and for selecting evaluation cells belonging to each row. One end of each row selection line Y1 to Yn is connected to a Y selection main decoder MDY (not shown in FIG. 1), and Y selection signals (row selection signals) YS1 to YSn supplied from the Y selection main decoder MDY. Are supplied to the evaluation cells belonging to each row via the row selection lines Y1 to Yn. Specifically, for example, the row selection line Y1 of the first row is connected to the evaluation cells C11 to C1m belonging to the first row, and the Y selection signal YS1 supplied from the Y selection main decoder MDY is the row selection line Y1. To the evaluation cells C11 to C1m. Similarly, for example, the row selection line Yn of the nth row is connected to the evaluation cells Cn1 to Cnm belonging to the nth row, and the Y selection signal YSn supplied from the Y selection main decoder MDY is passed through the row selection line Yn. Are supplied to the evaluation cells Cn1 to Cnm.

  Reference signs PSW1 to PSWm are provided for each column, and in accordance with an X select signal supplied to a column selection line belonging to each column, the connection / non-connection between the sub-drain force line and the main drain force line DF belonging to that column. Power supply line switching circuit for switching connection, connection / non-connection between the sub-source force line belonging to the column and the main source force line SF, and connection / non-connection between the sub-gate force line belonging to the column and the main gate force line GF It is.

  Each of the power supply line switching circuits PSW1 to PSWm is composed of three N-channel MOS transistors. Specifically, for example, the power line switching circuit PSW1 belonging to the first column includes a DF transistor (drain power line switching circuit) DFT1, a GF transistor (gate power line switching circuit) GFT1, and an SF transistor (source power line). Switching circuit) SFT1. The drain terminal of the DF transistor DFT1 is connected to the main drain force line DF, the source terminal is connected to the sub-drain force line DF1 belonging to the first column, and the gate terminal is connected to the column selection line X1 belonging to the first column. Yes. The drain terminal of the GF transistor GFT1 is connected to the main gate force line GF, the source terminal is connected to the sub-gate force line GF1 belonging to the first column, and the gate terminal is connected to the column selection line X1 belonging to the first column. Yes. The drain terminal of the SF transistor SFT1 is connected to the main source force line SF, the source terminal is connected to the sub-source force line SF1 belonging to the first column, and the gate terminal is connected to the column selection line X1 belonging to the first column. Yes.

  Similarly, the power line switching circuit PSWm belonging to the m-th column includes a DF transistor DFTm, a GF transistor GFTm, and an SF transistor SFTm. The drain terminal of the DF transistor DFTm is connected to the main drain force line DF, the source terminal is connected to the sub-drain force line DFm belonging to the mth column, and the gate terminal is connected to the column selection line Xm belonging to the mth column. Yes. The drain terminal of the GF transistor GFTm is connected to the main gate force line GF, the source terminal is connected to the sub-gate force line GFm belonging to the m-th column, and the gate terminal is connected to the column selection line Xm belonging to the m-th column. Yes. The drain terminal of the SF transistor SFTm is connected to the main source force line SF, the source terminal is connected to the sub-source force line SFm belonging to the mth column, and the gate terminal is connected to the column selection line Xm belonging to the mth column. Yes.

  Reference signs SSW1 to SSWn are provided for each row, and in accordance with a Y select signal supplied to a row selection line belonging to each row, connection / non-connection between the sub-drain sense line and the main drain sense line DS belonging to the row, This is a detection line switching circuit that switches connection / disconnection between the sub-source sense line belonging to the row and the main source sense line SS and connection / non-connection between the sub-gate sense line belonging to the row and the main gate sense line GS. .

  Each of the detection line switching circuits SSW1 to SSWn is composed of three N-channel MOS transistors. Specifically, for example, the detection line switching circuit SSW1 belonging to the first row includes a DS transistor (drain detection line switching circuit) DST1, a GS transistor (gate detection line switching circuit) GST1, and an SS transistor (source detection line). Switching circuit) SST1. The source terminal of the DS transistor DST1 is connected to the main drain sense line DS, the drain terminal is connected to the sub-drain sense line DS1 belonging to the first row, and the gate terminal is connected to the row selection line Y1 belonging to the first row. Yes. The source terminal of the GS transistor GST1 is connected to the main gate sense line GS, the drain terminal is connected to the sub-gate sense line GS1 belonging to the first row, and the gate terminal is connected to the row selection line Y1 belonging to the first row. Yes. The SS transistor SST1 has a source terminal connected to the main source sense line SS, a drain terminal connected to the sub-source sense line SS1 belonging to the first row, and a gate terminal connected to the row selection line Y1 belonging to the first row. Yes.

  Similarly, the detection line switching circuit SSWn belonging to the nth row includes a DS transistor DSTn, a GS transistor GSTn, and an SS transistor SSTn. The source terminal of the DS transistor DSTn is connected to the main drain sense line DS, the drain terminal is connected to the sub-drain sense line DSn belonging to the nth row, and the gate terminal is connected to the row selection line Yn belonging to the nth row. Yes. The source terminal of the GS transistor GSTn is connected to the main gate sense line GS, the drain terminal is connected to the sub-gate sense line GSn belonging to the nth row, and the gate terminal is connected to the row selection line Yn belonging to the nth row. Yes. The source terminal of the SS transistor SSTn is connected to the main source sense line SS, the drain terminal is connected to the sub-source sense line SSn belonging to the nth row, and the gate terminal is connected to the row selection line Yn belonging to the nth row. Yes.

  Next, a detailed internal circuit configuration of the evaluation cells C11 to Cnm will be described. In addition, since the internal circuit configuration in each of the evaluation cells C11 to Cnm is common, the following description will be made using the evaluation cell C11 as a representative.

  As shown in FIG. 1, the evaluation cell C11 includes a measured transistor DUT, a selection circuit 10, a first transistor (first switch) T1, a second transistor (second switch) T2, and a third transistor ( The third switch T3, the fourth transistor (fourth switch) T4, the fifth transistor (fifth switch) T5, and the sixth transistor (sixth switch) T6.

  As described above, the transistor DUT to be measured is a 1V-type N-channel MOS transistor manufactured by a fine process of 45 nm. The first transistor T1 to the sixth transistor T6 are 3V N-channel MOS transistors with stable characteristics, and the selection circuit 10 is also composed of 3V MOS transistors manufactured by the same process. .

  In the selection circuit 10, one input terminal is connected to a row selection line (Y1 here) belonging to its own row, and the other input terminal is connected to a column selection line (here X1) belonging to its own column. At the same time, a selection signal indicating selection / non-selection of its own transistor under test DUT according to the Y selection signal YS1 supplied to the connected row selection line Y1 and the X selection signal XS1 supplied to the column selection line X1. Output. Specifically, the selection circuit 10 includes a NAND circuit 10a and an inverter circuit 10b.

  In the NAND circuit 10a, one input terminal is connected to a row selection line (here Y1) belonging to its own row, and the other input terminal is connected to a column selection line (here X1) belonging to its own column. A negative logical product signal of the Y select signal YS1 supplied to the row selection line Y1 and the X select signal XS1 supplied to the column selection line X1 is output to the inverter circuit 10b. The inverter circuit 10b outputs a logically inverted signal of the output signal of the NAND circuit 10a as a selection signal.

  The first transistor T1 switches connection / disconnection between the sub-drain force line DF1 belonging to its own column (here, the first column) and the drain terminal of its own transistor DUT in accordance with the selection signal. The drain terminal is connected to the sub-drain force line DF1, the source terminal is connected to the drain terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the inverter circuit 10b). ing.

  The second transistor T2 switches connection / disconnection between the sub-source force line SF1 belonging to its own column (here, the first column) and the source terminal of its own transistor under test DUT according to the selection signal. The source terminal is connected to the sub-source force line SF1, the drain terminal is connected to the source terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (more specifically, the inverter circuit 10b). ing.

  The third transistor T3 switches connection / disconnection between the sub-gate force line GF1 belonging to its own column (here, the first column) and the gate terminal of its own transistor DUT to be measured according to the selection control signal. The drain terminal is connected to the sub-gate force line GF1, the source terminal is connected to the gate terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the inverter circuit 10b). Has been.

  The fourth transistor T4 switches connection / disconnection between the sub-drain sense line DS1 belonging to its own row (here, the first row) and the drain terminal of its own transistor under test DUT according to the selection signal. The source terminal is connected to the sub-drain sense line DS1, the drain terminal is connected to the drain terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the inverter circuit 10b). ing.

  The fifth transistor T5 switches connection / disconnection between the sub-source sense line SS1 belonging to its own row (here, the first row) and the source terminal of its own transistor under test DUT according to the selection signal. The source terminal is connected to the sub-source sense line SS1, the drain terminal is connected to the source terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the inverter circuit 10b). ing.

  The sixth transistor T6 switches connection / disconnection between the sub-gate sense line GS1 belonging to its own row (here, the first row) and the gate terminal of its own transistor under test DUT according to the selection signal. The source terminal is connected to the sub-gate sense line GS1, the drain terminal is connected to the gate terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (more specifically, the inverter circuit 10b). ing.

  As described above, the semiconductor evaluation circuit according to the present embodiment employs a completely separated Kelvin sense method capable of performing Kelvin sense evaluation for each measured transistor as the circuit configuration of the evaluation cell. Here, before explaining the operation of the semiconductor evaluation circuit according to the present embodiment, a preliminary description will be given of the complete separation type Kelvin sensing method as a premise thereof with reference to FIG.

  FIG. 2 shows only the circuit portion related to the evaluation cell C11 extracted from FIG. 1 for convenience of explanation. In FIG. 2, the power supply line switching circuit PSW1 and the detection line switching circuit SSW1 are omitted, the drain terminal of the first transistor T1 and the main drain force line DF are directly connected, and the source terminal of the second transistor T2 is connected to the main terminal. The source force line SF is directly connected, the drain terminal of the third transistor T3 and the main gate force line GF are directly connected, the source terminal of the fourth transistor T4 and the main drain sense line DS are directly connected, and the fifth The case where the source terminal of the transistor T5 and the main source sense line SS are directly connected and the source terminal of the sixth transistor T6 and the main gate sense line GS are directly connected is illustrated.

  In FIG. 2, when the X selection signal XS1 and Y selection signal YS1 indicating “1” are supplied to the column selection line X1 and the row selection line Y1, and the evaluation cell C11 is selected, “1” is output from the selection circuit 10. A selection signal is output. As a result, all of the first transistor T1 to the sixth transistor T6 are turned on, the drain terminal of the transistor DUT to be measured is connected to the main drain force line DF and the main drain sense line DS, and the source terminal is the main source force. The gate terminal is connected to the main gate force line GF and the main gate sense line GS, and is connected to the line SF and the main source sense line SS.

  In this state, the drain voltage is supplied from the external power supply device to the main drain force line DF, the source voltage is supplied to the main source force line SF, and the gate voltage is supplied to the main gate force line GF. The measurement transistor DUT is driven to detect the drain voltage generated in the main drain sense line DS, and also to detect the source voltage generated in the main source sense line SS and the gate voltage generated in the main gate sense line GS. Perform characterization.

  On the other hand, when the X select signal XS1 or Y select signal YS1 indicating “0” is output to at least one of the column selection line X1 and the row selection line Y1, and the evaluation cell C11 is not selected, the output of the selection circuit 10 is “0”. In this case, all of the first transistor T1 to the sixth transistor T6 are turned off, and the measured transistor DUT is not selected.

As described above, in the evaluation cell adopting the complete separation type Kelvin sense method, a switch (transistor) is provided for each transistor to be measured, and it becomes possible to evaluate Kelvin sense completely separated. Evaluation is possible.
However, for example, when the evaluation cells shown in FIG. 2 are arranged in a matrix of n = m = 512 and a medium-scale DMA-TEG capable of evaluating 256K measured transistors DUT is configured, the main drain force Assuming that the W size of the first transistor T1 on the line DF side is 15 μm and off-leakage and gate leakage current of 10 ⁻¹³ A / μm occur when not selected, the total leakage current is 512 × 512 × 15 μm × 10 ^{− Since 13} A / μm≈400 nA and the drain current flowing through the selected transistor under test DUT cannot be ignored, there is a problem that high-precision measurement cannot be performed.

 Therefore, in this embodiment, when the DMA-TEG is configured by arranging evaluation cells adopting the complete separation type Kelvin sense method in a matrix form, as described with reference to FIG. 1, it is provided for each column. In response to the X select signal supplied to the column selection line belonging to each column, the sub-drain force line belonging to the column and the main drain force line DF are connected / disconnected, and the sub-source force line belonging to the column is connected to the main source force line. One evaluation cell is provided by providing power supply line switching circuits PSW1 to PSWm for switching connection / disconnection with the source force line SF and connection / disconnection between the sub-gate force line belonging to the column and the main gate force line GF. The total leakage current generated when is selected is reduced.

 In the following description of the operation of the semiconductor evaluation circuit according to this embodiment shown in FIG. 1, the principle of reducing the leakage current in this embodiment will be described. In the following, a case where the transistor under test DUT of the evaluation cell C11 is selected as an evaluation target will be described as an example.

 First, when the X selection signal XS1 and Y selection signal YS1 indicating “1” are supplied to the column selection line X1 and the row selection line Y1, and the evaluation cell C11 is selected, the power supply line switching circuit PSW1 belonging to the first column is selected. Since the DF transistor DFT1, the GF transistor GFT1, and the SF transistor SFT1 are all turned on, the sub drain force line DF1 and the main drain force line DF belonging to the first column are connected, and the sub gate force line GF1 is connected to the main gate force line GF1. The gate force line GF is connected, and the sub source force line SF1 and the main source force line SF are connected.

 On the other hand, the X selection signals XS2 to XSm indicating “0” are supplied to the column selection lines X2 to Xm belonging to the other columns (second column to m column). The transistors in the power supply line switching circuits PSW2 to PSWm to which they belong are turned off, and the sub drain force lines DF2 to DFm, the sub gate force lines GF2 to GFm, and the sub source force lines SF2 to SFm belonging to the second column to the m column are The main drain force line DF, the main gate force line GF, and the main source force line SF are disconnected.

 At this time, since the DS transistor DST1, the GS transistor GST1, and the SS transistor SST1 in the detection line switching circuit SSW1 belonging to the first row are all turned on, the sub-drain sense line DS1 belonging to the first row and the main transistor The drain sense line DS is connected, the sub-gate sense line GS1 and the main gate sense line GS are connected, and the sub-source sense line SS1 and the main source sense line SS are connected.

 On the other hand, since the Y select signals YS2 to YSn indicating "0" are supplied to the row selection lines Y2 to Yn belonging to the other rows (second row to nth row), the second to nth rows are supplied. The transistors in the detection line switching circuits SSW2 to SSWn to which they belong are turned off, and the sub-drain sense lines DS2 to DSm, the sub-gate sense lines GS2 to GSm, and the sub-source sense lines SS2 to SSm belonging to the second to nth rows are The main drain sense line DS, main gate sense line GS, and main source sense line SS are disconnected.

 In the evaluation cell C11, a selection signal indicating “1” is output from the selection circuit 10, all of the first transistor T1 to the sixth transistor T6 are turned on, and the drain terminal of the transistor DUT to be measured is the sub-drain. The source line is connected to the force line DF1 (ie, the main drain force line DF) and the sub drain sense line DS1 (ie, the main drain sense line DS), and the source terminals are the sub source force line SF1 (ie, the main source force line SF) and the sub source sense line. The gate terminal is connected to the sub-gate force line GF1 (ie, the main gate force line GF) and the sub-gate sense line GS1 (ie, the main gate sense line GS).

  In this state, the drain voltage VD is supplied from the external power supply device to the drain force terminal DFP (main drain force line DF), the source voltage VS is supplied to the source force terminal SFP (main source force line SF), By supplying the gate voltage VG to the gate force terminal GFP (main gate force line GF), the transistor under test DUT of the evaluation cell C11 is driven. At this time, the voltage of the drain sense terminal DSP (main drain sense line DS) is measured by an external voltage measuring device, the voltage of the source sense terminal SSP (main source sense line SS), and the gate sense terminal GSP (main gate sense line). GS) is measured to monitor the drain terminal voltage, the source terminal voltage, and the gate terminal voltage of the transistor DUT to be measured, and the drain voltage VD supplied from the power supply device so that each terminal voltage becomes a desired voltage. The source voltage VS and the gate voltage VG are adjusted. For example, by fixing the drain voltage VD and the source voltage VS and measuring the current (drain current ID) flowing between the drain and source when the gate voltage VG is swung in a desired range, the transistor DUT to be measured is measured. Perform characterization. In order to measure the drain current ID, an ammeter may be connected in series between the source force terminal SFP and the power supply device.

  In this way, while the evaluation cell C11 is selected and the characteristics of the measured transistor DUT are being evaluated, all of the first transistor T1 to the sixth transistor T6 in the other evaluation cells C21 to Cn1 belonging to the first column. Is turned off, so that the measured transistor DUT in the evaluation cells C21 to Cn1 is electrically disconnected from the sub-drain force line DF1, the sub-gate force line GF1, and the sub-source force line SF1 belonging to the first column. . Since the sub-drain force line DF1, the sub-gate force line GF1, and the sub-source force line SF1 are common lines to the evaluation cells C11 to Cn1 belonging to the first column, they are also drained to the unselected evaluation cells C21 to Cn1. The voltage VD, the source voltage VS, and the gate voltage VG are supplied, and the off-leakage current and the gate leakage current described with reference to FIG. 2 are generated.

  However, in the semiconductor evaluation circuit according to the present embodiment, only the sub-drain force line DF1, the sub-gate force line GF1, and the sub-source force line SF1 in the column (here, the first column) to which the evaluation cell C11 to be selected belongs are used as the main drain. Connected to the force line DF, the main gate force line GF, and the main source force line SF, the sub-drain force lines DF2 to DFm, the sub-gate force lines GF2 to GFm and the sub-sources in other columns (second column to m column) The force lines SF2 to SFm are electrically separated from the main drain force line DF, the main gate force line GF, and the main source force line SF by the switches PSW2 to PSWm.

Here, first, the leakage current generated in the column to which the evaluation cell C11 to be selected belongs is calculated. For example, 512 evaluation cells per column (n = 512) are provided, and the W size of the first transistor T1 on the main drain force line DF side is 15 μm, and off-leakage of 10 ⁻¹³ A / μm when not selected. Assuming that a gate leakage current is generated, the total leakage current of the column to which the evaluation cell C11 to be selected belongs is 511 × 15 μm × 10 ⁻¹³ A / μm≈0.8 nA, which is compared with the case described in FIG. Thus, the total leakage current generated in the entire semiconductor evaluation circuit can be reduced to about 1/500.

Next, the off-leakage of unselected switches PSW2 to PSWm connected to the main drain force line DF, the main gate force line GF, and the main source force line SF is calculated. For example, considering the leakage of the main drain force line DF, the transistor DFT2 is set to have a W size of 60 μm. If an off-leakage of 10 ⁻¹³ A / μm occurs when not selected, 511 DFT2 to DFTm are connected. Therefore, the total off-leakage current is 511 × 60 μm × 10 ⁻¹³ A / μm≈3 nA, which is about 1/100 compared with the case described in FIG. Here, W = 60 μm is set because a large drain current is desired, and if it is set to 15 μm, which is the same as T1, if necessary, the leakage current becomes ¼.

  On the other hand, although the same applies to the row direction, no current flows through the sense-side transistor. For example, the transistor W such as T4, T5, T6 or DST1, GST1, SST1, etc. has a sufficient current of about 1 μm. Is further reduced.

  Thus, according to the semiconductor evaluation circuit according to the present embodiment, the total leakage current generated in the entire semiconductor evaluation circuit can be reduced, and the characteristics of the transistor under measurement to be selected can be measured with high accuracy. A possible large-scale DMA-TEG can be provided.

Next, the configuration and operation of the semiconductor evaluation circuit according to this embodiment and the method for evaluating the transistor under measurement will be described in detail with reference to FIGS.
FIG. 3 is an overall circuit diagram of a semiconductor evaluation circuit including a circuit for supplying X select signals XS1 to XSm to the column selection lines X1 to Xm and supplying Y select signals YS1 to YSn to the row selection lines Y1 to Yn. . As shown in FIG. 3, the semiconductor evaluation circuit according to this embodiment includes a cell test circuit 20, an X select predecoder PDX, and a Y select predecoder as circuits for supplying an X select signal and a Y select signal. PDY, X-select main decoder MDX and Y-select main decoder MDY are provided. In FIG. 3, it is assumed that n = m = 512. The cell test circuit 20, the X select predecoder PDX, the Y select predecoder PDY, the X select main decoder MDX, and the Y select main decoder MDY constitute a selection signal supply circuit in the present invention.

    The cell test circuit 20 includes a selector control signal (selection control signal) SELCONT, a clock signal CLK, a 9-bit X address signal (column address signal) AX0 to AX8, a 9-bit Y address signal (row address signal) AY0 to AY8, The test signals TEST0 and TEST1 are input, and X address decode signals AXDEC <8: 0> and AXDECB <8: 0> are generated based on these signals and output to the X select predecoder PDX and Y address decode Signals AYDEC <8: 0> and AYDECB <8: 0> are generated and output to the Y-select predecoder PDY. AXDEC <8: 0> is an integrated representation of 9-bit signals AXDEC0 to AXDEC8, and AXDECB <8: 0> is a logical inversion signal of AXDEC <8: 0>. . The same applies to AYDEC <8: 0> and AYDECB <8: 0>.

  FIG. 4 is an internal circuit configuration diagram of the cell test circuit 20. As shown in FIG. 4, the cell test circuit 20 includes a counter circuit CT, 18 selector circuits ST0 to ST17, and 18 decode signal output circuits DC0 to DC17.

  The counter circuit CT receives the selector control signal SELCONT and the clock signal CLK. When the selector control signal SELCONT is “1”, the counter circuit CT performs a count operation in synchronization with the rising edge of the clock signal CLK, and the count result is 18 bits. Counter address signals CA0 to CA17. The counter address signal CA0 of the 0th bit is output to the selector circuit ST0, the counter address signal CA1 of the 1st bit is output to the selector circuit ST1, and similarly, the counter address signal CA17 of the 17th bit is the selector circuit ST17. Is output.

  The selector circuit ST0 receives a SEL signal that is a logical inversion signal of the selector control signal SELCONT, a 0-bit counter address signal CA0, and a 0-bit Y address signal AY0, and outputs a counter according to the level of the SEL signal. Either one of the address signal CA0 and the Y address signal AY0 is selectively output. Specifically, when the SEL signal is “0” (that is, the selector control signal SELCONT is “1”), the counter address signal CA0 is output, and the SEL signal is “1” (that is, the selector control signal SELCONT is “0”). ), The Y address signal AY0 is output.

  The same applies to the selector circuits ST1 to ST8. That is, for example, the selector circuit ST8 receives the SEL signal, the 8-bit counter address signal CA8, and the 8-bit Y address signal AY8, and the counter address signal CA8 and the Y address according to the level of the SEL signal. One of the signals AY8 is selectively output.

  The selector circuit ST9 receives the SEL signal, the 9th bit counter address signal CA9, and the 0th bit X address signal AX0, and outputs the counter address signal CA9 and the X address signal AX0 according to the level of the SEL signal. Either one is selectively output. Specifically, the counter address signal CA9 is output when the SEL signal is “0”, and the X address signal AX0 is output when the SEL signal is “1”.

The same applies to the selector circuits ST10 to ST17. That is, for example, the selector circuit ST17 receives the SEL signal, the 17-bit counter address signal CA17, and the 8-bit X address signal AX8 and inputs the counter address signal CA17 and the X address according to the level of the SEL signal. One of the signals AX8 is selectively output.
Thus, among the counter address signals CA <17: 0> output from the counter circuit CT, CA <8: 0> has a corresponding relationship with the Y address signal AY <8: 0>, and CA <17: 9. > Corresponds to the X address signal AX <8: 0>.

  The decode signal output circuit DC0 receives the output signal of the selector circuit ST1, the logic inversion signal TESTB0 of the test signal TEST0, and the logic inversion signal TESTB1 of the test signal TEST1, and both the TESTB0 signal and the TESTB1 signal are “1”. In this case (that is, when both the test signals TEST0 and TEST1 are “0”), the output signal (either CA0 or AY0) of the selector circuit ST1 is output as the Y-bit decode address AYDEC0 of the 0th bit and its logic The inverted signal is output as AYDECB0. Further, the decode signal output circuit DC0 is “0” as the Y address decode signal AYDEC0 when the test signal TEST0 is “1” (TESTB0 is “0”) and the test signal TEST1 is “0” (TESTB1 is “1”). "Is output (AYDECB0 is also" 0 "). Further, when the test signal TEST1 is “1” (TESTB1 is “0”) regardless of the level of the test signal TEST0, the decode signal output circuit DC0 outputs “1” as the Y address decode signal AYDEC0 (AYDECB0 is also “ 1 ").

  The same applies to the decode signal output circuits DC1 to DC8. That is, for example, the decode signal output circuit DC8 receives the output signal of the selector circuit ST8, the TESTB0 signal, and the TESTB1 and outputs the output signals (CA8 and AY8 of the selector circuit ST8 according to the levels of the TESTB0 signal and the TESTB1 signal). Either), “0” or “1” is output as the Y-bit decode signal AYDEC8 (AYDECB8) of the eighth bit.

  The decode signal output circuit DC9 receives the output signal of the selector circuit ST9, the TESTB0 signal and the TESTB1, and outputs an output signal of the selector circuit ST9 (either CA9 or AX0) according to the levels of the TESTB0 signal and the TESTB1 signal. Either “0” or “1” is output as the X-address decode signal AXDEC0 (AXDECB0) of the 0th bit.

  The same applies to the decode signal output circuits DC10 to DC17. That is, for example, the decode signal output circuit DC17 receives the output signal of the selector circuit ST17, the TESTB0 signal, and the TESTB1 as input, and outputs the output signal (CA17 and AX8 of the selector circuit ST17 according to the levels of the TESTB0 signal and the TESTB1 signal). Either), “0” or “1” is output as the X-bit decode address signal AXDEC8 (AYDECB8) of the eighth bit.

  FIG. 5 shows a truth table representing the relationship between the input signal and the output signal of the cell test circuit 20 as described above. As shown in FIG. 5, when both the test signals TEST0 and TEST1 are “0” and the selector control signal SELCONT is “0”, the cell test circuit 20 is in the normal mode (random access: the first in the normal evaluation mode). Address mode) state, and the input Y address signal AY <8: 0> and X address signal AX <8: 0> are directly used as the Y address decode signal AYDEC <8: 0> (AYDECB <8: 0>) and An X address decode signal AXDEC <8: 0> (AXDECB <8: 0>) is output.

  When both the test signals TEST0 and TEST1 are “0” and the selector control signal SELCONT is “1”, the cell test circuit 20 is in a normal mode (counter access: second address mode in the normal evaluation mode), The counter address signal CA <8: 0> output from the counter circuit CT is output as a Y address decode signal AYDEC <8: 0> (AYDECB <8: 0>), and the counter address signal CA output from the counter circuit CT. <17: 9> is output as the X address decode signal AXDEC <8: 0> (AXDECB <8: 0>).

  When the test signal TEST0 is “1” and TEST1 is “0”, the cell test circuit 20 enters a test mode (all evaluation cell non-selection: second test mode), and the Y address decode signal AYDEC <8: 0. > And X address decode signals AXDEC <8: 0> are all “0” (AYDECB <8: 0> and AXDECB <8: 0> are all “0”).

When TEST1 is “1” regardless of the level of the test signal TEST0, the cell test circuit 20 enters the test mode (all evaluation cell selection: first test mode), and the Y address decode signal AYDEC <8: 0>. The X address decode signals AXDEC <8: 0> are all “1” (AYDECB <8: 0> and AXDECB <8: 0> are all “1”).
The above is the description of the cell test circuit 20, and the description will be continued below by returning to FIG.

  The X select predecoder PDX predecodes the X address decode signals AXDEC <8: 0> and AXDECB <8: 0> input from the cell test circuit 20, and then outputs a predecode signal as a result of the process to the Xdecode signal XX Output to the main decoder MDX for selection. The X select main decoder MDX generates X select signals XS1 to XSm (m = 512) based on the predecode signal input from the X select predecoder PDX, and supplies them to the column selection lines X1 to Xm.

  The Y select predecoder PDY predecodes the Y address decode signals AYDEC <8: 0> and AYDECB <8: 0> input from the cell test circuit 20, and then outputs a predecode signal as a result of the Y decode. Output to select main decoder MDY. The Y select main decoder MDY generates Y select signals YS1 to YSn (n = 512) based on the predecode signal input from the Y select predecoder PDY, and supplies it to the row select lines Y1 to Yn.

  Subsequently, the operation of the semiconductor evaluation circuit including the cell test circuit 20, the X-select predecoder PDX, the Y-select predecoder PDY, the X-select main decoder MDX, and the Y-select main decoder MDY as described above and the measurement target A method for evaluating a transistor will be described.

  FIG. 6 is a timing chart showing the temporal relationship of each signal in the normal mode (test signals TEST0 and TEST1 are “0”). As shown in FIG. 6, when the selector control signal SELCONT is “0” in the normal mode, the Y address signal AY <8: 0> and the X address signal AX <8: 0> are directly decoded by the Y address. The signal AYDEC <8: 0> and the X address decode signal AXDEC <8: 0> are output. That is, in this case, the evaluation cell arranged at a desired XY coordinate (row and column) by freely setting the Y address signal AY <8: 0> and the X address signal AX <8: 0> by the user. Can be selected (random access).

  As shown in FIG. 6, in the normal mode, the counter address signal CA <17: 0> is counted up in synchronization with the rising edge of the clock signal CLK during the period when the selector control signal SELCONT is “1”. Of these counter address signals CA <17: 0>, CA <8: 0> is output as Y address decode signal AYDEC <8: 0>, and CA <17: 9> is X address decode signal AXDEC <8: 0> is output. That is, in this case, in synchronization with the count-up operation of the counter address signal CA <17: 0>, the evaluation of the nth (= 512) th row m (= 512) th column is automatically performed from the first row and first column evaluation cell. The cells are sequentially selected (counter access).

  As described above, in the normal mode, either random access or counter access can be used depending on the level of the selector control signal SELCONT. In either access method, the transistor under measurement of the selected evaluation cell is used. The evaluation method is the same. Further, as can be seen from FIG. 6, in the counter access mode, 18 address input pins AY (8: 0) and AX (8: 0) are not required, so the number of pins for evaluation is reduced. It is effective for this purpose.

FIG. 7 shows a method for evaluating a transistor under measurement in each mode. As shown in FIG. 7, in the normal mode, when the transistor under measurement is an N-channel MOS transistor, the drain voltage VD = 1.0 V is supplied to the main drain force line DF, and the main source force line SF. Is supplied with the source voltage VS = 0V and the gate voltage VG is supplied to the main gate force line GF, thereby driving the measured transistor DUT of the selected evaluation cell. Then, by measuring the drain current ID flowing through the transistor under test DUT when the gate voltage VG is swung in a desired range, the characteristics of the transistor under test DUT are evaluated.
When the transistor under measurement is a P-channel MOS transistor, the drain voltage VD = 0V, the source voltage VS = 1.0V, and the gate voltage VG = 0V are set and the characteristic evaluation is performed.

  On the other hand, as shown in FIG. 7, in the test mode (selection of all evaluation cells), all evaluation cells are selected at the same time. Therefore, all evaluations are performed via the drain force terminal DFP, the gate force terminal GFP, and the source force terminal SFP. A stress test can be performed by applying each voltage to the measured transistor DUT of the cell. Specifically, any one of the gate stress, drain stress A (drain and source stress) and drain stress B (stress only on the drain) shown in FIG. By applying the source voltage VS and the gate voltage VG, voltages are simultaneously applied to all the transistors under test DUT, and a stress test can be performed in a short time.

  Further, as shown in FIG. 7, in the test mode (all evaluation cell non-selection), all the evaluation cells are simultaneously non-selected. Therefore, when the transistor under measurement is an N-channel MOS transistor, the source voltage VS = By setting the drain voltage VD and the gate voltage VG within a desired range by setting 0V, it is possible to measure the total leakage current generated in the entire semiconductor evaluation circuit. When the transistor under measurement is a P-channel MOS transistor, the total leakage current generated in the entire semiconductor evaluation circuit is set by setting the drain voltage VD = gate voltage VG = 0 V and swinging the source voltage VS within a desired range. Can be measured.

  As described above, by using the semiconductor evaluation circuit according to this embodiment, the total leakage current generated in the entire semiconductor evaluation circuit can be reduced in the normal mode, and the characteristics of the transistor under measurement to be selected can be reduced. In addition to being able to measure with high accuracy, in the test mode, it is possible to perform a stress test of all the transistors under measurement in a short time, and to measure the total leakage current generated in the entire semiconductor evaluation circuit Can do.

    Although the embodiment of the present invention has been described in detail, the specific configuration is not limited to this embodiment, and includes design changes and the like within a scope not departing from the gist of the present invention. For example, the number of transistors to be measured is not limited to the above-described example, and the relationship between rows and columns may be interchanged. In the above-described embodiment, three sub-drain force lines, sub-source force lines, and sub-gate force lines are provided in the column direction, and three sub-drain sense lines, sub-source sense lines, and sub-gate sense lines are provided in the row direction. Although the case where the force lines and the sense lines are provided is illustrated, it is not determined whether the force lines and the sense lines are provided in the row direction or the column direction. For example, all the force lines and the sense lines (six lines) are arranged in the row direction or It may be provided on one side in the column direction, or a pair of force line and sense line, a combination of drain force and drain sense, gate force and gate sense, source force and source sense, and two in the row direction , It may be four in the column direction.

In the above embodiment, the case where the completely separated Kelvin sense method is adopted as the internal circuit configuration of the evaluation cell has been described as an example. However, the present invention is not limited to this, and for example, a modification of the evaluation cell as shown in FIG. May be adopted.
As shown in FIG. 8, the evaluation cell C11 ′ in the modification includes a first transistor T10, a second transistor T11, and a third transistor T12 in addition to the transistor under test DUT, which is an N-channel MOS transistor. ing.

  The drain terminal of the measured transistor DUT is connected to the sub-drain force line DF1 and the sub-drain sense line DS1, the source terminal is connected to the sub-source force line SF1 and the drain terminal of the first transistor T10, and the gate terminal is the second terminal. The source terminal of the transistor T11 and the drain terminal of the third transistor T12 are connected.

  The drain terminal of the first transistor T10 is connected to the source terminal of the transistor under test DUT, the source terminal is connected to the sub-source sense line SS1, and the gate terminal is connected to the row selection line Y1. The drain terminal of the second transistor T11 is connected to the sub-gate force line GF1, the source terminal is connected to the gate terminal of the transistor under test DUT, and the gate terminal is connected to the row selection line Y1. The drain terminal of the third transistor T12 is connected to the gate terminal of the transistor DUT to be measured, the source terminal is connected to the ground line, and the logic inversion signal of the row selection line Y1 is input to the gate terminal.

  When the evaluation cell C11 ′ configured in this way is selected, the drain terminal of the transistor DUT to be measured is connected to the main drain force line DF via the sub drain force line DF1, and the sub drain sense line DS1 is connected. The source terminal is connected to the main source force line SF via the sub-drain force line SF1. At this time, since the first transistor T10 and the second transistor T11 are turned on and the third transistor T12 is turned off, the gate terminal of the transistor DUT to be measured is connected to the main gate force via the sub-gate force line GF1. The source terminal is connected to the main source sense line SS via the sub-source sense line SS1.

On the other hand, when the evaluation cell C11 ′ is not selected, only the third transistor T12 is turned on, and the gate terminal of the measured transistor DUT is held at the ground level. The current can be reduced.
As described above, the modified example of the evaluation cell illustrated in FIG. 8 is of a type that does not detect the gate terminal voltage of the transistor DUT to be measured, so even if the sub-gate sense line GS1 and the main gate sense line GS are deleted. good.

It is a circuit block diagram of the semiconductor evaluation circuit which concerns on one Embodiment of this invention. It is supplementary explanatory drawing regarding the semiconductor evaluation circuit which concerns on one Embodiment of this invention. 1 is an overall circuit configuration diagram of a semiconductor evaluation circuit according to an embodiment of the present invention. It is a circuit block diagram of the cell test circuit 20 of the semiconductor evaluation circuit based on one Embodiment of this invention. It is a truth table regarding operation | movement of the cell test circuit 20 of the semiconductor evaluation circuit based on one Embodiment of this invention. It is a timing chart regarding operation of a semiconductor evaluation circuit concerning one embodiment of the present invention. It is a table | surface which shows the evaluation method of the to-be-measured transistor using the semiconductor evaluation circuit based on one Embodiment of this invention. It is a modification of the evaluation cell of the semiconductor evaluation circuit which concerns on one Embodiment of this invention. It is a circuit block diagram of the conventional semiconductor evaluation circuit.

Explanation of symbols

  C11 to Cnm ... evaluation cell, DF ... main drain force line, GF ... main gate force line, SF ... main source force line, DF1 to DFm ... sub drain force line, GF1 to GFm ... sub gate force line, SF1 to SFm ... Sub source force line, DS ... main drain sense line, GS ... main gate sense line, SS ... main source sense line, DS1-DSn ... sub drain sense line, GS1-GSn ... sub gate sense line, SS1-SSn ... sub source Sense lines, X1 to Xm, column selection lines, Y1 to Yn, row selection lines, PSW1 to PSWm, power supply line switching circuits, SSW1 to SSWn, detection line switching circuits, DUTs, transistors under measurement, 10 ... selection circuits, T1 ... 1st transistor, T2 ... 2nd transistor, T3 ... 3rd transistor, T4 ... 4th transistor, T5 ... 1st Transistor, T6 ... sixth transistors, 20 ... cell test circuit, PDX ... X selection predecoder, PDY ... Y select predecoder, MDX ... X select for main decoder, MDY ... Y select-purpose main decoder

Claims (9)

A semiconductor evaluation circuit for evaluating the characteristics of a transistor under measurement,
n × m evaluation cells arranged in a matrix of n rows and m columns (n and m are positive integers) and having a transistor to be measured;
A main source power line for supplying a source voltage for the transistor under measurement;
A sub-source power supply line that is provided for each row or each column and supplies a source voltage to the transistor under measurement of the evaluation cell belonging to each row or each column;
A row selection line provided for each row and for supplying a row selection signal for selecting an evaluation cell belonging to each row;
A column selection line provided for each column and for supplying a column selection signal for selecting an evaluation cell belonging to each column;
In response to a row selection signal belonging to the same row as the sub-source power supply line or a column selection signal belonging to a column, the sub-source power supply line and the main source power supply line A source power line switching circuit for switching connection / disconnection;
A main drain power supply line for supplying a drain voltage for the transistor under measurement;
A main gate power supply line for supplying a gate voltage for the transistor under measurement;
A sub-drain power supply line that is provided for each row or each column and supplies a drain voltage to the transistor under measurement of the evaluation cell belonging to each row or each column;
A sub-gate power supply line that is provided for each row or each column and supplies a gate voltage to the transistor under measurement of the evaluation cell belonging to each row or each column;
In response to a row selection signal belonging to the same row as the sub-drain power supply line or a column selection signal belonging to a column, the sub-drain power supply line and the main drain power supply line are provided corresponding to the sub-drain power supply line. A drain power line switching circuit for switching connection / disconnection;
In response to a row selection signal belonging to the same row as the sub-gate power supply line or a column selection signal belonging to the column, the sub-gate power supply line and the main gate power supply line A gate power line switching circuit for switching connection / disconnection;
A main drain voltage detection line for detecting a drain voltage of the transistor under measurement;
A main source voltage detection line for detecting a source voltage of the transistor under measurement;
A main gate voltage detection line for detecting the gate voltage of the transistor under measurement;
A sub-drain voltage detection line provided for each row or each column, for detecting the drain voltage of the transistor under measurement of the evaluation cell belonging to each row or each column;
A sub-source voltage detection line provided for each row or each column, for detecting the source voltage of the transistor under measurement of the evaluation cell belonging to each row or each column;
A sub-gate voltage detection line provided for each row or each column, for detecting the gate voltage of the transistor under measurement of the evaluation cell belonging to each row or each column;
In response to a row selection signal belonging to the same row as the sub-drain voltage detection line or a column selection signal belonging to a column provided corresponding to the sub-drain voltage detection line, the sub-drain voltage detection line and the main drain voltage A drain detection line switching circuit for switching connection / disconnection with the detection line;
The sub-source voltage detection line and the main source voltage are provided corresponding to the sub-source voltage detection line and according to a row selection signal belonging to the same row as the sub-source voltage detection line or a column selection signal belonging to the column. A source detection line switching circuit for switching connection / disconnection with the detection line;
The sub-gate voltage detection line and the main gate voltage are provided corresponding to the sub-gate voltage detection line and according to a row selection signal belonging to the same row as the sub-gate voltage detection line or a column selection signal belonging to a column. A gate detection line switching circuit for switching connection / disconnection with the detection line;
With
Each of the evaluation cells is
One input terminal is connected to the row selection line belonging to its own row, and the other input terminal is connected to the column selection line belonging to its own column and supplied to the connected row selection line. A selection circuit for outputting a selection signal indicating selection / non-selection of its own transistor under measurement in accordance with a row selection signal and a column selection signal supplied to a column selection line;
A first switch that switches connection / disconnection between the sub-drain power supply line belonging to the same row or column as itself and a drain terminal of the transistor under measurement according to the selection signal;
A second switch for switching connection / disconnection between the sub-source power supply line belonging to the same row or column as the self and a source terminal of the transistor under measurement according to the selection signal;
A third switch for switching connection / disconnection between the sub-gate power supply line belonging to the same row or column as the self and the gate terminal of the transistor under test according to the selection signal;
A fourth switch for switching connection / disconnection between the sub-drain voltage detection line belonging to the same row or column as the self and a drain terminal of the self-measured transistor according to the selection signal;
A fifth switch that switches connection / disconnection between the sub-source voltage detection line belonging to the same row or column as the self and the source terminal of the transistor under measurement according to the selection signal;
A sixth switch for switching connection / disconnection between the sub-gate voltage detection line belonging to the same row or column as itself and the gate terminal of the transistor under measurement according to the selection signal;
Have
A selection signal supply circuit for supplying a column selection signal to each column selection line and supplying a row selection signal to each row selection line;
The selection signal supply circuit has a selection control signal, a clock signal, a column address signal, a row address signal, and a test signal as inputs,
According to the state of the test signal, the mode shifts to an operation mode for evaluating the characteristics of the transistor under measurement.
A semiconductor evaluation circuit. Each of the evaluation cells is
The sub-drain power supply line belonging to the same column as the self and the sub-drain voltage detection line belonging to the same row as the self are connected to the drain terminal of the transistor under test;
The sub-source power line belonging to the same column as the self is connected to the source terminal of the transistor under test;
Instead of the selection circuit, an input terminal is connected to the row selection line belonging to its own row, and selection / non-selection of its own transistor under measurement according to a row selection signal supplied to the connected row selection line A gate selection circuit that outputs a gate selection signal representing the same to the gate terminal of the transistor under test;
Instead of the first to sixth switches, switching between connection / disconnection of the sub-source voltage detection line belonging to the same row as itself and the source terminal of the transistor under measurement is switched according to the row selection signal. A seventh switch and an eighth switch that switches connection / disconnection between the sub-gate power supply line belonging to the same column as itself and the gate terminal of the transistor under test according to the row selection signal; Have
Not including the main gate voltage detection line, the sub-gate voltage detection line, and the gate detection line switching circuit;
The semiconductor evaluation circuit according to claim 1. The operation mode is any one of a normal evaluation mode, a first test mode, and a second test mode,
In the normal evaluation mode, a first address mode that generates the column selection signal and the row selection signal based on the column address signal and the row address signal according to the state of the selection control signal, and the clock signal Performing a count operation in synchronization, and switching between the second address mode for generating the column selection signal and the row selection signal based on the count result;
In the first test mode, the column selection signal and the row selection signal for selecting all evaluation cells are generated,
In the second test mode, the column selection signal and the row selection signal for deselecting all evaluation cells are generated.
The semiconductor evaluation circuit according to claim 1, wherein the semiconductor evaluation circuit is a semiconductor evaluation circuit. A semiconductor evaluation method for evaluating the characteristics of a transistor under measurement,
Using the semiconductor evaluation circuit according to any one of claims 1 to 3 ,
A column selection signal for selecting the evaluation cell to be evaluated is supplied to the column selection line belonging to the column of the evaluation cell to be evaluated, and the evaluation cell to be evaluated is selected to the row selection line belonging to the row. A first step of supplying a row selection signal for
A second step of supplying a desired source voltage to at least the main source power line;
A third step of evaluating the characteristics of the transistor under measurement by measuring the current flowing through the main source power line;
The semiconductor evaluation method characterized by having. A semiconductor evaluation method for evaluating the characteristics of a transistor under measurement,
Using the semiconductor evaluation circuit according to any one of claims 1 to 3 ,
A column selection signal for selecting the evaluation cell to be evaluated is supplied to the column selection line belonging to the column of the evaluation cell to be evaluated, and the evaluation cell to be evaluated is selected to the row selection line belonging to the row. A first step of supplying a row selection signal for
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
A third step of evaluating the characteristics of the transistor under measurement by measuring the current flowing through the main source power line;
The semiconductor evaluation method characterized by having. A semiconductor evaluation method for evaluating the characteristics of a transistor under measurement,
Using the semiconductor evaluation circuit according to claim 3 ,
When performing characteristic evaluation using the first address mode of the normal evaluation mode, the state of the test signal input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the selection signal supply circuit The state of the selection control signal input to the first address mode is set to a state corresponding to the first address mode, and the column address signal and the row address signal representing the position of the evaluation cell to be evaluated are input to the selection signal supply circuit. And the process of
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
A third step of evaluating the characteristics of the transistor under measurement by measuring the current flowing through the main source power line;
The semiconductor evaluation method characterized by having. A semiconductor evaluation method for evaluating the characteristics of a transistor under measurement,
Using the semiconductor evaluation circuit according to claim 3 ,
When performing characteristic evaluation using the second address mode of the normal evaluation mode, the state of the test signal input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the selection signal supply circuit A first step of setting a state of a selection control signal input to the state corresponding to the second address mode;
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
A third step of evaluating the characteristics of the transistor under measurement by measuring the current flowing through the main source power line;
The semiconductor evaluation method characterized by having. A semiconductor evaluation method for evaluating the characteristics of a transistor under measurement,
Using the semiconductor evaluation circuit according to claim 3 ,
When performing the characteristic evaluation using the first test mode, a first step of setting a state of the test signal input to the selection signal supply circuit to a state corresponding to the first test mode;
A desired drain voltage is supplied to the main drain power supply line, a desired source voltage is supplied to the main source power supply line, and a desired gate voltage is supplied to the main gate power supply line. A second step of testing,
The semiconductor evaluation method characterized by having. A semiconductor evaluation method for evaluating the characteristics of a transistor under measurement,
Using the semiconductor evaluation circuit according to claim 3 ,
When performing characteristic evaluation using the second test mode, a first step of setting a state of a test signal input to the selection signal supply circuit to a state corresponding to the second test mode;
A leak generated in the entire semiconductor evaluation circuit by supplying a desired drain voltage to the main drain power supply line, supplying a desired source voltage to the main source power supply line, and supplying a desired gate voltage to the main gate power supply line. A second step of measuring the sum of currents;
The semiconductor evaluation method characterized by having.

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