JPH01183148A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the disposition of an exclusive use testing terminal or to obviate the necessity of externally setting complicated input conditions by providing a power source voltage detector and an operation confirmation signal generator activated or nonactivated upon reception of a control signal from the detector. CONSTITUTION:A power source voltage detector 1 detects the level of a power line, and is connected through a control signal 2 to a testing circuit activation signal generator 3, thereby controlling the activation/nonactivation of the generator 3. A testing circuit activation signal 4 generated from the generator 3 is a signal for controlling the setting/cancelling a test mode. The signal is input to an internal circuit 5, and the circuit 5 is tested by an input/output signal at the time of setting the test mode. Thus, since an exclusive use testing terminal is not required, the number of package terminals of a semiconductor integrated circuit can be suppressed to its minimum limit, or since complicated conditions are not necessarily set to the input terminal in the unit inspection of the integrated circuit, its inspection efficiency can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to the configuration of an operation check circuit (hereinafter referred to as a test circuit) for a semiconductor integrated circuit.

[Conventional technology]

Conventionally, when testing the circuit functions of semiconductor integrated circuits, a method has been used to set special test conditions (hereinafter referred to as test modes) in order to improve the failure detection rate and shorten the test pattern for function confirmation. However, in this case, the circuit configuration is such that a test mode is set, such as by using a dedicated test terminal or by generating a test circuit activation signal based on a logic combination of input terminals.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit described above, when setting a test mode, a dedicated test terminal is used or a test activation signal is generated by a logic combination of input terminals to set the test mode. However, there are drawbacks such as the need to arrange dedicated test terminals unrelated to actual operation, or the need to set complicated input conditions from the outside.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a power supply voltage detection circuit and an operation confirmation signal generation circuit that is activated or deactivated in response to a control signal from the power supply voltage detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The semiconductor integrated circuit in this embodiment is a power supply voltage detection circuit 1.
．． It is composed of a test circuit activation signal generation circuit 3 and an internal circuit 5. A power supply voltage detection circuit 1 detects the level of a power supply line, is connected to a test circuit activation signal generation circuit 3 via a control signal 2, and controls activation/deactivation of the test circuit activation signal generation circuit 3. The test circuit activation signal 4 generated from the test circuit activation signal generation circuit 3 is a signal for controlling the setting/cancellation of the test mode, and is input to the internal circuit 5, and when the test mode is set, the internal circuit is Can perform circuit tests.

Next, the operation of this embodiment will be explained with reference to FIG.

FIG. 2 shows the timing of the power supply voltage and the test circuit activation signal. In this embodiment, a +5V power supply is used as the power supply voltage of the semiconductor integrated circuit, and the test circuit activation signal 4 remains inactive (+i L ++ level) while the +5V power supply voltage is supplied. The integrated circuit performs normal operation.

When the power supply voltage rises and is set to a preset voltage value - for example 7■, the applied power supply voltage reaches 7V, maintains a state of 7■ or higher for a certain period of time, and then decreases to 5V, the power supply voltage detection circuit The test circuit activation signal generation circuit 3 operates in response to the control signal 2 output from the test circuit activation signal 1, and the test circuit activation signal 4 is activated (“L II → II HI+ level”). In this state, the test circuit is activated. Since the signal 4 holds the "H" level compared to the "L" level in the normal mode, the operating mode conditions of the internal circuit 5 can be set using this signal.

Next, the power supply voltage rises again, exceeds 7V, is maintained for a certain period of time, and then falls to 5V again.The power supply voltage detection circuit 1 generates a control signal 2, and this signal causes the test circuit activation signal generation circuit 3 to operate. The test circuit activation signal 4 is deactivated (from "H" to "L" level). When the test circuit activation signal 4 becomes 'L' level, the test mode set for the internal circuit 5 is canceled and the normal operation mode returns.

The above-mentioned switching between the operation mode and the test mode can be performed periodically by changing the power supply voltage in a pulse manner from 5V to 7V to 5V.

〔Effect of the invention〕

As described above, according to the present invention, a semiconductor integrated circuit is provided with a power supply voltage detection circuit, and the test mode can be set or canceled depending on the level of the applied power supply voltage. Therefore, there is no need for a dedicated test terminal to control the setting/cancellation of the test mode, so the number of package terminals for semiconductor integrated circuits can be minimized. Since there is no need to set conditions, there is an effect that the inspection efficiency can be improved. Furthermore, since the test mode is set by increasing the power supply voltage in a pulse manner above the operating voltage, there is no need to maintain the power supply voltage at a high level after setting the test mode. Tests that vary within conditions are possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a timing diagram. ■...Power supply voltage detection circuit, 2...Control signal, 3...Test circuit activation signal generation circuit,
4...Test circuit activation signal, 5...
internal circuit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] In a semiconductor integrated circuit, there is a circuit that detects the voltage applied to the power supply terminal, and an operation confirmation signal generation circuit that receives a control signal from the power supply voltage detection circuit and switches part or all of the internal circuit to a specific operating state. A semiconductor integrated circuit characterized by comprising: