JPH10242397A - Cmos integrated circuit device and testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS integrated circuit and a testing method that allow an accurate DC leakage current test with a simple configuration and achieve a stable operation. SOLUTION: A CMOS integrated circuit is divided into a plurality of circuit blocks, a power supply line 5 and a power supply terminal 4 are provided corresponding to them, at the same time a MOS switch for connecting the above power supply lines between the above adjacent circuit blocks 18 and a control circuit for performing the switch control are provided, and the above MOS switch is turned off by the above control circuit in a DC testing mode and the current supply line 5 of the specific circuit block 8 is separated from the power supply line 5 of another circuit block 18 being adjacent to it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit device and a test method and, more particularly, to a technology effective for a DC current leak test technology of a CMOS integrated circuit device.

[0002]

2. Description of the Related Art With respect to a DC leakage current test of a CMOS integrated circuit device, ISSCC
(International Solid-State Circuits Conferrenc
e)), pp.88, 1994. In the DC leakage current test, a semiconductor integrated circuit is divided into a plurality of circuit blocks, and a power supply line is separated for each circuit block, and a leakage current is measured for each circuit block.

[0003]

With the advance of semiconductor integrated circuit technology, miniaturization of elements has been promoted, and the leakage current has increased accordingly. The circuit scale increases with the miniaturization of the elements, and the DC leakage current increases with the increase in the number of elements as a whole. When the leakage current increases in this way, it becomes impossible to distinguish whether the measured current is due to the leakage current or a short circuit in the Iddq (DC leakage current) test, and whether the semiconductor integrated circuit is good or bad. Can no longer be diagnosed.

In order to solve this, as described above, the CMO
When the S integrated circuit is divided into circuit blocks, and a power supply line and a power supply terminal are provided for each of the circuit blocks and the leak current is measured for each circuit block, the power supply impedance increases during the original operation of the CMOS integrated circuit. At a position away from the terminal, there is a problem that power supply noise due to the power supply impedance cannot be ignored.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS integrated circuit device and a test method which realize a highly accurate DC leakage current test with a simple configuration and realize stable operation. The above and other objects and novel techniques of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a CMOS integrated circuit is divided into a plurality of circuit blocks, a power supply line and a power supply terminal are provided correspondingly, and a MOS switch for interconnecting the power supply lines between the adjacent circuit blocks and a MOS switch therefor. A control circuit for performing switch control is provided,
In the DC test mode, the control circuit controls the MOS
By turning off the switch, a power supply line of a specific circuit block is separated from a power supply line of another circuit block adjacent thereto.

[0007] The outline of another typical invention disclosed in the present application will be briefly described as follows. The CMOS integrated circuit is divided into a plurality of circuit blocks each having N rows and M columns, and a power supply line and a power supply terminal are provided corresponding to each of the circuit blocks, and the power supply is provided between the adjacent circuit blocks. A MOS switch for connecting the supply lines to each other is provided, and a gate of a first group of MOS switches, which is divided into N rows among the MOS switches, is connected to a first control line group, and a second group is divided into M columns.
The gates of the group of MOS switches are connected to a second control line group, and the first and second control lines are controlled by the control circuit in a DC test mode.
A switch control signal to be supplied to the group of control lines is formed, and a DC test mode is simultaneously performed for each of the M circuit blocks for each column. When the value is exceeded, one circuit block is selected from the M blocks.

[0008]

FIG. 1 shows a CMOS according to the present invention.
FIG. 1 is a schematic block diagram for explaining an embodiment of a power supply line of an integrated circuit device. In this embodiment, although not particularly limited, a circuit formed on one semiconductor substrate 1 is divided into nine blocks, and a power supply terminal 4 and a power supply line 5 are provided for each block. In order to reduce the power impedance during normal operation while performing the DC leakage test as described above, the power supply lines 5 of each circuit block are connected to each other adjacent to each other by the switch MOSFET 2. .

By providing the switch MOSFET 2 as described above, when the switch MOSFET is turned on, the power supply lines 5 are formed in a mesh on one semiconductor substrate 1. Although not particularly limited, the gate of the switch MOSFET 2 is commonly connected to the control lines 7 # 1 and 7-2.
That is, the switches MOSFE arranged side by side in the horizontal direction
The gate of T2 is connected to a control line represented by the control line 7-1, and is connected to a switch MOS arranged in the vertical direction.
The gate of the FET2 is connected to a control line represented by the control line 7 # 2. These control lines 7-1 and 7 # 2 are:
The switch M according to the DC leakage test and the normal operation
A control signal generated by a control circuit 6 that performs switch control of the OSFET 2 is commonly supplied.

Although the control circuit 6 is not particularly limited,
In the DC test mode, the switch MOSFET 2 responds to a control signal supplied from an appropriate control terminal.
Is formed and supplied to the control lines 7-1 and 7-2 and the like. As a result, in the test mode, all the switch MOSFETs 2 are turned off. Therefore, power supply lines 5 are separated corresponding to individual circuit blocks. For this reason, for example, in the circuit block 8 where the leak test is performed, the switch MOSFET 2 is in the off state, and therefore, the leak current flowing to the corresponding power supply terminal 4 is only that generated in the circuit block 8, and the power supply It is possible to distinguish the short-circuit current from the short-circuit current due to the short-circuit of the wire, and it is possible to perform such a DC test. Hereinafter, similarly, in the remaining eight circuit blocks, the DC leak current Iddq can be measured in circuit block units as described above.

The control circuit 6 forms a control signal for turning on the MOSFET 2 in the normal operation mode, and supplies the control signal to the control lines 7-1, 7 # 2 and the like. As a result, all the switch MOSFETs 2 are turned on, and the power supply lines 5 are connected to each other between the circuit blocks. For this reason, in each circuit block, in a circuit provided at the far end with respect to the corresponding power supply terminal 4, the current from the power supply terminal 4 of another circuit block adjacent thereto via the switch MOSFET 2 Supply is also performed, and the power supply impedance can be significantly reduced. In other words, ignoring the on-resistance of the MOSFET 2 and simplification, in a configuration in which the operating voltage is supplied from two circuit blocks through almost the same power supply line, the power supply impedance is reduced by half.
If it is supplied from three circuit blocks, it is reduced to １ ／, and if it is supplied from four circuit blocks, it is reduced to ４.

In the state where the power supply lines 5 are connected to each other in a mesh pattern as described above, the power supply impedance in a unit circuit such as a gate circuit provided at any position in each circuit block depends on the power supply line in the mesh form. The lines provide a generally uniform low power supply impedance. Therefore, CMOS
In a gate circuit or the like, when the level of the input signal changes, the current supply corresponding to the through current flowing when the output signal changes and the charge-up current of the load capacitance is sufficiently performed. Can be suppressed to a low level, and the operation of the CMOS gate circuit and the like can be stabilized.

The process variation of the leak current in the CMOS integrated circuit device is relatively large. That is, when the circuit block is divided as described above, it is necessary to determine the size of the circuit block in consideration of the worst case of the process variation. For such a worst case, the average leakage current value is much smaller. Therefore, the inventors of the present invention perform a test in a plurality of circuit blocks in order to shorten the test time, and individually test the circuit blocks only when the leak current exceeds a reference value in such a circuit block. I thought that.

FIG. 2 is a schematic block diagram of another embodiment for explaining a power supply line of a CMOS integrated circuit device according to the present invention and a test method thereof. In this embodiment, although there is no particular limitation for improving the efficiency of the test as described above, the circuit blocks formed by dividing the semiconductor substrate 1 are divided into three rows and three columns. The gates of the switch MOSFETs that divide the circuit block on a row-by-row basis have switch MOSFs arranged side by side in the horizontal direction.
The gates of ET2 are connected to control lines 7-1a and 7-1b, respectively. The gates of the switch MOSFETs 2 that are arranged in the vertical direction are connected to the gates of the switch MOSFETs that divide the circuit block in units of columns.
2a and 7-2b.

A total of four control lines 7-1a to 7-2b as described above are connected to the control circuit 6 in order to separate circuit blocks in units of rows or columns.
, Four control signals are formed and supplied to each of them. Thus, for example, in the test operation mode, the control circuit 6 controls the control line 7-2 extended in the column direction.
a, and the control signal supplied to the control line 7-2b is set to the off level of the switch MOSFET2, and the control lines 7-1a and 7 # b extending in the row direction are set to the on level of the switch MOSFET2.

In the above state, the power supply lines 5 of only the three circuit blocks arranged in the column direction as in the circuit block group 8 'are connected to each other, and the three circuit blocks are collectively subjected to the leak current test. Will be possible. Those that passed the leak current test for each of the three circuit blocks inevitably passed the leak test for the unit circuit block. Move to test. When a circuit block corresponding to the worst case as described above exists in the circuit block group 8 ', the leak current value is set to a reference value or more. At this time, control lines 7-1a and 7-1b are connected to switch MOS.
The FET 2 is turned off, and a leak test is performed for each individual circuit block as in the embodiment of FIG.

It is considered that the distribution of the leak current is the average and the one corresponding to the worst case is less than about several percent of the whole. . Therefore, in terms of the total number of tests, by performing the primary test for each of the plurality of circuit blocks as described above, in most CMOS integrated circuit devices, only the primary test is required to be performed three times. Thus, a significant reduction in test time can be expected.

FIG. 3 shows a specific circuit diagram of the switch MOSFET 2 used in the embodiment shown in FIGS. In this embodiment, as the switch MOSFET 2,
N-channel MOSFET Q1 and P-channel M
A CMOS switch in which OSFET Q2 is connected in parallel is used. This CMOS switch is provided between a power supply line 5A corresponding to one circuit block and a power supply line 5B corresponding to another circuit block. A control signal from the control line 7-1 is supplied to the gate of the N-channel MOSFET Q1.
In order to simultaneously turn on / off the P-channel MOSFET Q2 with respect to TQ1, an inverter circuit I
The control signal of the control line 7-1 is inverted via V and supplied to the gate of the P-channel MOSFET Q2.

If the level of the control line 7-1 is a high level such as a power supply voltage, the N-channel MOSFET Q1
Is turned on, and the output signal of the inverter circuit IV is set to the low level.
TQ2 is also turned on. Conversely, if the level of the control line 7-1 is a low level such as the ground potential of the circuit, the N-channel MOSFET Q1 is turned off, and the output signal of the inverter circuit IV is set to the high level. The type MOSFET Q2 is also turned off. Since the semiconductor integrated circuit device of this embodiment is based on the above-described CMOS circuit, the switch MOSF
The ET also has no particular problem in being constituted by the CMOS circuit as described above, whereby the power supply lines can be connected with a low on-resistance value.

The functions and effects obtained from the above embodiment are as follows. That is, (1) a CMOS integrated circuit is divided into a plurality of circuit blocks, a power supply line and a power supply terminal are provided correspondingly, and a MOS for interconnecting the power supply lines between the adjacent circuit blocks is provided. A switch and a control circuit for controlling the switch are provided. In the DC test mode, the MOS switch is turned off by the control circuit so that a power supply line of a specific circuit block is supplied to another circuit block adjacent thereto. By separating from the line, an effect is obtained that the power supply impedance can be lowered by the ON state of the switch MOSFET during normal operation to stabilize the operation while enabling the leak current test.

(2) The plurality of circuit blocks are divided into a plurality of N rows and M columns, and the control circuit includes: a first control line group divided every N rows; A second control line group to be divided, and a control signal corresponding to each of the gates of the MOS switch divided for each row and the gate of the MOS switch divided for each column. Since the test can be performed, the effect that the test can be made more efficient is obtained.

(3) By using a CMOS switch in which an N-channel MOSFET and a P-channel MOSFET are connected in parallel as the switch, the power supply lines can be connected with low on-resistance and without level loss. The effect that it can be obtained is obtained.

(4) The CMOS integrated circuit is divided into a plurality of circuit blocks each of which is divided into N rows and M columns, and a power supply line and a power supply terminal are provided for each of these circuit blocks. A MOS switch for connecting the power supply lines to each other between circuit blocks is provided, and a first group of MOs of the MOS switch divided into N rows.
The gate of the S switch is connected to the first control line group, and the gate of the second group of MOS switches that are divided for each M columns is connected to the second control line group. A switch control signal to be supplied to the first and second control line groups is formed, and a DC test mode is simultaneously performed for each of the M circuit blocks for each column. And when one circuit block is selected from the M blocks when the reference value is exceeded, the test time can be shortened.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. The MOS switch may be composed of only a P-channel MOSFET or an N-channel MOSFET. When an N-channel MOSFET is used and the operating voltage is a positive voltage, a charge pump circuit is provided to raise the high level of the control voltage supplied to the control line to a level higher than the threshold voltage of the power supply voltage. The N-channel MOSFET may be turned on. The control circuit 6 for controlling the switch MOSFET may be composed of only external terminals or test pads. That is, the switch MOSF is directly supplied from the external terminal or the test pad for the test operation.
The ET on / off level may be supplied.

The circuit blocks need not be sized to a constant geometric size. For example, a CMOS integrated circuit device is used for an arithmetic circuit, a memory circuit, an A / D conversion circuit, a D / A
When the power supply line is divided into functional blocks such as a conversion circuit, an input / output interface circuit, and a signal conversion circuit, the power supply line may be divided by configuring a circuit block with one or a plurality of functional units. Therefore, the plurality of circuit blocks need not always be regularly divided like rows and columns, but are appropriately divided according to the circuit configuration. The present invention can be widely used for a CMOS integrated circuit device and a test method.

[0026]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described.
It is as follows. That is, a CMOS integrated circuit is divided into a plurality of circuit blocks, a power supply line and a power supply terminal are provided corresponding to each of the plurality of circuit blocks, and the power supply lines are connected to each other between the adjacent circuit blocks.
A switch and a control circuit for controlling the switch are provided.
By turning off the OS switch and separating a power supply line of a specific circuit block from a power supply line of another circuit block adjacent thereto, a leak current test can be performed and the switch MOSFET is turned on during normal operation. Accordingly, the power supply impedance can be lowered and the operation can be stabilized.

The CMOS integrated circuit is divided into a plurality of circuit blocks each having N rows and M columns, and a power supply line and a power supply terminal are provided corresponding to each of the circuit blocks. And a MOS switch for connecting the power supply lines to each other is provided.
The gates of the first group of MOS switches that are divided for every N rows of the switches are connected to the first control line group, and the gates of the second group of MOS switches that are divided for each of the M columns are connected to the second control line group. Connected, a control circuit forms a switch control signal to be supplied to the first and second control line groups in the DC test mode, and performs a DC test mode on M circuit blocks simultaneously for each column; When the value does not exceed the value, the test is performed in M units.
By selecting one circuit block, the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of a power supply line of a CMOS integrated circuit device according to the present invention.

FIG. 2 is a schematic block diagram for explaining another embodiment and a test method of a power supply line of the CMOS integrated circuit device according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a switch used in the CMOS integrated circuit device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Switch MOSFET, 4 ... Power supply terminal, 5 ... Power supply line, 6 ... Control circuit, 7 # 1a
7-2b: control line, 8: circuit block, 8 ': circuit block group.

Claims (4)

[Claims] A plurality of divided circuit blocks; a power supply line and a power supply terminal provided corresponding to each of the circuit blocks; and a power supply line interconnected between the adjacent circuit blocks. And a control circuit for performing switch control of the MOS switch. In the DC test mode, the control circuit connects a power supply line of one or more specific circuit blocks to another circuit block adjacent thereto. The above M
A CMOS integrated circuit device, wherein the OS switch is turned off and the MOS switch is turned on in a normal operation mode. 2. The control circuit according to claim 1, wherein the plurality of circuit blocks are divided into a plurality of N rows and M columns, and the control circuit includes: a first control line group divided every N rows;
A second control line group divided for each of the M columns, and a control signal corresponding to each of the gates of the MOS switch divided for each row and the gate of the MOS switch divided for each column; 2. The CMOS according to claim 1, wherein
Integrated circuit device. 3. The switch is an N-channel MOS.
3. The CMOS integrated circuit device according to claim 1, wherein the CMOS integrated circuit device comprises a CMOS switch in which an FET and a P-channel type MOSFET are connected in parallel. 4. A circuit block divided into a plurality of N rows and M columns, a power supply line and a power supply terminal provided corresponding to each of the circuit blocks, and A MOS switch for connecting the power supply lines to each other; a first control line group for connecting the gates of the first group of MOS switches for every N rows in common; and a second control line for each of the M columns A second control line group in which the gates of a group of MOS switches are connected in common; and a control circuit for forming a switch control signal to be supplied to the first and second control line groups. A method for testing a leakage current of an integrated circuit device, comprising:
A leakage current test is performed in a state where the power supply lines of a plurality of circuit blocks are connected to the M circuit blocks in each of the columns at the same time according to the control signal supplied to the control line group. Is exceeded, the MOS switches of the second group are selectively turned off so that one circuit block is selected from M by a control signal supplied to the second control line group, and the leakage current test is performed. And when the leak current does not exceed the reference value, the process shifts to a test of M circuit blocks corresponding to the next column by a control signal control signal supplied to the first control line group. Of testing a CMOS integrated circuit device.