JPS62150600A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a large capacity mask ROM or the like executing screening in a short time by providing at least one memory array and an address selection circuit capable of selecting all word lines of the memory array. CONSTITUTION:A memory array M-ARY 2 similar to a memory array M-ARY1 is provided to the left side of an X decoder circuit XDCR and a Y decoder circuit is provided to the M-ARY 2. In using sense amplifiers SA0, SA1 in common to the left side M-ARY 2, the common data line of the M-ARY 1 is prolonged up to the memory array M-ARY 2, and any of the Y decoder circuits form a data line selection signal to the M-ARY 1 and M-ARY 2. The M-ARY is divided in this way and one data line and word line is decreased and the number of storage MOSFETs connected to the line is reduced, then the operation is quickened. Thus, the aging processing of all memory cells is realized in a short period.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a memory device, and for example, a semiconductor mask R on which writing is performed by ion implantation.
It relates to a technology that is effective for use in OM (read-only memory).

[Background Art] As the storage capacity and integration of mask ROMs increases, it has become difficult to test products or semi-finished products in the production process and to select good and defective products, so-called screening. In other words, it takes a huge amount of time to externally specify the addresses of all memory cells and perform aging processing, and since the aging time for one memory cell cannot be increased, there are problems such as insufficient screening. (For semiconductor mask ROM, for example, see Hitachi IC published by Hitachi, March 1985.
(See pages 242 to 265 of "Memory Data Book").

[Purpose of the invention]

An object of the present invention is to provide a large-capacity mask ROM, etc., which can be subjected to aging screening etc. in a short time during the production process.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by providing a test pad to force all word lines to a selected state for an address decoder that selects and specifies word lines of a memory array using an externally supplied address signal, it is possible to This method performs screening by aging all memory cells in a short period of time.

[Embodiment] FIG. 2 shows a semiconductor mask ROM to which this invention is applied.
A circuit diagram of an embodiment of the main part is shown.

The mask ROM described in this embodiment is formed on a single semiconductor substrate such as single crystal silicon by a known 0M03 circuit manufacturing technique, although this is not particularly limited. Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MO
A 3FET is made of polysilicon formed on the surface of a semiconductor substrate, such as a source region, a drain region, and a thin gate insulating film formed on the surface of the semiconductor substrate (channel region) between the source region and the drain region. It consists of a gate electrode that looks like this. P channel MO3
The FET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MO3FETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MO5FET formed thereon.

The memory array M-ARYI includes a plurality of word lines WO to Wn extending in the horizontal direction, and a plurality of data lines (bit lines or deshift lines) D00 to DO1, etc. extending in the vertical direction. MO5FE for storage at the intersection with
TQm is formed.

Although not particularly limited, in this embodiment, a common source line cs runs parallel to a pair of data lines DOO and DIO in order to reduce power consumption.

is provided. The common source line C8O is commonly connected to the sources of storage MOS FETQm whose drains are respectively connected to the corresponding pair of data lines DOO and Dlo. Furthermore, the drains of the storage MOS FETs whose sources are coupled to the adjacent common source line CSI are commonly connected to the data line D10. Other storage MOS F corresponding to the above common source line cs1
The drain of ET is connected to data line DOI. This data line DIO has a storage MO3F whose source is coupled to a common source line C32 provided next to it.
The drains of ET are coupled together.

In this way, the data lines and the common source lines are alternately arranged and, except for the data line DOO at the end, are commonly connected to the drains of the storage MO3FETs assigned different Y addresses. In other words, the data line DOO is connected to the Y gate (
It is coupled to the common data line CDO via MO3FETQ5 forming a column switch). The corresponding common source line CSO is coupled to the ground potential point of the circuit via the switch MO3FETQ6. Further, the other data line D10 corresponding to the common source line C8O is connected to the common data line C through the MO3FETQ7 forming a Y gate.
Coupled to DI. These switches MO5FETQ5
A selection signal YO formed by a Y decoder YDCR, which will be described later, is commonly supplied to the gates of Q7.

The data line DIO is also coupled to the common data line CDI via an MO5FETQ8 forming a Y gate to which another Y address (Y2) is assigned. A common source line C3I arranged on the right side of the data line DIO is coupled to the ground potential point of the circuit via a switch MOS FETQ9. The data line DOI arranged on the right side of this common source line C5I is a MOS that constitutes a Y gate.
Coupled to common data line CDO via FETQIO.

The selection signal Y1 formed by the Y decoder YDCR is supplied to the gates of these MO3FETs Q8 to QIO. Hereafter, by repeating the same circuit pattern, the data line, common data line and switch MO3FET are connected.
is formed.

The gates of the storage MOS FETs arranged in the same row are respectively coupled to the corresponding word lines WO to Wn. The word lines WOwWn are each supplied with a selection signal formed by an X decoder XDCR, which will be described later.

Although not particularly limited, a load MOSFETQ
I to Q3 are provided. Although not particularly limited, these MOS FETQ1 to Q3 act as resistance elements having desired conductance by supplying a predetermined bias voltage VB to their gates.

An X address signal AX consisting of multiple bits supplied from an external terminal is supplied to an X address buffer XADB,
A complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

These complementary address signals are decoded by an X decoder XDCR, which forms a selection signal for one word line. In this example, the above
The address buffer XADB and the X decoder XDCR are collectively expressed as XADB-DCH.

In addition, when performing tests such as aging, test pad P
When a high-level test signal is input through TEST, the X address buffer XADB sets the X address decoder XDCR to the all selection level and all word lines to the selected state, as will be described later.

A Y address signal AY consisting of multiple bits supplied from an external terminal is supplied to a Y address buffer YADB,
A complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

These complementary address signals are decoded by Y decoder YDCR to form selection signals for two data lines.

In this embodiment, the above Y address buffer YADB and Y
The decoder YDCR is collectively expressed as YADB-DCR. For example, by Y decoder YDCR,
When the selection signal YO is set to high level, the switch MO3
Since FETs Q5 to Q7 are turned on, the data line D
Two storage MOS F E coupled to OO and Dlo
The stored information of T is read out to common data lines CDO and CDI. At this time, the data line to which the selected word line is connected is a storage MO5FET connected to another data line.
As a result of the switch MO3FET provided on the corresponding common source line being turned off, the memory MO3
No current flows through the FET. Due to this selection operation of the common source line, the storage MOS FET provided between the selected data line DIO and the common source line C3I is also rendered inactive. Therefore, the data line DIO is set to a potential according to the stored information of the storage MOS FET provided between it and the common source line C3O.

Further, when the selection signal Y1 is set to high level by the Y decoder YDCR, the switch MO3FE T Q,8
~ Since QIO is turned on, the data lines DIO and D
The storage information of the two storage MO3FETs coupled to OI is connected to the common data line CD1. Read out to CDO. At this time, similarly to the above case, the selected data line DIO
and a common source line C8O, and a storage MOS FET provided between the data line D01 and the common source line C82.
is rendered inoperative because the switches MO3FETs Q6 and Qll corresponding thereto are turned off. Therefore, the data lines DIO and DOI are connected to two memory MOSs provided between each common source IC3I.
The potential is set according to the information stored in the FET.

Due to the configuration of the memory array M-ARYI as described above, even though a large number of storage MO3FETs are connected to one word line, the storage information is transmitted only to the storage MO3FET selected by the data line. Since only the current according to the current flow flows, it is possible to reduce power consumption. In addition, by selection operation according to the Y address of the common source line,
Memory M with different Y addresses assigned to data lines
Since O3' FET can be connected, memory MOS F
ETs can be placed in high density.

The storage MO3FETQm is made to have different threshold voltages according to storage information. MO3FE for storage where logic “1” is written, although it is not particularly layered.
T is relatively reduced by introducing impurities of the same conductivity type as that of the semiconductor substrate into the semiconductor substrate (channel region) under the gate electrode by selective ion implantation using an appropriate masking method. It is made to have a high threshold voltage. The writing process using such an ion implantation technique is performed in the final process of a semiconductor integrated circuit formed on a semiconductor wafer, for example, by an ion implantation process through the gate electrode of a MOSFET, which is a memory cell, after data lines made of aluminum are formed. Implemented.

The output signal from the memory cell read out to the common data line CDO by selecting the data line is given as one input to the sense amplifier SAO. The other input of the sense amplifier SAO receives read signals from a storage MO3FET with a relatively low threshold voltage and a storage MOSFET with a relatively high threshold voltage in the memory array, and low level/ A reference voltage Vref set to approximately an intermediate level between high levels is applied. The output signal of this sense amplifier SAO is connected to a data output buffer DO (not shown).
It is sent out through B. In addition, in order to define the level of the output signal during the non-operating time of the sense amplifier SAO,
A sense amplifier operation timing signal C8 is provided.

That is, during the non-operating time when the operation timing signal C8 is at a low level, its output is fixed at a high level such as the power supply voltage Vcc. The reason for this is that the sense amplifier S included in the data output buffer DOB
A CMOS inverter circuit that amplifies the output signal of the AO,
This prevents a relatively large through-current from flowing. That is, during the non-operation period of the sense amplifier SAO, the gate voltages of the P-channel MO3FET and the N-channel MO3FET constituting the CMOS inverter circuit are set to an intermediate level, thereby preventing both from being turned on. Note that a sense amplifier S having the same configuration as above is also used for the common data line CDI.
AI will be provided. The output signal of this sense amplifier SA1 is sent to the output terminal via the corresponding data output buffer DOB.

Although not particularly limited, on the left side of the X-decoder circuit
RY2 is provided.

For this memory array M-ARY2, the same Y
A decoder circuit is provided.

In addition to providing a similar sense amplifier and data output buffer for the memory array M-ARY2,
When the sense amplifiers SAO and SAI are used in common for the left memory array M-ARY2, the common data line of the memory array M-ARY1 is connected to the memory array M-AR.
It is extended to the Y2 side. And memory array M-A
Either one of the Y decoder circuits corresponding to RYI and M-ARY2 forms a data line selection signal.

By dividing the memory array M-ARY in this way, the length of one data line and word line can be shortened, and the number of storage MO3FETs coupled to it can be reduced, thereby increasing the speed of operation. I can do it.

In addition, by arranging a memory array and a sense amplifier below the Y decoder YDCR,
The number of read bits can be increased. By arranging multiple sets of similar memory mats, the number of read bits can be further increased.

FIG. 1 shows X of the mask ROM to which this invention is applied.
Address buffer XADB and X address decoder
A circuit diagram of one embodiment of a DCR is shown. In the figure, an externally supplied address signal XO-Xm is input to an X address buffer XADB via an address signal coupler PXO-PXM, and an internal complementary address signal is formed and sent to a NOR gate GOO-GMI. The test pad PTEST is normally at a low level because it is grounded by an extra-high resistance, and is maintained at a low level during testing except when necessary. Therefore, NOR game) GOO-
The GMI output is normally the internal address signal inverted and
The signal is input to the decoder NOR gate of the address decoder XDCR, and the word line designated by the external address signal is selected.

On the other hand, when a high-level test signal is input to the test pad PTEST by probing, the NOR gate G
The outputs of oo~GMI all become low level, the outputs of all decoder NOR gates connected to the internal address signal bus become high level, and all word lines are selected.

In this state, the power supply voltage VCC is set to a high voltage, for example 9.6
By doing so, all memory cells connected to the data line designated by the external Y address signal enter the aging state via their gates. This type of test is performed using mask ROM.
This can be performed on a semi-finished wafer using a prober or the like, and by applying a screening voltage to all data lines, gate breakdown screening, junction leak screening due to hot carriers, etc. can be performed in a short time.

〔effect〕

(1) By providing a test pad that inputs a test signal for selecting all the word lines of the memory array to the X decoder, which selects and specifies the word line of the memory array using an externally supplied AT/Large signal. , it is possible to realize the aging process of all memory cells in a short time.

(2) Since the above item (1) can be performed in a wafer state, there is no need to lead out the test pads to the outside of the sealing, so the effect can be achieved without increasing the number of external terminals.

(3) In order to deal with increased junction leakage due to hot carriers associated with writing into memory cells by ion implantation, the method described in item (1) above is also applicable to mask ROMs that can clamp the drain voltage Vd of memory cells. As a result, it is possible to achieve the effect of aging all memory cells in a wafer state in a short time.

(4) According to item (3) above, aging of mask ROMs, etc. that can clamp the drain voltage of memory cells in order to cope with increased junction leakage due to real carriers is performed reliably, and stable mask ROMs are provided to users. can. This has the effect of improving the reliability of the product.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, all word lines are selected during testing, and at the same time a specific data line is selected by an external Y address signal. By adding it to the decoder, all data lines may be selected simultaneously. Furthermore, in this embodiment, the data line and the source line are shared by the memory cells in two adjacent columns of memory cells, but the source of the storage MOS FET is directly connected to the ground potential of the circuit. There may be. In this case, M for memory
The drains of the O3FETs are each coupled to one independent data line.

[Application field]

The present invention relates to a semiconductor memory device including a memory element having two different threshold voltages according to stored information, such as a mask type ROM, %EPROM (Electrically Programmable Read Only Memory), etc. It is widely available.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an address decoder of a mask ROM to which the present invention is applied, and FIG. 2 is a circuit diagram showing an embodiment of the main part of the mask ROM. PTEST...Test pad Goo-GM1...Test NOR gate M-ARY1
, M-ARY2...Memory array DCI...□...Dummy array XADB...X address buffer XDCR...
......X address decoder YADB...Y address buffer YDCR...Y address decoder SAO, SAI...Sense ambuoy tI! ! I-O8-III III! ”7, 1st f
! 1

Claims (1)

Claims: 1. A memory device comprising at least one memory array and an address selection circuit capable of selecting all word lines of the memory array. 2. The memory array is configured by arranging memory elements in a matrix to have a relatively high threshold voltage or a relatively low threshold voltage according to stored information, and the address selection circuit 2. The memory device according to claim 1, wherein the memory device receives a predetermined signal from a pad and selects all word lines of the memory array. 3. The above memory element is made to have a relatively high threshold voltage by selectively introducing impurities of the same conductivity type as the substrate gate into its channel region by ion implantation. A storage device according to claim 1 or 2, characterized in that: