CN113406911A - IO circuit and control method thereof - Google Patents

IO circuit and control method thereof Download PDF

Info

Publication number
CN113406911A
CN113406911A CN202110785686.XA CN202110785686A CN113406911A CN 113406911 A CN113406911 A CN 113406911A CN 202110785686 A CN202110785686 A CN 202110785686A CN 113406911 A CN113406911 A CN 113406911A
Authority
CN
China
Prior art keywords
pull
circuit
current
units
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110785686.XA
Other languages
Chinese (zh)
Inventor
周建冲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Anlu Information Technology Co ltd
Original Assignee
Shanghai Anlu Information Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Anlu Information Technology Co ltd filed Critical Shanghai Anlu Information Technology Co ltd
Priority to CN202110785686.XA priority Critical patent/CN113406911A/en
Publication of CN113406911A publication Critical patent/CN113406911A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21119—Circuit for signal adaption, voltage level shift, filter noise

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides an IO circuit, which comprises a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a PMOS tube, a pull-up polysilicon resistor and a first shared bus, the drain electrodes of the PMOS tubes are correspondingly connected with one end of the pull-up polysilicon resistor, the first sharing bus is connected with one end of all the pull-up polysilicon resistors, the pull-down unit comprises an NMOS tube, a pull-down polysilicon resistor and a second sharing bus, the source electrodes of the NMOS tubes are all grounded, the drain electrodes of the NMOS tubes are correspondingly connected with one end of the pull-down polysilicon resistor one by one, and the second sharing bus is connected with one end of all the pull-down polysilicon resistors, the pull-up units share the pull-up polysilicon resistors, the pull-down units share the pull-down polysilicon resistor, so that the current density on the polysilicon resistor is reduced, and the reliability of the IO circuit is improved. The invention also provides a control method of the IO circuit.

Description

IO circuit and control method thereof
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to an IO circuit and a control method thereof.
Background
Input/Output (I/O) in a Field Programmable Gate Array (FPGA) is an important module that is not available, and IO has an Input/Output function, provides a driving capability corresponding to a required impedance when outputting, and needs an on-chip termination impedance to alleviate the signal integrity problem when being used as Input.
At present, the output drive and the on-chip termination impedance of the high-speed IO adopt a multiplexing mode, the output is used as a driver, and the input is used as the on-chip termination impedance. In consideration of the characteristics of high-speed IO and the electrostatic discharge (ESD) requirement, a pull-up unit and a pull-down unit are generally implemented in a manner that an MOS transistor and a polysilicon resistor are connected in series, where a conventional structure is shown in fig. 1, the pull-up unit is formed by connecting N PMOS transistors connected in parallel and a polysilicon resistor in series, and the pull-down unit is formed by connecting M NMOS transistors connected in parallel and a polysilicon resistor in series, where N and M are natural numbers greater than 1. The current carrying capacity of the polysilicon resistor is much weaker than that of the transistor and the interconnection metal wiring, so the polysilicon resistor is often a bottleneck of current density limitation, and the reliability problem of the IO circuit is greatly influenced.
Therefore, it is necessary to provide a novel IO circuit and a control method thereof to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide an IO circuit and a control method thereof, which can reduce the current density on a polysilicon resistor and improve the reliability of the IO circuit.
In order to achieve the above object, the IO circuit of the present invention includes a pull-up unit and a pull-down unit, the pull-up unit includes at least two PMOS transistors, pull-up polysilicon resistors having the same number as the PMOS transistors, and a first shared bus, sources of the PMOS transistors are all connected to a supply voltage, gates of the PMOS transistors are all used for receiving a control signal, drains of the PMOS transistors are connected to one end of the pull-up polysilicon resistors in a one-to-one correspondence, and the first shared bus is connected to one end of all the pull-up polysilicon resistors, the pull-down unit includes at least two NMOS transistors, pull-down polysilicon resistors having the same number as the NMOS transistors, and a second shared bus, sources of the NMOS transistors are all grounded, gates of the NMOS transistors are all used for receiving a control signal, drains of the NMOS transistors are connected to one end of the pull-down polysilicon resistors in a one-to-one correspondence, and the second shared bus is connected to one end of all the pull-down polysilicon resistors, the other end of each pull-down polycrystalline silicon resistor is connected with the other end of each pull-up polycrystalline silicon resistor.
The IO circuit has the advantages that: the first sharing bus is connected with one end of each pull-up polycrystalline silicon resistor, the second sharing bus is connected with one end of each pull-down polycrystalline silicon resistor, the pull-up units share the pull-up polycrystalline silicon resistors, and the pull-down units share the pull-down polycrystalline silicon resistors, so that the current density of the polycrystalline silicon resistors is reduced, and the reliability of an IO circuit is improved.
Preferably, the IO circuit further includes a plate bus 103, and the plate bus 103 is connected to the other end of all the pull-down polysilicon resistors.
The invention also provides an IO circuit control method which is applied to the IO circuit, wherein the control signals comprise a turn-on control signal and a turn-off control signal, the IO circuit control method comprises the steps of applying the turn-off control signal to the grids of all the NMOS tubes to turn off all the NMOS tubes, applying the turn-on control signal to the grids of part of the PMOS tubes to turn on part of the PMOS tubes, and applying the turn-off control signal to the grids of the rest of the PMOS tubes to turn off the rest of the PMOS tubes.
The IO circuit control method has the beneficial effects that: and applying the conduction control signal to the grid electrode of part of the PMOS tubes to conduct part of the PMOS tubes, wherein the pull-up units share the pull-up polysilicon resistor, so that the current density on the pull-up polysilicon resistor is reduced, and the reliability of the IO circuit is improved.
The invention also provides an IO circuit control method which is applied to the IO circuit, wherein the control signals comprise a turn-on control signal and a turn-off control signal, the IO circuit control method comprises the steps of applying the turn-off control signal to the grids of all the PMOS tubes to turn off all the PMOS tubes, applying the turn-on control signal to the grids of part of the NMOS tubes to turn on part of the NMOS tubes, and applying the turn-off control signal to the grids of the rest of the NMOS tubes to turn off the rest of the NMOS tubes.
The IO circuit control method has the beneficial effects that: and applying the conduction control signal to the grid electrode of part of the NMOS tube to conduct part of the NMOS tube, wherein the pull-down units share the pull-down polysilicon resistor, so that the current density on the pull-down polysilicon resistor is reduced, and the reliability of the IO circuit is improved.
The invention also provides an IO circuit control method which is applied to the IO circuit, wherein the control signals comprise a conduction control signal and a turn-off control signal, the IO circuit control method comprises the steps of applying the conduction control signal to part of grid electrodes of the PMOS tubes and part of grid electrodes of the NMOS tubes to conduct part of grid electrodes of the PMOS tubes and part of grid electrodes of the NMOS tubes, and applying the turn-off control signal to the rest of grid electrodes of the PMOS tubes and the rest of grid electrodes of the NMOS tubes to turn off the rest of the PMOS tubes and the rest of the NMOS tubes.
The IO circuit control method has the beneficial effects that: and applying the conduction control signal to partial grid electrodes of the PMOS tubes and partial grid electrodes of the NMOS tubes to conduct the partial grid electrodes of the PMOS tubes and the partial grid electrodes of the NMOS tubes, wherein the pull-up units share the pull-up polycrystalline silicon resistors, and the pull-down units share the pull-down polycrystalline silicon resistors, so that the current density on the polycrystalline silicon resistors is reduced, and the reliability of the IO circuit is improved.
Drawings
FIG. 1 is a circuit diagram of an IO circuit in the prior art;
FIG. 2 is a circuit diagram of an IO circuit in accordance with some embodiments of the present invention;
FIG. 3 is a schematic diagram of the current distribution of the IO circuit as an output driver outputting a high signal according to some embodiments of the present invention;
FIG. 4 is a schematic diagram of the current distribution of the IO circuit as an output driver outputting a low level signal according to some embodiments of the present invention;
FIG. 5 is a schematic diagram of the current distribution of an IO circuit receiving a low signal using pull-up units as on-chip termination resistors according to some embodiments of the present invention;
FIG. 6 is a schematic diagram of the current distribution of an IO circuit using pull-down cells as on-chip termination resistors to receive high level signals according to some embodiments of the present invention;
FIG. 7 is a schematic diagram of the current distribution of an IO circuit receiving a low signal using pull-up units and pull-down units as on-chip termination resistors according to some embodiments of the present invention;
fig. 8 is a schematic diagram of current distribution of an IO circuit receiving a high-level signal using pull-up units and pull-down units as on-chip termination resistors according to some embodiments of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides an IO circuit, which is applied to an FPGA, and according to fig. 2, the IO circuit 100 includes a pull-up unit 101 and a pull-down unit 102, where the pull-up unit 101 includes at least two PMOS transistors 1011, pull-up polysilicon resistors 1012 and a first shared bus 1013, where the number of the pull-up polysilicon resistors is the same as that of the PMOS transistors 1011, the sources of the PMOS transistors 1011 are connected to a supply voltage vddq, the gates of the PMOS transistors 1011 are used for receiving a control signal, the drains of the PMOS transistors 1011 are connected to one end of the pull-up polysilicon resistors 1012 in a one-to-one correspondence, the first shared bus 1013 is connected to one end of all the pull-up polysilicon resistors, the pull-down unit 102 includes at least two NMOS transistors 1012, pull-down polysilicon resistors 1022 and a second shared bus 1023, the sources of the NMOS transistors 1021 are grounded, and the gates of the NMOS transistors 1021 are used for receiving a control signal, the drains of the NMOS transistors 1021 are connected to one end of the pull-down polysilicon resistors 1022 in a one-to-one correspondence manner, the second common bus 1023 is connected to one end of all the pull-down polysilicon resistors 1022, and the other ends of the pull-down polysilicon resistors 1022 are connected to the other ends of all the pull-up polysilicon resistors 1012.
In some embodiments, the IO circuit 100 further includes a plate bus 103, and the plate bus 103 is connected to the other end of all the pull-down polysilicon resistors 1022.
Fig. 3 is a schematic diagram of current distribution of an IO circuit as an output driver for outputting a high-level signal according to some embodiments of the present invention. Fig. 4 is a schematic diagram of current distribution of an IO circuit as an output driver for outputting a low-level signal according to some embodiments of the present invention. Fig. 5 is a schematic diagram of current distribution of an IO circuit receiving a low-level signal using a pull-up unit as an on-chip termination resistor according to some embodiments of the present invention. Fig. 6 is a schematic diagram of current distribution of an IO circuit receiving a high-level signal using a pull-down unit as an on-chip termination resistor according to some embodiments of the present invention. Fig. 7 is a schematic diagram of current distribution of an IO circuit receiving a low-level signal using pull-up units and pull-down units as on-chip termination resistors according to some embodiments of the present invention. Fig. 8 is a schematic diagram of current distribution of an IO circuit receiving a high-level signal using pull-up units and pull-down units as on-chip termination resistors according to some embodiments of the present invention. Referring to fig. 2 to 8, differences between fig. 3 to 8 and fig. 2 include: the pull-up unit 101 includes three PMOS transistors 1011 and three pull-up polysilicon resistors 1012, the three PMOS transistors 1011 are respectively a first PMOS transistor 10111, a second PMOS transistor 10112 and a third PMOS transistor 10113, the three pull-up polysilicon resistors 1012 are respectively a first pull-up polysilicon resistor 10121, a second pull-up polysilicon resistor 10122 and a third pull-up polysilicon resistor 10123, the pull-down unit 102 includes three NMOS tubes 1021 and three pull-down polysilicon resistors 1022, the three NMOS tubes 1021 are respectively a first NMOS tube 10211, a second NMOS tube 10212 and a third NMOS tube 10213, the three pull-down polysilicon resistors 1022 are respectively a first pull-down polysilicon resistor 10221, a second pull-down polysilicon resistor 10222 and a third pull-down polysilicon resistor 10223, the other end of the first pull-up polysilicon resistor 10121, the other end of the second pull-up polysilicon resistor 10122, the other end of the third pull-up polysilicon resistor 10123, The other end of the first pull-down polysilicon resistor 10221, the other end of the second pull-down polysilicon resistor 10222 and the other end of the third pull-down polysilicon resistor 10223 are all connected to a third shared bus 104, and one end of the third shared bus 104 is connected to one end of the board-level bus 103.
Referring to fig. 3 to 8, the first common bus 1013 and the drain of the first PMOS transistor 10111 and one end of the first pull-up polysilicon resistor 10121 are connected to a first welding point 10131, the first common bus 1013 and the drain of the second PMOS transistor 10112 and one end of the second pull-up polysilicon resistor 10122 are connected to a second welding point 10132, and the first common bus 1013 and the drain of the third PMOS transistor 10113 and one end of the third pull-up polysilicon resistor 10123 are connected to a third welding point 10133.
Referring to fig. 3 to 8, the second shared bus 1023 and the drain of the first NMOS transistor 10211 and one end of the first pull-down polysilicon resistor 10221 are connected to a fourth pad 10231, the first shared bus 1013 and the drain of the second NMOS transistor 10212 and one end of the second pull-down polysilicon resistor 10222 are connected to a fifth pad 10232, and the second shared bus 1023 and the drain of the third NMOS transistor 10213 and one end of the third pull-down polysilicon resistor 10223 are connected to a sixth pad 10233.
Referring to fig. 3 to 8, the other end of the first pull-up polysilicon resistor 10121 and the other end of the first pull-down polysilicon resistor 10221 are connected to a seventh pad 1041 of the third common bus 104, the other end of the second pull-up polysilicon resistor 10122 and the other end of the second pull-down polysilicon resistor 10222 are connected to an eighth pad 1042 of the third common bus 104, and the other end of the third pull-up polysilicon resistor 10123 and the other end of the third pull-down polysilicon resistor 10223 are connected to a ninth pad 1043 of the third common bus 104.
The invention provides an IO circuit control method which is applied to an IO circuit, wherein control signals comprise a turn-on control signal and a turn-off control signal, the IO circuit control method comprises the steps of applying the turn-off control signal to the grids of all NMOS tubes to turn off all NMOS tubes, applying the turn-on control signal to the grids of partial PMOS tubes to turn on partial PMOS tubes, and applying the turn-off control signal to the grids of the rest PMOS tubes to turn off the rest PMOS tubes.
Referring to fig. 3, the other end of the board bus 103 and the resistor RtermIs connected, when the IO circuit is applied to a circuit with a memory specification of DDR3, the resistor RtermThe other end of the resistor R is connected with 0.5 times of Power supply voltage vddq, and when the IO circuit is applied to a Low-Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), the resistor R is a resistor RtermAnd the other end of which is connected to ground gnd.
Referring to fig. 3, the IO circuit control method includes applying a turn-on control signal to the gates of the first PMOS transistor 10111 and the second PMOS transistor 10112 to turn on the first PMOS transistor 10111 and the second PMOS transistor 10112, and simultaneously applying a turn-off control signal to the gates of the third PMOS transistor 10113, the first NMOS transistor 10211, the second NMOS transistor 10212, and the third NMOS transistor 10213 to turn off the third PMOS transistor 10113, the first NMOS transistor 10211, the second NMOS transistor 10212, and the third NMOS transistor 10213. The magnitude of the current I1 on the first PMOS transistor 10111 is 3 units, the magnitude of the current I3 flowing from the first pad 10131 to the second pad 10132 is 1 unit through the shunt of the first common bus 1013, the magnitude of the current I5 on the first pull-up polysilicon resistor 10121 is 2 units, the magnitude of the current I8 flowing from the seventh pad 1041 to the eighth pad 1042 is 2 units, the magnitude of the current I2 on the second PMOS transistor 10112 is 3 units, the magnitude of the current I6 on the second pull-up polysilicon resistor 10122 is 2 units through the shunt of the first common bus 1013, the magnitude of the current I4 flowing from the second pad 10132 to the third pad 10133 is 2 units, the remaining 1 unit of current of the second pad 10132 flows to the second pull-up polysilicon resistor 10122, the magnitude of the current I6 on the second pull-up polysilicon resistor 10122 is 2 units, and the magnitude of the current I7 on the third pull-up polysilicon resistor 10123 is 2 units, the magnitude of the current I9 flowing to the ninth pad 1043 from the eighth pad 1042 is 4 units, and the magnitude of the current I10 flowing to the board bus 103 from the ninth pad 1043 is 6 units, that is, the magnitude of the current flowing out from the IO circuit serving as an output driver is 6 units.
Referring to fig. 1 and 3, with the circuit of fig. 1, in order to maintain the same signal amplitude as that of fig. 3, the number of the opened PMOS transistors in fig. 1 is 2-3, and the current flowing through each polysilicon resistor is 2-3 units, which is significantly greater than the current flowing through 2 units of the first pull-up polysilicon resistor 10121, the second pull-up polysilicon resistor 10122 and the third pull-up polysilicon resistor 10123 in fig. 3, so that the present application relieves the stress on the current density of the pull-up polysilicon resistors.
Referring to fig. 5, when the IO circuit is applied to a circuit with a memory specification of DDR4, the pass output impedance is RoutThe driver of (1) sends a low level to the opposite end do.
Referring to fig. 5, the IO circuit control method includes applying a turn-on control signal to the gates of the first PMOS transistor 10111 and the second PMOS transistor 10112 to turn on the first PMOS transistor 10111 and the second PMOS transistor 10112, and simultaneously applying a turn-off control signal to the gates of the third PMOS transistor 10113, the first NMOS transistor 10211, the second NMOS transistor 10212, and the third NMOS transistor 10213 to turn off the third PMOS transistor 10113, the first NMOS transistor 10211, the second NMOS transistor 10212, and the third NMOS transistor 10213. The magnitude of the current I1 on the first PMOS transistor 10111 is 3 units, the magnitude of the current I3 flowing from the first pad 10131 to the second pad 10132 is 1 unit through the shunt of the first common bus 1013, the magnitude of the current I5 on the first pull-up polysilicon resistor 10121 is 2 units, the magnitude of the current I8 flowing from the seventh pad 1041 to the eighth pad 1042 is 2 units, the magnitude of the current I2 on the second PMOS transistor 10112 is 3 units, the magnitude of the current I6 on the second pull-up polysilicon resistor 10122 is 2 units through the shunt of the first common bus 1013, the magnitude of the current I4 flowing from the second pad 10132 to the third pad 10133 is 2 units, the remaining 1 unit of current of the second pad 10132 flows to the second pull-up polysilicon resistor 10122, the magnitude of the current I6 on the second pull-up polysilicon resistor 10122 is 2 units, and the magnitude of the current I7 on the third pull-up polysilicon resistor 10123 is 2 units, the current I9 flowing from the eighth pad 1042 to the ninth pad 1043 is 4 units, and the current I10 flowing from the ninth pad 1043 to the board bus 103 is 6 units, that is, the current flowing from the IO circuit serving as an on-chip termination resistor is 6 units.
Referring to fig. 1 and 5, with the circuit of fig. 1, in order to maintain the same signal amplitude as that of fig. 5, the number of the opened PMOS transistors in fig. 1 is 2-3, and the current flowing through each polysilicon resistor is 2-3 units, which is significantly greater than the current flowing through 2 units of the first pull-up polysilicon resistor 10121, the second pull-up polysilicon resistor 10122 and the third pull-up polysilicon resistor 10123 in fig. 5, so that the present application relieves the stress on the current density of the pull-up polysilicon resistors.
The invention also provides another IO circuit control method which is applied to the IO circuit, wherein the control signals comprise a turn-on control signal and a turn-off control signal, the IO circuit control method comprises the steps of applying the turn-off control signal to the grids of all the PMOS tubes to turn off all the PMOS tubes, applying the turn-on control signal to the grids of part of the NMOS tubes to turn on part of the NMOS tubes, and applying the turn-off control signal to the grids of the rest of the NMOS tubes to turn off the rest of the NMOS tubes.
Referring to FIG. 4, the other end of the board bus 103 and the resistor RtermIs connected, when the IO circuit is applied to a circuit with a memory specification of DDR3, the resistor RtermIs connected with 0.5 times of supply voltage vddq, when the IO circuit is applied to a circuit with the memory specification being DDR4, the resistor RtermTo the other terminal of the supply voltage vddq.
Referring to fig. 4, the IO circuit control method includes applying a turn-on control signal to gates of the first NMOS transistor 10211 and the second NMOS transistor 10212 to turn on the first NMOS transistor 10211 and the second NMOS transistor 10212, and simultaneously applying a turn-off control signal to gates of the first PMOS transistor 10111, the second PMOS transistor 10112, the third PMOS transistor 10113 and the third NMOS transistor 10213 to turn off the first PMOS transistor 10111, the second PMOS transistor 10112, the third PMOS transistor 10113 and the third NMOS transistor 10213. The magnitude of the current I11 flowing through the first NMOS transistor 10211 is 3 units, the magnitude of the current I12 flowing through the second NMOS transistor 10212 is 3 units, the magnitude of the current I15 flowing through the first pull-down polysilicon resistor 10221 is 2 units, the magnitude of the current I13 flowing through the fifth pad 10232 to the fourth pad 10231 is 1 unit, the magnitude of the current I16 flowing through the second pull-down polysilicon resistor 10222 is 2 units, the magnitude of the current I17 flowing through the third pull-down polysilicon resistor 10223 is 2 units, the magnitude of the current I14 flowing through the sixth pad 10233 to the fifth pad 10232 is 2 units, the magnitude of the current I18 flowing through the eighth pad 1042 to the seventh pad 1041 is 2 units, the magnitude of the current I19 flowing through the ninth pad 1043 to the eighth pad 1042 is 4 units, the magnitude of the current I1046 flowing through the board level bus 103 to the ninth pad 1043 is 20 units, i.e. the current drawn by the IO circuit acting as an output driver is 6 units in magnitude.
Referring to fig. 1 and 4, with the circuit of fig. 1, in order to maintain the same signal amplitude as that of fig. 4, the number of the turned-on NMOS transistors in fig. 1 is 2-3, and the current flowing through each polysilicon resistor is 2-3 units, which is significantly greater than the current flowing through 2 units of the first pull-down polysilicon resistor 10221, the second pull-down polysilicon resistor 10222 and the third pull-down polysilicon resistor 10223 in fig. 4, and the present application relieves the stress of the current density of the pull-down polysilicon resistor.
Referring to fig. 6, when the IO circuit is applied to the circuit of LPDDR SDRAM, the pass output impedance is RoutThe driver of (1) sends a high level to the opposite end do.
Referring to fig. 1 and 6, the IO circuit control method includes applying a turn-on control signal to gates of the first NMOS transistor 10211 and the second NMOS transistor 10212 to turn on the first NMOS transistor 10211 and the second NMOS transistor 10212, and simultaneously applying a turn-off control signal to gates of the first PMOS transistor 10111, the second PMOS transistor 10112, the third PMOS transistor 10113, and the third NMOS transistor 10213 to turn off the first PMOS transistor 10111, the second PMOS transistor 10112, the third PMOS transistor 10113, and the third NMOS transistor 10213. The magnitude of the current I11 flowing through the first NMOS transistor 10211 is 3 units, the magnitude of the current I12 flowing through the second NMOS transistor 10212 is 3 units, the magnitude of the current I15 flowing through the first pull-down polysilicon resistor 10221 is 2 units, the magnitude of the current I13 flowing through the fifth pad 10232 to the fourth pad 10231 is 1 unit, the magnitude of the current I16 flowing through the second pull-down polysilicon resistor 10222 is 2 units, the magnitude of the current I17 flowing through the third pull-down polysilicon resistor 10223 is 2 units, the magnitude of the current I14 flowing through the sixth pad 10233 to the fifth pad 10232 is 2 units, the magnitude of the current I18 flowing through the eighth pad 1042 to the seventh pad 1041 is 2 units, the magnitude of the current I19 flowing through the ninth pad 1043 to the eighth pad 1042 is 4 units, the magnitude of the current I1046 flowing through the board level bus 103 to the ninth pad 1043 is 20 units, i.e. the current drawn by the IO circuit acting as an on-die termination resistor is 6 units in magnitude.
Referring to fig. 1 and 6, with the circuit of fig. 1, in order to maintain the same signal amplitude as that of fig. 6, the number of turned-on NMOS transistors in fig. 1 is 2-3, and the current flowing through each polysilicon resistor is 2-3 units, which is significantly larger than the current flowing through 2 units of the first pull-down polysilicon resistor 10221, the second pull-down polysilicon resistor 10222 and the third pull-down polysilicon resistor 10223 in fig. 6, and the present application relieves the stress of the current density of the pull-down polysilicon resistor.
The invention also provides another IO circuit control method which is applied to the IO circuit, wherein the control signals comprise a turn-on control signal and a turn-off control signal, the IO circuit control method comprises the steps of applying the turn-on control signal to the grid electrode of part of the PMOS tube and the grid electrode of part of the NMOS tube to turn on the grid electrode of part of the PMOS tube and the grid electrode of part of the NMOS tube, and applying the turn-off control signal to the grid electrode of the rest of the PMOS tube and the grid electrode of the rest of the NMOS tube to turn off the rest of the PMOS tube and the rest of the NMOS tube.
Referring to fig. 7, when the IO circuit is applied to a circuit with a memory specification of DDR3, the pass output impedance is RoutThe driver of (1) sends a low level to the opposite end do.
Referring to FIG. 8, when the IO circuit is describedWhen the circuit is applied to a circuit with the memory specification of DDR3, the output impedance is RoutThe driver of (1) sends a high level to the opposite end do.
Referring to fig. 7 and 8, the IO circuit control method includes applying a turn-on control signal to gates of the first PMOS transistor 10111, the second PMOS transistor 10112, the first NMOS transistor 10211, and the second NMOS transistor 10212 to turn on the first PMOS transistor 10111, the second PMOS transistor 10112, the first NMOS transistor 10211, and the second NMOS transistor 10212, and simultaneously applying a turn-off control signal to gates of the third PMOS transistor 10113 and the third NMOS transistor 10213 to turn off the third PMOS transistor 10113 and the third NMOS transistor 10213.
Referring to fig. 7, the magnitude of the current I1 on the first PMOS transistor 10111 is 6 units, the magnitude of the current I3 flowing from the first pad 10131 to the second pad 10132 through the shunt of the first common bus 1013 is 2 units, the magnitude of the current I5 on the first pull-up polysilicon resistor 10121 is 4 units, the magnitude of the current I2 on the second PMOS transistor 10112 is 6 units, the magnitude of the current I4 flowing from the second pad 10132 to the third pad 10133 through the shunt of the first common bus 1013 is 4 units, the magnitude of the current I7 on the second pad 10132 to the second pull-up resistor 10122 is 4 units, the magnitude of the current I6 on the second pull-up polysilicon resistor 10122 to the third pad 10123 is 4 units, the magnitude of the current I11 on the first PMOS transistor 10211 is 3 units, the magnitude of the current I12 on the second NMOS transistor 10212 is 3 units, the magnitude of the current I15 on the first pull-down polysilicon resistor 10221 is 2 units, the magnitude of the current I13 flowing from fifth solder joint 10232 to fourth solder joint 10231 is 1 unit, the magnitude of the current I16 across the second pull-down polysilicon resistor 10222 is 2 units, the magnitude of the current I17 across the third pull-down polysilicon resistor 10223 is 2 units, the magnitude of the current I14 flowing from sixth solder 10233 to fifth solder 10232 is 2 units, the magnitude of the current I8 flowing from the seventh welding point 1041 to the eighth welding point 1042 is 2 units, the magnitude of the current I9 flowing from the eighth pad 1042 to the ninth pad 1043 is 4 units, the magnitude of the current I10 flowing to the board-level bus 103 through the ninth pad 1043 is 6 units, that is, the magnitude of the current flowing out from the IO circuit serving as an on-chip termination resistor is 6 units.
Referring to fig. 1 and 7, in order to maintain the same signal amplitude as that of fig. 7, the number of the opened NMOS transistors and PMOS transistors in fig. 1 is 2-3, the current flowing through the polysilicon resistor in the pull-up unit is 4-6 units, which is significantly larger than the current flowing through 4 units of the first pull-up polysilicon resistor 10121, the second pull-up polysilicon resistor 10122 and the third pull-up polysilicon resistor 10123 in fig. 7, the current flowing through the polysilicon resistor in the pull-down unit is 2-3 units, which is significantly larger than the current flowing through 2 units of the first pull-down polysilicon resistor 10221, the second pull-down polysilicon resistor 10222 and the third pull-down polysilicon resistor 10223 in fig. 7, and the present application relieves the stress of the current densities of the pull-up polysilicon resistor and the pull-down polysilicon resistor.
Referring to fig. 8, the magnitude of the current I1 on the first PMOS transistor 10111 is 3 units, the magnitude of the current I3 flowing from the first pad 10131 to the second pad 10132 through the shunt of the first common bus 1013 is 1 unit, the magnitude of the current I5 on the first pull-up polysilicon resistor 10121 is 2 units, the magnitude of the current I2 on the second PMOS transistor 10112 is 3 units, the magnitude of the current I4 flowing from the second pad 10132 to the third pad 10133 through the shunt of the first common bus 1013 is 2 units, the magnitude of the current I7 on the second pad 10132 to the second pull-up resistor 10122 is 2 units, the magnitude of the current I6 on the second pull-up polysilicon resistor 10122 is 2 units, the magnitude of the current I7 on the third pull-up polysilicon resistor 10123 is 2 units, and the magnitude of the current I11 on the first NMOS transistor 10211 is 6 units, the magnitude of the current I12 on the second NMOS transistor 10212 is 6 units, the magnitude of the current I15 on the first pull-down polysilicon resistor 10221 is 4 units, the magnitude of the current I13 flowing from fifth solder joint 10232 to fourth solder joint 10231 is 2 units, the magnitude of the current I16 across the second pull-down polysilicon resistor 10222 is 4 units, the magnitude of the current I17 across the third pull-down polysilicon resistor 10223 is 4 units, the magnitude of the current I14 flowing from sixth solder point 10233 to fifth solder point 10232 is 4 units, the magnitude of the current I8 flowing from the eighth pad 1042 to the seventh pad 1041 is 2 units, the magnitude of the current I9 flowing from the ninth welding point 1043 to the eighth welding point 1042 is 4 units, the magnitude of the current I10 flowing to the ninth pad 1043 through the board-level bus 103 is 6 units, that is, the magnitude of the current flowing into the IO circuit serving as an on-chip termination resistor is 6 units.
Referring to fig. 1 and 8, in order to maintain the same signal amplitude as that of fig. 8, the number of the turned-on NMOS transistors and PMOS transistors in fig. 1 is 2-3, the current flowing through the poly resistor in the pull-up unit is 2-3 units, which is significantly larger than the current flowing through 2 units of the first pull-up poly resistor 10121, the second pull-up poly resistor 10122 and the third pull-up poly resistor 10123 in fig. 7, the current flowing through the poly resistor in the pull-down unit is 4-6 units, which is significantly larger than the current flowing through 4 units of the first pull-down poly resistor 10221, the second pull-down poly resistor 10222 and the third pull-down poly resistor 10223 in fig. 8, and the present application relieves the stress of the current densities of the pull-up poly resistor and the pull-down poly resistor.
In some embodiments of the present invention, the on control signal is a high level signal, and the off control signal is a low level signal.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (5)

1. An IO circuit is characterized by comprising a pull-up unit and a pull-down unit, wherein the pull-up unit comprises at least two PMOS tubes, pull-up polysilicon resistors with the same number as the PMOS tubes and a first shared bus, the source electrodes of the PMOS tubes are connected with a power supply voltage, the grid electrodes of the PMOS tubes are used for receiving control signals, the drain electrodes of the PMOS tubes are correspondingly connected with one ends of the pull-up polysilicon resistors, the first shared bus is connected with one ends of all the pull-up polysilicon resistors, the pull-down unit comprises at least two NMOS tubes, pull-down polysilicon resistors with the same number as the NMOS tubes and a second shared bus, the source electrodes of the NMOS tubes are grounded, the grid electrodes of the NMOS tubes are used for receiving control signals, the drain electrodes of the NMOS tubes are correspondingly connected with one ends of the pull-down polysilicon resistors, and the second shared bus is connected with one end of all the pull-down polysilicon resistors, the other end of each pull-down polycrystalline silicon resistor is connected with the other end of each pull-up polycrystalline silicon resistor.
2. The IO circuit according to claim 1, further comprising a plate bus line 103, wherein the plate bus line 103 is connected to the other end of all the pull-down polysilicon resistors.
3. An IO circuit control method applied to the IO circuit as claimed in any one of claims 1 to 2, wherein the control signals include an on control signal and an off control signal, the IO circuit control method includes applying the off control signal to gates of all the NMOS transistors to turn off all the NMOS transistors, applying the on control signal to gates of a part of the PMOS transistors to turn on a part of the PMOS transistors, and applying the off control signal to gates of the remaining part of the PMOS transistors to turn off the remaining part of the PMOS transistors.
4. An IO circuit control method applied to the IO circuit as claimed in any one of claims 1 to 2, wherein the control signals include an on control signal and an off control signal, the IO circuit control method includes applying an off control signal to gates of all the PMOS transistors to turn off all the PMOS transistors, applying the on control signal to gates of a part of the NMOS transistors to turn on a part of the NMOS transistors, and applying the off control signal to gates of the remaining part of the NMOS transistors to turn off the remaining part of the NMOS transistors.
5. An IO circuit control method applied to the IO circuit as claimed in any one of claims 1 to 2, wherein the control signals include an on control signal and an off control signal, the IO circuit control method includes applying the on control signal to a part of the gates of the PMOS transistors and a part of the gates of the NMOS transistors to turn on a part of the gates of the PMOS transistors and a part of the gates of the NMOS transistors, and applying the off control signal to a remaining part of the gates of the PMOS transistors and a remaining part of the gates of the NMOS transistors to turn off a remaining part of the gates of the PMOS transistors and a remaining part of the gates of the NMOS transistors.
CN202110785686.XA 2021-07-12 2021-07-12 IO circuit and control method thereof Pending CN113406911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110785686.XA CN113406911A (en) 2021-07-12 2021-07-12 IO circuit and control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110785686.XA CN113406911A (en) 2021-07-12 2021-07-12 IO circuit and control method thereof

Publications (1)

Publication Number Publication Date
CN113406911A true CN113406911A (en) 2021-09-17

Family

ID=77686066

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110785686.XA Pending CN113406911A (en) 2021-07-12 2021-07-12 IO circuit and control method thereof

Country Status (1)

Country Link
CN (1) CN113406911A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113961490A (en) * 2021-11-04 2022-01-21 上海安路信息科技股份有限公司 System and method for monitoring DDR signal based on FPGA, FPGA and medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5099148A (en) * 1990-10-22 1992-03-24 Sgs-Thomson Microelectronics, Inc. Integrated circuit having multiple data outputs sharing a resistor network
US6005413A (en) * 1997-09-09 1999-12-21 Lsi Logic Corporation 5V tolerant PCI I/O buffer on 2.5V technology
US20050057281A1 (en) * 2003-08-25 2005-03-17 Seong-Jong Yoo Data output driver
JP2009188790A (en) * 2008-02-07 2009-08-20 Spansion Llc Output buffer circuit
CN104834341A (en) * 2015-05-13 2015-08-12 灿芯半导体(上海)有限公司 Output impedance regulation circuit in interface circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5099148A (en) * 1990-10-22 1992-03-24 Sgs-Thomson Microelectronics, Inc. Integrated circuit having multiple data outputs sharing a resistor network
US6005413A (en) * 1997-09-09 1999-12-21 Lsi Logic Corporation 5V tolerant PCI I/O buffer on 2.5V technology
US20050057281A1 (en) * 2003-08-25 2005-03-17 Seong-Jong Yoo Data output driver
JP2009188790A (en) * 2008-02-07 2009-08-20 Spansion Llc Output buffer circuit
CN104834341A (en) * 2015-05-13 2015-08-12 灿芯半导体(上海)有限公司 Output impedance regulation circuit in interface circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113961490A (en) * 2021-11-04 2022-01-21 上海安路信息科技股份有限公司 System and method for monitoring DDR signal based on FPGA, FPGA and medium
CN113961490B (en) * 2021-11-04 2023-09-26 上海安路信息科技股份有限公司 System, method, FPGA and medium for monitoring DDR signal based on FPGA

Similar Documents

Publication Publication Date Title
KR930006843B1 (en) Ic memory circuit apparatus
US9875786B2 (en) Output buffer circuit with low sub-threshold leakage current
KR910009077B1 (en) Voltage level conversion circuit
GB2184622A (en) Output buffer having limited rate-of-change of output current
US4354256A (en) Semiconductor memory device
US5382847A (en) Output buffer circuits including voltage compensation
US10885955B2 (en) Driver circuit equipped with power gating circuit
US6229365B1 (en) Semiconductor integrated circuit device operating stably at a plurality of power supply voltage levels
KR100211758B1 (en) Multi-power data buffer
JPS6381551A (en) Memory device
US10573373B1 (en) Serializer
CN113406911A (en) IO circuit and control method thereof
KR100259070B1 (en) Data output buffer circuit
US4651029A (en) Decoder circuit
US11380406B2 (en) Output circuit
US10878853B2 (en) Power supply control
EP0202582B1 (en) A nmos data storage cell and shift register
KR910006478B1 (en) Semiconductor integrated circuit
JPH06132747A (en) Semiconductor device
US9548726B1 (en) Slew-rate control and waveshape adjusted drivers for improving signal integrity on multi-loads transmission line interconnects
JPH11500896A (en) High voltage level shift CMOS buffer
US20230170013A1 (en) Apparatuses including output drivers and methods for providing output data signals
KR960001864B1 (en) Semiconductor memory device with segment word line
JPH07161185A (en) Data-transmission circuit, data line-driving circuit, amplifying circuit, semiconductor integrated circuit and semiconductor memory device
JP3167309B2 (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210917

RJ01 Rejection of invention patent application after publication