JPH07161185A - Data-transmission circuit, data line-driving circuit, amplifying circuit, semiconductor integrated circuit and semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a consuming power in a semiconductor integrated circuit provided with a data transmission circuit and to transfer data at high velocity. CONSTITUTION:A driver circuit 6a for driving a pair of data lines 20 reduces an amplitude of arm input differential signal, that is, 2.5V to 0.6V which is smaller than a conventional lower limit of a source voltage (approximately 1.5V). The amplitude of the differential signal transmitted through the pair of data lines 20 is amplified at an amplifier circuit 30 to 2.5V and latched at a latch circuit 40. After the latching at the latch circuit 40, the operation of the amplifier circuit 30 is stopped. Tone driver circuit 6a is constituted of only NMOS transistors Qn11-Qn16 so as not to increase leakage current. A threshold voltage of the Qn12 and Qn14 at the earth side is set to be a value considered to be a lower limit heretofore (0.3V-0.6V), and that of the Qn11 and Qn13 at the side of a power source is set, to be a lower value than the lower limit, (0V-0.3V). Accordingly, a driving efficiency of the Qn11 and Qn13 is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit, a data line drive circuit and an amplification circuit used in the data transmission circuit, and a semiconductor integrated circuit and a semiconductor memory device having the data transmission circuit.

[0002]

2. Description of the Related Art In recent years, dynamic RAM (DRAM), which is one of semiconductor integrated circuits (LSI), has been increasing in capacity at a rate of quadruple in three years. With this increase in capacity, the chip area of DRAM has increased by 1.5 times in each generation (for example, from 1 Mbit to 4 Mbit). With the increase of the chip area, the wiring of the signal line for data transmission in the DRAM becomes longer, which leads to the increase of the wiring capacity. Furthermore, the increase in the number of wirings due to the increase in the number of bits also contributes to the increase in wiring capacity.

Most of the power consumption in the DRAM is consumed by charging and discharging the signal line. The increase in the wiring capacity causes an increase in charge / discharge current, and thus an increase in power consumption of the entire DRAM. Further, an increase in wiring capacitance causes an increase in signal delay.

On the other hand, with the miniaturization of MOS transistor elements in DRAM, the breakdown voltage of the oxide film has become a problem.

Therefore, in the conventional DRAM, efforts have been made to lower the internal power supply voltage in order to improve the reliability of the oxide film in addition to reducing the power consumption and the signal delay. The step-down voltage VINT generated inside the DRAM chip based on the external power supply voltage VCC is supplied to the MOS transistor circuit on the chip.

To reduce the voltage amplitude of the signal line, L
It is extremely effective in reducing the power consumption of the entire SI. Japanese Unexamined Patent Publication No. 4-21515 discloses a data transmission circuit that operates with a small amplitude based on the reduced internal power supply voltage (step-down voltage). This is because a driver circuit having a CMOS structure drives a single data line for data transmission with a small amplitude, and a receiver circuit as shown in FIG. 18 receives a signal with a small amplitude from the data line to generate a signal with a large amplitude. It is to convert.

[0007]

However, in the conventional data transmission circuit described above, when the wiring for data transmission becomes long, the input IN of the receiver circuit shown in FIG. 18 changes only slowly and the operation speed becomes slow. There is a problem that The cause of this is the input I of the receiver circuit.
If N does not become VCL-Vtn (or VSL-Vtp), it does not work, and since it is in the form of a source follower, Vt
This is because n and Vtp are increased due to the substrate bias effect. In addition, VCL and VSL that require attention 2
Two power supplies are required, and this two power supplies cause an increase in current consumption.

Therefore, as a measure for improving the operating speed, the NMOS and the PMOS of the input section of the receiver circuit are respectively set to Vt.
A means of reducing n and Vtp can be considered. However, in order to lower the threshold voltage of the MOS transistor, the number of processes is increased in the manufacturing stage,
An increase in mask occurs. Further, a CMOS inverter may be provided in the preceding stage of the receiver circuit in order to reduce the transition time of the signal input to the receiver circuit, but an off-leak current occurs between VCL and VSL.

The present invention has been made in view of the above, and an object thereof is to realize high-speed data transmission with low power consumption even when wiring is long.

[0010]

In order to achieve the above-mentioned object, concretely, the solution means taken by the invention of claim 1 is intended for a data transmission circuit for a semiconductor integrated circuit, as shown in FIG. A first circuit (driver circuit) 6a for converting a first differential signal having a first amplitude into a second differential signal having a second amplitude smaller than the first amplitude; Signal line pair (data line pair) 20 for transmitting the second differential signal converted by the first circuit 6a, and the second differential signal transmitted through the signal line pair 20 to the third amplitude. A second circuit (amplifier circuit) 30 for converting into a third differential signal having a third differential signal and a third circuit converted by the second circuit 30.
Circuit (latch circuit) 40 for latching the differential signal of
And a configuration provided with.

The invention of claim 2 is, specifically, claim 1
According to the configuration of the invention described above, the second circuit includes a pair of differential input terminals for inputting the differential signal, and an amplification section for amplifying the differential signal input through the pair of differential input terminals. And a pair of differential output terminals for outputting the differential signal amplified by the amplification section, and a power supply control for controlling power supply to the amplification section based on outputs from the pair of differential output terminals. And a structure having a section.

The invention of claim 3 is, specifically, claim 1
A configuration in which the third amplitude of the third differential signal is equal to the first amplitude of the first differential signal is added to the configuration of the described invention.

The invention of claim 4 is, specifically, claim 1
In the configuration of the invention described above, the first to third differential signals are logic signals each having a high level and a low level,
A configuration in which the low level of each logic signal is equal to the ground level is added.

The invention of claim 5 is, specifically, claim 1
In the configuration of the invention described above, the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is equal to a power supply voltage given from the outside of the semiconductor integrated circuit. The configuration is added.

The invention of claim 6 is, specifically, claim 1
In the configuration of the invention described above, the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is based on a power supply voltage applied from the outside of the semiconductor integrated circuit. A configuration is added that is equal to the first step-down voltage generated inside the semiconductor integrated circuit.

The invention of claim 7 is, specifically, claim 1
In the configuration of the invention described above, the second differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is based on a power supply voltage applied from the outside of the semiconductor integrated circuit. A configuration is added that is equal to the second step-down voltage generated inside the semiconductor integrated circuit.

The invention of claim 8 is specifically, claim 1.
In addition to the configuration of the invention described above, the configuration is such that the ground line of the first circuit is provided independently of the ground lines of the other circuits in the semiconductor integrated circuit.

The invention of claim 9 is specifically, claim 1.
In addition to the configuration of the invention described above, the operation of the second circuit is stopped in synchronization with the latching of the third differential signal by the third circuit.

In a tenth aspect of the invention, specifically, in the configuration of the first aspect of the invention, as shown in FIG. 11, a fourth aspect for equalizing the potential of the signal line pair (data line pair) 20 is provided. The circuit (equalizing circuit) 60 is further provided.

Specifically, the invention of claim 11 is the configuration of the invention of claim 10, in which the first differential signal to the third differential signal are changed in the first half of one data transmission cycle. As described above, the first and second circuits are operated, and in the latter half of the data transmission cycle, the second circuit is synchronized with the latching of the third differential signal by the third circuit. A configuration is added in which the operation is stopped and the fourth circuit is operated so as to equalize the potential of the signal line pair.

In order to achieve the above-mentioned object, the solution means specifically taken by the invention of claim 12 is as shown in FIG.
A pair of differential input terminals for a data line driving circuit (driver circuit) 6a that differentially drives a data line pair 20 in a semiconductor integrated circuit, to which a first differential signal having a first amplitude is input. 11 and 12, a pair of differential output terminals 14 and 15 connected to the data line pair 20 so as to output a second differential signal having a second amplitude, and the pair of differential input terminals 11. , 12 having a gate connected to one terminal 11 thereof, a drain connected to one terminal 14 of the pair of differential output terminals 14 and 15 and a source connected to a power supply line. A first NMOS transistor Qn11, a gate connected to the other terminal 12 of the pair of differential input terminals 11 and 12, a drain connected to the drain of the first NMOS transistor Qn11, and a ground line To A second NMOS transistor Qn12 having a source connected to it, a gate connected to the gate of the second NMOS transistor Qn12, and the other terminal 15 of the pair of differential output terminals 14 and 15 A third NMOS transistor Qn13 having a drain connected to the power supply line, a gate connected to the gate of the first NMOS transistor Qn11, and a drain of the third NMOS transistor Qn13. A fourth NMOS transistor Qn having a drain connected to it and a source connected to the ground line.
14 is provided.

According to a thirteenth aspect of the present invention, in the configuration according to the twelfth aspect, the second amplitude of the second differential signal is smaller than the first amplitude of the first differential signal. Is added.

According to a fourteenth aspect of the present invention, in the structure according to the twelfth aspect, the first and second differential signals are logic signals having a high level and a low level, respectively, and the low level of each logic signal. Adds a configuration that is equal to the ground level.

According to a fifteenth aspect of the present invention, in the structure according to the twelfth aspect, the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is the semiconductor. A configuration is added in which the power supply voltage is given from the outside of the integrated circuit.

According to a sixteenth aspect of the present invention, in the structure according to the twelfth aspect, the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is the semiconductor. A first generated inside the semiconductor integrated circuit based on a power supply voltage given from the outside of the integrated circuit;
A configuration in which the voltage is equal to the step-down voltage is added.

According to a seventeenth aspect of the present invention, in the structure according to the twelfth aspect, the second differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is the semiconductor. A second voltage generated inside the semiconductor integrated circuit based on a power supply voltage applied from the outside of the integrated circuit;
A configuration in which the voltage is equal to the step-down voltage is added.

According to an eighteenth aspect of the present invention, the threshold voltage of the first and third NMOS transistors Qn11 and Qn13 shown in FIG.
And a configuration in which it is lower than the threshold voltage of the fourth NMOS transistors Qn12 and Qn14.

In order to achieve the above-mentioned object, the solution means specifically taken by the invention of claim 19 is intended for an amplifier circuit for amplifying a differential signal in a semiconductor integrated circuit.
, A pair of differential input terminals 31, 32 for inputting the differential signal, and a pair of differential input terminals 31,
An amplification unit 36 that amplifies the differential signal input through 32.
And a pair of differential output terminals 34 and 35 for outputting the differential signal amplified by the amplifying section 36, and to the amplifying section 36 based on outputs from the pair of differential output terminals 34 and 35. And a power supply controller 37 for controlling the power supply of the power supply.

According to a twentieth aspect of the invention, in addition to the configuration of the nineteenth aspect of the invention, as shown in FIG.
Are first and second PMOS transistors Q connected in series with each other and interposed between the power supply line and the amplification unit 36.
p37, Qp38, and the first PMOS transistor Q
The gate of p37 is connected to one terminal 35 of the pair of differential output terminals 34 and 35, and the gate of the second PMOS transistor Qp38 is connected to the pair of differential output terminals 3
The structure connected to the other terminal 34 of 4, 35 is added.

In order to achieve the above-mentioned object, the solution means specifically taken by the invention of claim 21 is intended for a semiconductor integrated circuit, and as shown in FIG. 9, each has a power supply line and a ground line. Main power supply wiring system 56, sub power supply wiring system 57, and first circuit block 5 directly connected to the main power supply wiring system 56.
1, the second circuit block 52 directly connected to the sub power supply wiring system 57, and the main power supply wiring system so as to suppress noise propagation from the first circuit block 51 to the second circuit block 52. The power supply system coupling circuit 70 is interposed between the sub power supply wiring system 57 and the sub power supply wiring system 57.

According to a twenty-second aspect of the invention, in the configuration of the twenty-first aspect, the second circuit block has a first difference having a first amplitude so as to drive the data line pairs differentially. A second signal having a second amplitude smaller than the first amplitude
A data line drive circuit for converting into a differential signal, the first and second differential signals are logic signals having a high level and a low level, respectively, and the low level of each logic signal is the sub-power supply wiring system. The configuration is added that is equal to the voltage level of the ground line.

According to a twenty-third aspect of the present invention, in addition to the configuration of the twenty-first aspect, as shown in FIG.
Reference numeral 0 denotes first and second NMOS transistors Qn71 and Qn72 which are connected in parallel to each other and are interposed between the ground line 56 of the main power supply wiring system and the ground line 57 of the sub power supply wiring system.
The gate of the first NMOS transistor Qn71 is supplied with the control clock, and the gate of the second NMOS transistor Qn72 is provided with the ground line 5 of the sub power supply wiring system.
The configuration connected to 7 is added.

According to a twenty-fourth aspect of the invention, in addition to the configuration of the twenty-third aspect of the invention, a configuration is adopted in which the threshold voltage of the second NMOS transistor is 0 V or less.

According to a twenty-fifth aspect of the present invention, in addition to the configuration of the twenty-first aspect, as shown in FIG. 9, a power supply voltage supplied from the outside so as to supply a step-down voltage to the second circuit block 52. A power supply voltage down circuit 80 for generating the stepped down voltage based on the above is further provided, and as shown in FIG. 10, the power supply voltage down circuit 80 has a reference potential generation circuit 84 for generating a potential serving as a reference of the down voltage. The ground line of the reference potential generating circuit 84 is added to the structure directly connected to the ground line of the sub power supply wiring system.

According to a twenty-sixth aspect of the present invention, in addition to the configuration of the twenty-fifth aspect of the invention, as shown in FIG.
Reference numeral 0 further includes a comparison circuit 85 for comparing the reference potential generated by the reference potential generation circuit 84 with the step-down voltage, each of the comparison circuits 85 constituting a parallel current mirror type current source. A pair of PMs connected to the power line
OS transistors Qp81, Qp82 and a pair of NMOS transistors Qn82 connected to the ground side of the pair of PMOS transistors Qp81, Qp82, respectively, so as to form a differential amplifier with the reference potential and the step-down voltage as inputs.
Qn83 and the pair of NMOS transistors Qn82, Qn
A switch element (NMOS transistor) Qn84 interposed between each source of 83 and the ground line, and the threshold voltage of each of the pair of NMOS transistors Qn82 and Qn83 is set to be low so as to enhance the driving capability. The existing configuration is added.

In order to achieve the above object, the solution means specifically taken by the invention of claim 27 is intended for a semiconductor memory device, and is provided on the same semiconductor chip 1 as shown in FIG. 1 or 2. A data processing unit 3 and at least one memory unit 2; and a pad 4 provided on the semiconductor chip 1 for at least one of inputting a signal from the outside and outputting a signal to the outside. The pad 4 is arranged between the portion of the semiconductor chip 1 where the memory unit 2 is arranged and the portion where the data processing unit 3 is arranged.

The invention of claim 28 is, specifically, in the structure of claim 27, further comprising a data transmission circuit for transmitting data between the memory section and the data processing section. The data transmission circuit converts a first differential signal having a first amplitude into a second differential signal having a second amplitude smaller than the first amplitude, and the first circuit.
And a signal line pair for transmitting the second differential signal converted by the circuit, and the second differential signal transmitted through the signal line pair into a third differential signal having a third amplitude. A second circuit for converting and a third circuit converted by the second circuit.
And a third circuit for latching the differential signal of 3) is added.

A thirty-ninth aspect of the present invention is, specifically, in the configuration of the twenty-seventh aspect of the present invention, further comprising a data transmission circuit which has a plurality of the memory sections and which transmits data between the memory sections. The data transmission circuit includes a first circuit for converting a first differential signal having a first amplitude into a second differential signal having a second amplitude smaller than the first amplitude; A signal line pair for transmitting the second differential signal converted by the first circuit, and a third differential signal having a third amplitude for the second differential signal transmitted through the signal line pair. A configuration having a second circuit for converting into a signal and a third circuit for latching the third differential signal converted by the second circuit is added.

The thirtieth aspect of the invention is, specifically, in the configuration of the twenty-seventh aspect of the invention, as shown in FIG. 1, there are a plurality of the memory sections 2 and the data processing section 3 is the semiconductor. The plurality of memory parts 2 are arranged in the central part of the chip 1, the plural memory parts 2 are arranged in the peripheral part of the semiconductor chip 1, and the pads 4 are intermediate parts which are parts between the central part and the peripheral part of the semiconductor chip 1. The configuration arranged in the section is added.

The thirty-first aspect of the invention is, specifically, the configuration of the thirtieth aspect of the invention, further comprising a data transmission circuit for transmitting data between the memory section and the data processing section. The data transmission circuit converts a first differential signal having a first amplitude into a second differential signal having a second amplitude smaller than the first amplitude, and the first circuit.
And a signal line pair for transmitting the second differential signal converted by the circuit, and the second differential signal transmitted through the signal line pair into a third differential signal having a third amplitude. A second circuit for converting and a third circuit converted by the second circuit.
And a third circuit for latching the differential signal of 3) is added.

A thirty-second aspect of the present invention is, specifically, the configuration of the thirtieth aspect of the invention, further including a data transmission circuit for transmitting data between the memory sections, wherein the data transmission circuit is the first A first circuit for converting a first differential signal having an amplitude of 1 into a second differential signal having a second amplitude smaller than the first amplitude; and a first circuit converted by the first circuit. A signal line pair for transmitting the second differential signal, and a second circuit for converting the second differential signal transmitted through the signal line pair into a third differential signal having a third amplitude. , A third circuit for latching the third differential signal converted by the second circuit is added.

In order to achieve the above-mentioned object, a solution means specifically taken by the invention of claim 33 is a semiconductor memory device, and as shown in FIGS. 3A and 3B, the same semiconductor is used. A power supply voltage terminal (power supply voltage pad) that includes a memory array 122 and a data processing unit 3 provided on the chip 1 and that supplies a power supply voltage to the memory array 122 and the data processing unit 3 provided on the semiconductor chip 1. 125
And the memory array 1 provided on the semiconductor chip 1.
22 and a ground voltage terminal (ground voltage pad) 126 for supplying a ground voltage to the data processing unit 3, a power supply voltage from the power supply voltage terminal 125 provided on the semiconductor chip 1, and a ground from the ground voltage terminal 126. A memory array supply voltage generation circuit (reference voltage generation circuit) 127 which receives a voltage and generates a memory array supply voltage supplied to the memory array 122, and a memory array supply voltage from the power supply voltage terminal 125 provided in the semiconductor chip 1. Through current interrupting means (switch element) 12 for interrupting the through current flowing through the generation circuit 127 to the ground voltage terminal 126.
9 is further provided.

In order to achieve the above-mentioned object, a solution means specifically taken by the invention of claim 34 is a semiconductor memory device, and as shown in FIGS. 5A and 5B, the same semiconductor is used. A first power supply voltage terminal (first power supply voltage pad) that includes a memory array 122 provided on the chip 1 and a data processing unit 3 and is provided on the semiconductor chip 1 and supplies a power supply voltage to the memory array 122. ) 125a, a second power supply voltage terminal (second power supply voltage pad) 125b provided on the semiconductor chip 1 for supplying a power supply voltage to the data processing section 3, and the second power supply voltage terminal 125b provided on the semiconductor chip 1 A memory array supply voltage generation circuit (reference voltage generation circuit) that receives a power supply voltage from the power supply voltage terminal 125a of No. 1 and generates a memory array supply voltage supplied to the memory array 122. It is an further comprising Configurations and 27.

[0044]

According to the invention of claims 1 to 11, in the data transmission circuit for a semiconductor integrated circuit, the second differential signal having a voltage amplitude smaller than that of the first differential signal (input differential signal) is used. Data transmission through the signal line pair (data line pair) 20 can be realized. As a result, the signal line pair 20
Even if the wiring length is long, the influence of the parasitic resistance and the parasitic capacitance of the signal line pair 20 can be suppressed, and the charging / discharging current and the signal delay can be reduced, so that a high speed and low power consumption semiconductor integrated circuit can be realized. Furthermore, since the peak current can be reduced by reducing the charging / discharging current, the reliability and noise resistance of the signal wiring are improved. Further, since the third circuit (latch circuit) 40 is provided at the subsequent stage of the second circuit (amplifier circuit) 30, the output load of the second circuit 30 becomes small, and the size of the second circuit 30 becomes small. Therefore, the through current can be suppressed to be small.

According to the structure of the invention of claim 8, the first
By providing the ground wire of the circuit (driver circuit) independently of the ground wires of other circuits, stable operation of the first circuit is secured without being affected by fluctuations in the ground level due to the operation of other circuits. can do.

According to the configuration of the invention of claim 9, the second
By latching the output (third differential signal) of the circuit (amplification circuit) of (3), the operation of the second circuit is stopped,
The power consumption of the semiconductor integrated circuit can be further reduced.

By further providing the fourth circuit (equalize circuit) 60 according to the structure of the tenth and eleventh aspects of the invention, the time until the potential difference between the signal line pair (data line pair) 20 reaches a predetermined value. As a result, the data transmission is further speeded up.

According to the twelfth to eighteenth aspects of the present invention, by adopting the NMOS configuration in the data line driving circuit, a large gate-source voltage can be secured in each of the NMOS transistors Qn11 to Qn14, and the threshold voltage thereof can be secured. Even if the lower limit of is limited to 0.3 V to 0.6 V, a large ability to drive the signal line pair (data line pair) 20 can be obtained, so that high speed is achieved with a voltage amplitude smaller than 1.5 V without an increase in off-leakage current. Data transmission can be realized. On top of that,
Since only two power supplies are required in the conventional CMOS configuration, the power consumption of the semiconductor integrated circuit can be further reduced. Further, since it can be constituted by only NMOS transistors, it is easy to manufacture.

According to the eighteenth aspect of the present invention, the first and third NMOS transistors Q located on the power supply side are provided.
Even if the threshold voltage of n11 and Qn13 is set lower than the value (about 0.3V to 0.6V) which is the lower limit of the prior art, the Q
Since the off-leakage currents of n11 and Qn13 are blocked by the second and fourth NMOS transistors Qn12 and Qn14 located on the ground side, the threshold voltage of Qn11 and Qn13 is set lower than the threshold voltage of Qn12 and Qn14. Therefore, Qn11 and Qn can be increased without increasing the off-leakage current.
The drive capability of 13 can be further enhanced.

In the amplifier circuit according to the nineteenth and twentieth aspects of the invention, in the amplifier circuit, the power is supplied to the amplifier section 36 based on the output differential signal amplified by the amplifier section 36 instead of the input differential signal having a small voltage amplitude. Is controlled. As a result, the operation of the amplification section 36 can be surely stopped,
The power consumption of the semiconductor integrated circuit can be further reduced.

Further, according to the twentieth aspect of the invention, since the output is a differential signal, at least one of the first and second PMOS transistors Qp37 and Qp38 forming the power supply controller 37 is surely turned off. To do.

According to the invention of claims 21 to 26, in the semiconductor integrated circuit, the power supply system coupling circuit 70 interposed between the main power supply wiring system 56 and the sub power supply wiring system 57 is arranged from the first circuit block 51 to the first circuit block 51. The noise propagation to the second circuit block 52 is suppressed.

According to the twenty-third aspect of the invention, the first NMOS transistor Qn71 of the two NMOS transistors Qn71, Qn72 forming the power supply system coupling circuit 70 is turned on in response to the control clock. The ground line 56 of the main power supply wiring system and the ground line 57 of the sub power supply wiring system are connected with low impedance. Also, the first N
While the MOS transistor Qn71 is off, the second NMOS transistor Qn72 functions as a MOS diode for suppressing noise propagation from the ground line 56 of the main power supply wiring system to the ground line 57 of the sub power supply wiring system. . Therefore, even when the second circuit block 52 has a driver circuit that handles the differential signal of the small voltage amplitude, the malfunction thereof can be prevented.

According to the twenty-seventh to thirty-second aspects of the invention, in the semiconductor memory device, the memory section 2 and the data processing section 3 are provided on the same semiconductor chip 1, so that the conventional memory chip and data processing chip are combined. It becomes unnecessary to exchange data between the chips, the data transfer rate can be easily increased, and the data processing system can be simplified and high-density mounted. Furthermore, since it is not necessary to provide a data bus connecting the memory chip and the data processing chip on the board as in the conventional case, the current for driving the data bus on the board can be omitted and the current consumption in the data processing system can be reduced. It can also be achieved. In addition, since the pad 4 is arranged just in the middle of the memory section 2 and the data processing section 3, it is possible to shorten the wiring distance to each. As a result, a delay in operating speed can be prevented. Furthermore, since the wiring area can be reduced, it is possible to prevent an increase in the chip area and reduce the input capacitance of the signal line terminal as seen from the outside.

According to the structure of the thirtieth aspect of the invention, the data processing unit 3 is arranged in the central portion of the semiconductor chip 1 and the plurality of memory units 2 are arranged in the peripheral portion of the semiconductor chip 1, so that the semiconductor The wiring distance between each memory unit 2 and the data processing unit 3 on the chip 1 becomes equal. This allows
It is possible to prevent the disadvantage that the operation speed becomes slow when accessing a specific memory unit.

According to the configuration of the thirty-third aspect, when the standby power supply current of the data processing unit 3 is inspected, the power supply voltage terminal 1 is provided by the through current interrupting means (switch element) 129.
Since the through current flowing from 25 to the ground voltage terminal 126 through the memory array supply voltage generation circuit (reference voltage generation circuit) 127 can be cut off, the standby power supply current defect of the data processing unit 3 can be detected.

According to the structure of the thirty-fourth aspect, the first power supply voltage terminal 125a for supplying the power supply voltage to the memory array 122 and the memory array supply voltage generation circuit (reference voltage generation circuit) 127 and the power supply voltage to the data processing unit 3. Is separately provided. Therefore, the shoot-through current is generated by the first power supply voltage terminal 125.
flow through the memory array supply voltage generation circuit 127 from a,
It does not affect the current flowing in the data processing unit 3 from the second power supply voltage terminal 125b. Accordingly, when the standby power supply current is inspected, the standby power supply current of the memory array 122 and the standby power supply current of the data processing unit 3 can be measured independently, so that the data processing unit 3 can be measured.
It is also possible to detect the power supply failure during standby. Further, claim 3
Since a control signal for controlling the through current interruption means (switch element) 129 of No. 3 is unnecessary, the control of the chip can be simplified.

[0058]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a DRAM according to the first embodiment. In FIG. 1, eight memory units 2 and a data processing unit 3 are provided in the same semiconductor chip 1, and the data processing unit 3 is arranged in the central portion of the semiconductor chip 1.
The individual memory units are arranged around the semiconductor chip 1 so as to surround the data processing unit 3. In addition, the semiconductor chip 1
A plurality of input pads 4 for inputting an external signal are arranged in an intermediate portion between the central portion and the peripheral portion in the intermediate portion, and the intermediate portions include the memory portion 2, the data processing portion 3, and the input pad 4.
It also serves as a wiring region in which wirings (not shown except for a part) for connecting and are respectively provided.

The DRAM in which the memory section 2, the data processing section 3 and the input pad 4 are arranged on the semiconductor chip 1 in this way
In the first, in consideration of the operation between the memory unit 2 and the data processing unit 3, the distance between each memory unit 2 and the data processing unit 3 on the semiconductor chip 1 becomes equal, so that the data processing unit 3 It is possible to prevent the disadvantage that the operation speed becomes slow when the particular memory unit 2 is accessed. Further, when considering the operation between the memory unit 2 or the data processing unit 3 and the outside of the semiconductor chip 1, the input pad 4 is arranged just in the middle of the memory unit 2 and the data processing unit 3. It is possible to shorten the wiring distance between the input pad 4 and the memory section 2 and the wiring distance between the input pad 4 and the data processing section 3, and as a result,
It is possible to prevent a delay in operating speed. Furthermore, since the wiring area can be reduced, it is possible to prevent an increase in the chip area and also reduce the input capacitance of the signal line terminal as viewed from the outside of the semiconductor chip 1.

Each memory unit 2 includes a memory core 5 including a memory array, a decoder circuit, a control circuit, and the like and an I.
I / O block 6 and a voltage conversion circuit 7 for generating an internal power supply voltage used inside the memory unit 2,
The O block 6 has a data transfer unit 6c for executing bidirectional data transfer between the memory unit 2 and the data processing unit 3 through the data bus 10. The data transfer unit 6c is composed of a driver circuit 6a for sending data to the data bus 10 for transfer to the data processing unit 3 and a receiver circuit 6b for receiving the data sent from the data processing unit 3 from the data bus 10. ing.

Further, the data processing section 3 is provided with a data processing block 8 and an I / O block 9 which perform original data processing, and the I / O block 9 is similar to the memory section 2 in the driver circuit 9a. And a data transfer section 9c including a receiver circuit 9b.

In this embodiment, the data transfer is performed only between the data processing section 3 and each memory section 2, but data may be exchanged between the memory sections 2. . Further, the pad 4 may not only input an external signal but also output a signal generated inside the DRAM to the outside.

FIG. 2 is a diagram showing another example of the layout of each constituent element of the DRAM. Here, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. As shown in FIG. 2, the memory unit 2 and the data processing unit 3 are provided on the same semiconductor chip 1, and the memory unit 2 is arranged on one side (on the right side in FIG. 2) on the semiconductor chip 1, and the data processing unit is provided. Three
Is arranged on the other side (left side in FIG. 2) on the semiconductor chip 1, and a plurality of input pads 4 are arranged between the part where the memory part 2 is arranged and the part where the data processing part 3 is arranged in the semiconductor chip 1. You may arrange in a line in the site | part between them, ie, a central part. When there are a plurality of memory units 2, the plurality of memory units 2 are arranged in a line on one side (for example, the right side in FIG. 2) on the semiconductor chip 1.

FIG. 3A shows the DR of this embodiment shown in FIG.
From AM, one memory section 2, one data processing section 3, and a circuit for externally supplying a predetermined voltage to these are shown in an excerpted manner.

In FIG. 3A, the memory array 122 constituting the memory core of the memory unit 2 and the data processing unit 3 are provided in the same semiconductor chip 1, and the semiconductor chip 1 further has a voltage conversion unit. Circuit 7 and memory array 1
22 and the power supply voltage pad 125 that supplies the power supply voltage VDD to the data processing unit 3, and the ground voltage pad 1 that supplies the ground voltage VSS to the memory array 122 and the data processing unit 3.
And 26 are provided. The voltage conversion circuit 7 receives the power supply voltage VDD from the power supply voltage pad 125 and the ground voltage VSS from the ground voltage pad 126, and generates, for example, a reference voltage or a half power supply voltage.

FIG. 3B is a block diagram showing the configuration of the voltage conversion circuit 7. As shown in FIG. 3B, the voltage conversion circuit 7 is a reference voltage generation circuit as a memory array supply voltage generation circuit. The reference voltage generating circuit 127 is composed of a driving circuit 128, a switch element 129 as a through current cut-off means which becomes non-conductive by activating the test control signal TCS, and the reference voltage generating circuit 127 is the simplest example. As shown in FIG. Note that FIG. 4 shows a circuit in a normal case where the switch element 129 is in a conductive state. In this case, a through current flows from the power supply voltage pad 125 to the ground voltage pad 126 through the resistor 130 of the reference voltage generating circuit 127. By flowing, the power supply voltage VDD is divided and VD is applied to the output node 131.
A voltage that is half that of D is generated.

D in which a memory array and a data processing unit are mounted together
In the RAM, when the standby power supply current is inspected, a through current flowing from the power supply voltage pad 125 to the ground voltage pad 126 through the reference voltage generation circuit 127 is two digits or more as compared with the standby power supply current of the data processing unit 3. Since it is three orders of magnitude larger, the power supply failure during standby of the data processing unit 3 is caused by the memory array 122.
There is a problem that it is hidden by the power supply current during standby.

However, in the present embodiment, in order to solve such a problem, between the power supply voltage pad 125 and the reference voltage generating circuit 127 of the voltage converting circuit 7, and between the ground voltage pad 126 and the voltage converting circuit. A switch element 129 is provided between the circuit 7 and the reference voltage generation circuit 127.

When the standby power supply current of the memory array 122 is to be tested, the test control signal TCS is inactivated and the switch element 129 is kept conductive to measure the current. On the other hand, when inspecting the standby power supply current of the data processing unit 3, the test control signal TCS is activated and the switch element 129 is brought into the non-conducting state, and the current is measured. As a result, a through current stops flowing, so the data processing unit 3
It is possible to detect defective power supply current during standby.

In this embodiment, the switch element 129 is provided between the power supply voltage pad 125 and the reference voltage generation circuit 127 of the voltage conversion circuit 7, and the ground voltage pad 1.
26 and the reference voltage generation circuit 127 of the voltage conversion circuit 7, respectively, but the same effect can be obtained by providing only one of them.

FIG. 5A shows another example of a circuit for supplying a predetermined voltage to the memory array 122 of the memory section 2 and the data processing section 3.

In FIG. 5A, the memory array 122 constituting the memory core of the memory unit 2 and the data processing unit 3 are provided on the same semiconductor chip 1, and the semiconductor chip 1 further has a voltage conversion unit. The circuit 7a, the first power supply voltage pad 125a for supplying the power supply voltage VDD to the memory array 122, the first ground voltage pad 126a for supplying the ground voltage VSS to the memory array 122, and the power supply voltage VDD for the data processing unit 3. And a second ground voltage pad 126b for supplying the ground voltage VSS to the data processing unit 3.
The voltage conversion circuit 7a includes a power supply voltage VDD from the first power supply voltage pad 125a and a first ground voltage pad 126a.
It receives the ground voltage VSS from, and generates, for example, a reference voltage or a half power supply voltage.

FIG. 5B is a block diagram showing the configuration of the voltage conversion circuit 7a. As shown in FIG. 5B, the voltage conversion circuit 7a is a reference voltage generation circuit as a memory array supply voltage generation circuit. The reference voltage generation circuit 127 is the same as the reference voltage generation circuit shown in FIG.

In this embodiment, the memory array 122
And the first power supply voltage pad 125a connected to the voltage conversion circuit 7a and the second power supply voltage pad 125b connected to the data processing unit 3 are physically separated from each other, and the memory array 122 and the voltage conversion circuit. A first ground voltage pad 126a connected to the circuit 7a and a data processing unit 3
Is physically separated from the second ground voltage pad 126b connected to. Therefore, a through current flows from the first power supply voltage pad 125a to the first ground voltage pad 126a through the reference voltage generation circuit 127, and from the second power supply voltage pad 125b through the data processing unit 3 to the second ground voltage pad 126b. It does not affect the current flowing to.
As a result, when the standby power supply current is inspected, the standby power supply current of the memory array 122 and the standby power supply current of the data processing unit 3 can be measured independently. Defective power supply current during standby can also be detected.

According to the present embodiment, since the test control signal for controlling the switch element as the through current cutoff means is unnecessary, the chip control can be simplified.

FIG. 6 is a DRA of the first embodiment shown in FIG.
The data transmission circuit is extracted from M and its configuration is shown. Here, as a data transmission circuit, a unidirectional circuit composed of a driver circuit 6a in the memory unit 2, a receiver circuit 9b in the data processing unit 3, and a set of data line pairs connecting these circuits is used. The data transmission circuit will be described. The data transmission circuit including the driver circuit 9a in the data processing unit 3, the receiver circuit 6b in the memory unit 2, and a set of data line pairs connecting these circuits is also the same. . The data bus 10 shown in FIG. 1 is composed of the two sets of data line pairs.

In FIG. 6, 6a is a driver circuit (data line drive circuit) of the memory section 2, 20 is a data line pair, and 3 is a data line pair.
0 is an amplifier circuit, 40 is a latch circuit, and the amplifier circuit 30
The receiver circuit 9b of the data processing unit 3 is composed of the latch circuit 40 and the latch circuit 40. VINT is the first step-down voltage, VI
NTL is the second step-down voltage, the latter lower than the former.
VINT and VINTL are respectively generated from the external power supply voltage VCC by a power supply voltage down circuit (not shown). For example, V
CC = 3.3V, VINT = 2.5V, VINTL =
It is 0.6V.

The driver circuit 6a operates from 0V to VINT.
A circuit for differentially driving the data line pair 20 by converting the input differential signal IN / XIN swinging up to 0V to VINTL into a small amplitude differential signal, and inputting IN / XIN Pair of differential input terminals 11 and 12, a control terminal 13 for inputting the first control signal CONT1, a pair of differential output terminals 14 and 15 connected to the data line pair 20, 1st to 6th N
It is provided with MOS transistors Qn11 to Qn16. Q
n11 has a gate on one terminal 11 of the pair of differential input terminals 11 and 12, and a drain on the pair of differential output terminals 1 and 12.
The source is connected to one terminal 14 of the terminals 4 and 15 to VINTL via Qn15. Qn12 has a gate on the other terminal 12 of the pair of differential input terminals 11 and 12, and a drain on the same terminal 1 as the drain of Qn11.
4, the source via Qn16 to the ground line (ground level: 0
V) respectively. The gate of Qn13 is Qn12
Of the differential output terminals 14 and 15 is connected to the other terminal 15 of the pair of differential output terminals 14 and 15, and the source thereof is connected to VINTL via Qn15 like the source of Qn11. The gate of Qn14 is the same as the gate of Qn11 at the terminal 11, the drain is the same as the drain of Qn13 at the terminal 15, and the source is the same as the source of Qn12 at Qn14.
Each is connected to the ground wire via 16. Qn15 and Q
The gates of n16 are commonly connected to the control terminal 13. The threshold voltages of Qn11 to Qn14 are all about 0.5V.

The data line pair 20 for transmitting the small-amplitude differential signal output from the driver circuit 6a to the amplifier circuit 30 has a resistance component RL and a capacitance component CL as distributed constants.

The amplifier circuit 30 is a circuit for amplifying the differential signal OUT / XOUT swinging from 0V to VINTL transmitted through the data line pair 20 into the differential signal AOT / XAOT swinging from 0V to VINT. Therefore, the pair of differential input terminals 31 and 32 for inputting OUT / XOUT, and the second control signal CONT2
, A pair of differential output terminals 34 and 35 connected to the latch circuit 40, first to sixth
PMOS transistors Qp31 to Qp36 and first to first
0 NMOS transistors Qn31 to Qn3a.

The latch circuit 40 uses the A signal from the amplifier circuit 30.
A circuit for latching OT / XAOT to obtain an output differential signal BOT / XBOT swinging from 0V to VINT, and a pair of differential input terminals 41, 42 for inputting AOT / XAOT, and a third Control signal CONT3
A control terminal 43 for inputting a signal, a pair of differential output terminals 44, 45 for outputting BOT / XBOT, and a first
And second PMOS transistors Qp41 and Qp42, and first to sixth NMOS transistors Qn41 to Qn46.

FIGS. 7A to 7G are operation timing charts of the data transmission circuit of FIG. When CONT1 is raised to high level, the data transmission cycle starts. IN / with amplitude VINT in each cycle
XIN is converted into OUT / XOUT having a small amplitude VINTL by the driver circuit 6a, and then amplified to AOT / XAOT having an amplitude VINT by the amplifier circuit 30.
At this time, CONT3 is raised to high level and AO
As a result of T / XAOT being latched by the latch circuit 40, B
OT / XBOT is confirmed. In this way BOT / X
As a result of CONT2 being raised to the high level after the BOT is determined, the operation of the amplifier circuit 30 is stopped in synchronization with the latching of AOT / XAOT by the latch circuit 40.

As described above, according to this embodiment, since the voltage amplitude of the data line pair 20 is limited to VINTL, the charge / discharge current of the data line pair 20 can be reduced. The present embodiment is particularly effective when the wiring capacitance of the data line pair 20 accounts for a large proportion of the capacitance of the entire data transmission circuit.

Further, in the driver circuit 6a composed only of NMOS transistors, the gates of Qn11 to Qn14 have IN swinging from 0V to VINT.
/ XIN is input, but the applied voltage between the source and drain of each is limited to the magnitude of VINTL, so that a sufficient gate-source voltage can be secured in each of Qn11 to Qn14. If the difference is between the magnitude of VINT and the magnitude of VINTL, the driver circuit 6a operates at high speed. Also, Qn11 to Qn
Even if the lower limit of the threshold voltage of each of 14 is limited to 0.3V to 0.6V, a large ability to drive the data line pair 20 can be obtained, so that the voltage amplitude smaller than 1.5V can be obtained without increasing the off leak current. Can realize high-speed data transmission.

Now, in the amplifier circuit 30 of this embodiment, the signals OUT / XOUT of the differential input terminals 31 and 32 are changed to Qp31 to Qp.
Since it is received by the gate of p34, there is no problem even if the signal makes a slow transition. However, since the amplitude of OUT / XOUT is limited to the size of VINTL, VINT
Through Qp31 to Qp34 always pass through current to the ground line. However, since CONT2 is given to the amplifier circuit 30 so as to stop the operation of the amplifier circuit 30 in synchronization with the latching of the AOT / XAOT by the latch circuit 40 as described above, the through current is suppressed by Qp35 and Qp36. . Further, since the latch circuit 40 is provided in the subsequent stage of the amplifier circuit 30, the output load of the former becomes small, and the size of each MOS transistor forming the amplifier circuit 30 can be reduced, so that Qp35 and Qp36 are turned on. The through current can be suppressed to be small even during the period.

The VCC may be directly applied to the application position of the VINT generated from the VCC. IN / XIN, AOT / XAOT and BOT / XB
A suitable high level of OT is in the range of 1V to 3.3V, and a high level of OUT / XOUT is 0.1V to 1.5V.
The range of V is suitable.

In the driver circuit 6a, the threshold voltage of Qn11 and Qn13 located on the power supply side can be set lower than the threshold voltage of Qn12 and Qn14 located on the ground side. Specifically, Qn11 and Q
n13 threshold voltage to 0V to 0.3V, Qn12 and Qn
The threshold voltage of n14 is set to 0.3V to 0.6V, respectively. Thus, even if the threshold voltage of Qn11 and Qn13 is set lower than the value (0.3V to 0.6V) which is the lower limit of the prior art, the potentials of the differential input terminals 11 and 12 are both 0V during standby. If it is controlled so that Qn11 and Qn13
Off-leakage current is blocked by Qn12 and Qn14. Therefore, the threshold voltage of Qn11 and Qn13 is set to Q
By setting it lower than the threshold voltage of n12 and Qn14, the driving ability of Qn11 and Qn13 can be further increased without increasing the off-leakage current. Qn11 and Qn
Since the gate-source voltage of 13 is inevitably smaller than that of Qn12 and Qn14, lowering the threshold voltage of Qn11 and Qn13 is effective for increasing the driving capability of the driver circuit 6a.

FIG. 8 is a wiring diagram showing measures against noise in the ground line in the DRAM of the first embodiment. This noise countermeasure is from 0V to VINTL in the driver circuit 6a.
This is in view of handling a small-amplitude differential signal that swings up to.

In FIG. 8, reference numeral 51 designates a first circuit block which operates at the standard amplitude VINT, and in addition to the amplifier circuit 30 and the latch circuit 40 of the receiver circuit 9b, a timing generator, a decoder circuit and the like in the DRAM concerned. Contains. Reference numeral 52 denotes a second circuit block that operates with a small amplitude VINTL, and the driver circuit 6a corresponds to this. The first circuit block 51 includes the ground wire 5
3 to the ground pad 55. On the other hand, the second circuit block 52 is connected to the ground pad 55 via a ground line 54 provided independently of the ground line 53 of the first circuit block 51. Here, if a very large current flows through the ground line 53 due to the operation of the circuit in the first circuit block 51, the resistance component RL1 of the ground line 53.
As a result, a voltage drop occurs and the ground level of the first circuit block 51 fluctuates greatly. However, the ground wire 5
4 is provided independently of the ground line 53 of the first circuit block 51, the driver circuit 6a in the second circuit block 52 is less affected by fluctuations in the ground level of the first circuit block 51. Normal operation can be continued without receiving. RL2 indicates the resistance component of the ground line 54.

As described above, by adopting the ground wiring as shown in FIG. 8, it is possible to suppress the intrusion of the power source noise into the second circuit block 52 due to the operating current of the first circuit block 51 to some extent. You can

FIG. 9 is a wiring diagram showing another example of measures against noise in the ground line. Similarly to the case of FIG. 8, the wiring of the ground line in FIG. 9 also has noise countermeasures in view of handling differential signals of small amplitude in the driver circuit 6a. In FIG. 9, the first and second circuit blocks 51,
Reference numeral 52 is a circuit block similar to that shown in FIG. The ground lines include a first ground line (main power supply wiring system ground line) 56 for the first circuit block 51 and a local second ground line (sub power supply line) for the second circuit block 52. System ground line) 57. The first ground line 56 is connected to the ground pad 55, and the second ground line 57 is connected to the first ground line 56 via the power supply system coupling circuit 70. Reference numeral 80 is a power supply step-down circuit for supplying VINTL to the second circuit block 52.

The power supply system coupling circuit 70 couples the first ground line 56 and the second ground line 57 so as to suppress noise propagation from the first circuit block 51 to the second circuit block 52. Circuit, and includes first and second NMOS transistors Qn71 and Qn72 connected in parallel with each other. The gate of Qn71 is supplied with the control clock through the control terminal 71. On the other hand, the gate of Qn72 is connected to the second ground line 57 so that Qn72 functions as a MOS diode.

Two NMs constituting the power supply system coupling circuit 70
Qn71 of the OS transistors connects the first ground line 56 and the second ground line 57 with low impedance by turning on in response to a control clock supplied through the control terminal 71 during standby of the DRAM. Also, DRA
During operation of M, that is, while Qn71 is off, Qn
The reference numeral 72 indicates the floating of the ground voltage level in the first ground line 56 due to the operation of the first circuit block 51.
It functions as a MOS diode to prevent the signal from being transmitted to 7.

As described above, the driver circuit 6a has 0
It handles a small-amplitude differential signal swinging from V (ground level) to VINTL. VINTL is
It is a small voltage of about 0.6V. Therefore, even if the potential of the second ground line 57 floats up even slightly, the driver circuit 6a in the second circuit block 52 may malfunction. However, according to the present embodiment, it is possible to effectively suppress the intrusion of the power supply noise due to the operating current of the first circuit block 51 into the second circuit block 52, and thus the second circuit block 52. It is possible to prevent malfunction of the driver circuit 6a therein.

Incidentally, Qn72 which functions as a MOS diode
The smaller the threshold voltage of, the better, and it is desirable that it is 0 V or less.

FIG. 10 is a circuit diagram showing an internal configuration of power supply voltage down converter 80 shown in FIG. This power supply voltage down circuit 80
Is a circuit for generating VINTL from VINT generated from VCC by another power supply voltage down circuit (not shown), and is a control terminal 81 for inputting a control clock.
, An output terminal 82 for outputting VINTL, a resistor 83, and first to third PMOS transistors Qp81 to
Qp83 and the first to fourth NMOS transistors Qn81 to
It is equipped with Qn84.

A resistor 83 and a Qn81 connected in series with each other.
And constitute a reference potential generation circuit 84 for generating a potential VREF that serves as a reference for VINTL. The reference potential generating circuit 84 uses the threshold voltage of Qn81. Then, at least the reference potential generation circuit 8
The ground potential of 4 is taken from the second ground line 57 as shown in FIG.

Qp81, Qp82 and Qn82 to Qn84 are V
A comparison circuit 85 for comparing INTL and VREF is configured. Qp81 and Qp82 are each connected to VINT so as to form a parallel current mirror type current source. Qn82 and Qn83 are connected to the ground side of the current source composed of Qp81 and Qp82, and VREF is applied to the gate of Qn82 so as to form a differential amplifier.
VINTL is fed back to the gate of Qn83. The sources of Qn82 and Qn83 are connected to the ground line via Qn84 as a common switch element whose gate is connected to the control terminal 81. Moreover, the threshold voltage of Qn82 and Qn83 is set to be low (0 V to 0.3 V) like Qn11 and Qn13 in the driver circuit so as to enhance the driving capability thereof.

The Qp83 constitutes an output circuit 86 for outputting VINTL to the output terminal 82, and the potential of the connection point of Qp81 and Qn82 is applied to the gate thereof.

According to the configurations of FIG. 9 and FIG.
Even if the potential of the ground line 57 changes, the output VREF of the reference potential generating circuit 84 changes according to this change, so that the voltage between the output terminal 82 of the power supply step-down circuit 80 and the second ground line 57. Is kept at a constant value VINTL. Therefore,
There is an effect that the malfunction of the driver circuit in the second circuit block 52 can be surely prevented. Moreover, since the threshold voltage of Qn82 and Qn83 in the comparison circuit 85 is set low so as to increase the driving ability, VREF and VI are set.
Even if the level of NTL is low, the normal operation of the comparison circuit 85 and the good performance of the power supply step-down circuit 80 are guaranteed.

In the configuration of FIG. 10, VINT to VI
Although NTL is generated, VINTL may be generated directly from VCC.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 is a circuit diagram showing a part of the data transmission circuit in the DRAM of the second embodiment. The data transmission circuit of the second embodiment is the same as that of the DRAM of the first embodiment. An equalizer circuit 60 is further added between the driver circuit 6a and the data line pair 20 in the data transmission circuit.

In FIG. 11, the internal structure of the driver circuit 6a is the same as that of the first embodiment (see FIG. 6), but unlike the CONT1 of the first embodiment, the control terminal is different in this embodiment. First control signal CON applied to 13
T1a is held high only in the first half of each data transmission cycle.

The equalizer circuit 60 is a circuit for equalizing the potential of the data line pair 20, and includes a pair of differential input terminals 61 and 62 connected to the differential output terminals 14 and 15 of the driver circuit 6a. A control terminal 63 for inputting the equalize control signal EQ, a pair of differential output terminals 64 and 65 connected to the data line pair 20, and one NMO.
S-transistor Qn61. Qn61 is interposed between the differential output terminals 64 and 65 so as to equalize the potential of the data line pair 20, and EQ is applied to its gate.

The amplifier circuit and the latch circuit similar to those in the first embodiment are connected to the subsequent stage of the data line pair 20 to constitute the entire data transmission circuit of the present embodiment. Is omitted.

FIGS. 12A to 12H are operation timing charts of the data transmission circuit of this embodiment. In the first half of each data transmission cycle, CONT1a and CONT3 are raised to high level. As a result, the amplitude VIN
IN / XIN having T is converted into OUT / XOUT having a small amplitude VINTL by the driver circuit 6a, and then AOT / XA having an amplitude VINT is given by the amplifier circuit 30.
The AOT / XAOT is amplified by the OT and the latch circuit 4
As a result of being latched with 0, BOT / XBOT is determined.
After BOT / XBOT is established in this way, that is, in the latter half of the data transmission cycle, CONT2 and EQ are
Is launched to a high level. As a result, the amplifier circuit 3
The operation of 0 is stopped in synchronization with the latch of AOT / XAOT by the latch circuit 40, and at the same time, the data line pair 2
The potential OUT / XOUT of 0 is Qn of the equalizing circuit 60.
Equalized by 61.

According to this embodiment, the equalization of the data line pair 20 shortens the time until the potential difference reaches a predetermined value, and as a result, the data transmission is further speeded up. Moreover, the equalization operation is performed in the latter half of the data transmission cycle so that the access speed is not adversely affected.

Although the equalizing NMOS transistor Qn61 is interposed between the differential output terminals 14 and 15 of the driver circuit 6a and the data line pair 20 in this embodiment, the transistor is the data line pair 20. It may be provided anywhere as long as the potential of can be equalized.

Here, the performance comparison between the data transmission circuit in the conventional DRAM and the data transmission circuits according to the first and second embodiments will be described.

FIG. 13A shows a simulation circuit (DT) of a driver circuit having a CMOS structure in a conventional data transmission circuit. The two control signals CONT / XCONT in FIG. 13A are complementary signals. FIG. 13B shows a simulation circuit (SHT1) corresponding to the driver circuit having the NMOS structure in the data transmission circuit of the first embodiment, and FIG.
3 shows a simulation circuit (SHT2) corresponding to a driver circuit to which an equalizing circuit is added in the data transmission circuit of the embodiment.

FIGS. 14A to 14D show DT and SHT1.
FIG. 6 is a timing chart showing simulation conditions for SHT2 and SHT2. In this simulation, 16-bit data was transmitted with a cycle time t _C of 20 ns. VIN
TL = 0.6V, RL = 1.8kΩ, CL = 4.5pF
Is.

FIG. 15 is a diagram showing simulation results regarding the current consumption of each of DT, SHT1 and SHT2. Compared to DT, VINT = 2.5V in SHT1
At that point, the current consumption is reduced by 15 mA.
Further, the current consumption is further reduced in SHT2 as compared with SHT1.

FIG. 16 is a diagram showing simulation results concerning delay times of DT, SHT1 and SHT2. CONT / XCONT for DT, CONT1 for SHT1, and CONT1a for SHT2 are VIN respectively.
It is a comparison of the time (delay time t _D ) from the time when the potential changes to ½ of T until the potential difference of 0.1 V appears as OUT / XOUT. SHT compared to DT
It has been shown that 1 and SHT2 can achieve higher speed data transmission than SHT1.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 17 is a circuit diagram of an amplifier circuit 30a used in a data transmission circuit in a DRAM according to the third embodiment. The data transmission circuit of the third embodiment is a DRAM according to the first embodiment. Amplifier circuit 3 in the data transmission circuit in
0 is replaced with an amplifier circuit 30a. A driver circuit and a data line pair similar to those in the first embodiment are connected to the front stage of the amplifier circuit 30a in FIG. 17, and a rear stage of the amplifier circuit 30a is similar to that in the first embodiment. The entire data transmission circuit is configured by connecting the latch circuits. As in the case of the second embodiment, an equalize circuit may be interposed between the driver circuit and the data line pair.

The structure of the amplifier circuit 30a shown in FIG. 17 is obtained by adding a power supply control unit 37 to the amplifier unit 36 having the same structure as the amplifier circuit 30 of the first embodiment (see FIG. 6).

The power supply control section 37 includes the differential output terminals 34, 3
5, which is a circuit portion for controlling the power supply to the amplification unit 36 based on the output from 5, and includes first and second PMOS transistors Qp37 and Qp38 connected in series. Qp37 and Qp38 are interposed between Qp36 and VINT for controlling the power supply to the latter half of the amplification section 36, and the gate of Qp37 is one of the pair of differential output terminals 34 and 35. The terminal 35 and the gate of Qp38 are connected to the other terminal 34, respectively.

Qp37 and Qp constituting the power supply control unit 37
The on / off of 38 is controlled based on the differential signal of the amplitude VINT at the pair of differential output terminals 34 and 35 amplified by the amplifier 36. After the output of the amplifier circuit 30a and the output of the latch circuit of the subsequent stage are determined, the amplifier circuit 30a
When a high level CONT2 is input to the control terminal 33 so as to stop the operation of the differential output terminals 34, 3
Either one of Qp37 and Qp38 must be turned off because either one of Vp5 and VINT has almost the same potential. Therefore, the through current flowing through Qp36 can be completely cut off, and the operation of the amplification section 36 is surely stopped. During the operation of the amplification section 36, the potentials of the differential output terminals 34 and 35 are equalized to Qp37 and Qp37.
Both 38 turn on.

The amplifier circuit 30a of the present embodiment automatically stops its operation when the outputs at the differential output terminals 34 and 35 are fixed to some extent even when the turning off of the Qp36 is delayed, so that the current consumption is reduced. It is valid.

In this embodiment, a feedback P similar to Qp37 and Qp38 is provided between Qp35 and VINT for controlling the power supply to the first half of the amplifier 36.
The amplifying section 3 does not include the MOS transistor.
This is because 6 may not be able to follow the potential change at the differential input terminals 31 and 32. This is because an erroneous signal (erroneous data) may be temporarily input to the differential input terminals 31 and 32. Further, since the load of the first half portion of the amplifier 36 is small, the through current flowing through Qp35 is very small. However, when it is guaranteed that the input data does not change, Qp35 and V
It is desirable to interpose a feedback PMOS transistor also between INT and INT.

The DRAM has been described above as an example of the LSI provided with the data transmission circuit. However, the present invention can be applied to any LSI provided with a data transmission circuit. It is also applicable to data transmission between multiple chips.

[0124]

As described above, according to the data transmission circuit for a semiconductor integrated circuit of the invention of claims 1 to 11, data transmission is performed by a differential signal having a voltage amplitude smaller than the input differential signal. Therefore, even when the wiring length of the signal line pair is large, the influence of the parasitic resistance and the parasitic capacitance of the signal line pair can be suppressed, and the charge / discharge current and the signal delay can be reduced. Therefore, a semiconductor of high speed and low power consumption can be realized. An integrated circuit can be realized. Furthermore, since the peak current can be reduced by reducing the charging / discharging current, the reliability and noise resistance of the signal wiring are improved. Further, since the latch circuit is provided in the subsequent stage of the amplifier circuit, the output load of the amplifier circuit is reduced and the size thereof can be reduced, so that the shoot-through current can be reduced.

According to the data transmission circuit of the eighth aspect of the present invention, the ground line of the driver circuit is provided independently of the ground lines of the other circuits, so that the influence of the fluctuation of the ground level due to the operation of the other circuits is affected. It is possible to ensure a stable operation of the driver circuit without being affected.

According to the data transmission circuit of the present invention, the power consumption of the semiconductor integrated circuit can be further reduced by stopping the operation of the amplifier circuit after latching the output of the amplifier circuit. .

According to the data transmission circuit of the tenth and eleventh aspects of the present invention, by further providing the equalizing circuit, the time required for the potential difference of the signal line pair to reach a predetermined value is shortened, resulting in data transmission. It will be even faster.

According to the data line drive circuit of the twelfth to eighteenth inventions, by adopting the NMOS configuration, the lower limit of the threshold voltage of each NMOS transistor is 0.3.
Even if the voltage is limited to V to 0.6V, a large ability to drive the signal line pair can be obtained, so that the off-leakage current is increased to 1.5
High-speed data transmission can be realized with a voltage amplitude smaller than V. In addition, the conventional CMOS configuration can reduce the power consumption of the semiconductor integrated circuit to two because only two power sources can be used. Also,
Since it can be configured with only NMOS transistors, it is easy to manufacture. In addition, by setting the threshold voltage of the power-supply-side NMOS transistor lower than the threshold voltage of the ground-side NMOS transistor, it is possible to further enhance the driving capability of the power-supply-side NMOS transistor without increasing the off-leakage current. .

According to the amplifier circuit of the nineteenth and twentieth aspects of the invention, the power supply to the amplifying section is controlled based on the output differential signal amplified by the amplifying section, not on the input differential signal having a small voltage amplitude. It As a result, the operation of the amplification unit can be reliably stopped, and the power consumption of the semiconductor integrated circuit can be further reduced.

According to the semiconductor integrated circuit of the invention of claims 21 to 26, the power supply system coupling circuit interposed between the main power supply wiring system and the sub power supply wiring system is changed from the first circuit block to the second circuit block. Therefore, even if the second circuit block has a driver circuit that handles a differential signal having a small voltage amplitude, the malfunction can be prevented.

According to the semiconductor memory device of the twenty-seventh to thirty-second aspects, the data processing speed can be increased, a simple data processing system can be constructed, and the optimum layout in the semiconductor chip can be realized. be able to.

According to the semiconductor memory device of the thirty-third and thirty-fourth aspects of the present invention, the data processing speed can be increased, a simple data processing system can be constructed, and the standby power supply current can be efficiently inspected. Can be executed.

As described above, according to the present invention, high-speed data transmission can be realized with low power consumption even if the wiring is long.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a DRAM according to a first embodiment of the present invention.

FIG. 2 is a layout diagram showing another example of the arrangement of each component of the DRAM.

3A is a block diagram showing an example of a circuit for supplying a predetermined voltage to a memory array and a data processing unit in the DRAM of the first embodiment, and FIG. 3B is a block diagram of FIG. It is a block diagram which shows the structure of the voltage conversion circuit in a circuit.

4 is a circuit diagram showing a configuration of a reference voltage generation circuit in the voltage conversion circuit of FIG. 3 (b).

FIG. 5A is a block diagram showing another example of a circuit for supplying a predetermined voltage to a memory array and a data processing unit in the DRAM of the first embodiment, and FIG. 2] A block diagram showing the configuration of a voltage conversion circuit in the circuit of FIG.

FIG. 6 is a circuit diagram showing a configuration of a data transmission circuit in the DRAM of the first embodiment.

7A to 7G are timing charts showing the operation of the data transmission circuit according to the first embodiment.

FIG. 8 is a wiring diagram showing an example of a ground line in the DRAM of the first embodiment.

FIG. 9 is a wiring diagram showing another example of a ground line in the DRAM of the first embodiment.

10 is a circuit diagram showing a configuration of a power supply step-down circuit in FIG.

FIG. 11 is a circuit diagram showing a part of a data transmission circuit in a DRAM according to a second embodiment of the present invention.

12A to 12H are timing charts showing the operation of the data transmission circuit according to the second embodiment.

13A is a circuit diagram showing a circuit to be simulated in a data transmission circuit in a conventional DRAM, and FIG. 13B is a data transmission circuit in the DRAM according to the first embodiment; It is a circuit diagram which shows the circuit used as a simulation, and (c) is a circuit diagram which shows the circuit used as a simulation in the data transmission circuit in the DRAM which concerns on a 2nd Example.

14A to 14D are timing charts showing simulation conditions of each circuit of FIGS. 13A to 13C.

FIG. 15 is a diagram showing a simulation result relating to current consumption of each circuit of FIGS.

FIG. 16 is a diagram showing a simulation result regarding a delay time of each circuit of FIGS.

FIG. 17 is a circuit diagram showing a configuration of an amplifier circuit used in a data transmission circuit in a DRAM according to a third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of a receiver circuit of a conventional data transmission circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor chip 2 memory part 3 data processing part 4 input pad 6a memory part driver circuit (first circuit) 6b memory part receiver circuit 7, 7a voltage conversion circuit 9a data processing part driver circuit 9b data processing part receiver Circuit 10 Data bus 11,12 Differential input terminal of driver circuit 14,15 Differential output terminal of driver circuit 20 Data line pair (signal line pair) 30,30a Amplifier circuit (second circuit) 31,32 Amplifier circuit Differential input terminals 34, 35 Differential output terminals of amplification circuit 36 Amplification unit 37 Power supply control unit 40 Latch circuit (third circuit) 51 Circuit block operating at standard amplitude (first circuit block) 52 Operation at small amplitude Circuit block (second circuit block) 56 First ground line (ground line of main power supply wiring system) 57 Second ground line Sub power supply wiring system ground line) 60 Equalize circuit (4th circuit) 70 Power supply system coupling circuit 80 Power supply voltage down circuit 84 Reference potential generation circuit 85 Comparison circuit 86 Output circuit 122 Memory array 125 Power supply voltage pad (power supply voltage terminal) 125a First power supply voltage pad (first power supply voltage terminal) 125b Second power supply voltage pad (second power supply voltage terminal) 126 Ground voltage pad (ground voltage terminal) 126a First ground voltage pad (first ground) Voltage terminal) 126b second ground voltage pad (second ground voltage terminal) 127 reference voltage generation circuit (memory array supply voltage generation circuit) 129 switch element (through current interrupting means) CONT1, CONT1a first control signal CONT2 2 control signal CONT3 3rd control signal EQ equalize control signal Qn11 driver First NMOS transistor Qn12 of the driver circuit second NMOS transistor Qn13 third NMOS transistor of the driver circuit Qn14 fourth NMOS transistor of the driver circuit Qn71 first NMOS transistor of the power system coupling circuit Qn72 power system coupling circuit Second NMOS transistor Qp37 first PMOS transistor Qp38 power supply control section second PMOS transistor Vp38 power supply control section VINT first step-down voltage VINTL second step-down voltage VREF reference potential

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiro Yamada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Akihiro Sawada 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 72) Inventor Hirohito Kikukawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masashi Agata 1006 Kadoma, Kadoma City, Osaka Pref. Matsushita Electric Industrial Co., Ltd. 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd.

Claims (34)

[Claims] 1. A data transmission circuit for a semiconductor integrated circuit, comprising: a first differential signal having a first amplitude and a second differential signal having a second amplitude smaller than the first amplitude. A first circuit for converting the second differential signal transmitted through the signal line pair, a signal line pair for transmitting the second differential signal converted by the first circuit, Three
And a third circuit for latching the third differential signal converted by the second circuit. Data transmission circuit. 2. The data transmission circuit according to claim 1, wherein the second circuit is input through a pair of differential input terminals for inputting the differential signal, and the pair of differential input terminals. An amplifier for amplifying a differential signal, a pair of differential output terminals for outputting the differential signal amplified by the amplifier, and to the amplifier based on outputs from the pair of differential output terminals. And a power supply control unit for controlling power supply of the data transmission circuit. 3. The data transmission circuit according to claim 1, wherein the third amplitude of the third differential signal is equal to the first amplitude of the first differential signal. circuit. 4. The data transmission circuit according to claim 1, wherein the first to third differential signals are logic signals each having a high level and a low level, and the low level of each logic signal is equal to the ground level. A data transmission circuit characterized by the above. 5. The data transmission circuit according to claim 1, wherein the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is from outside the semiconductor integrated circuit. A data transmission circuit, which is equal to a given power supply voltage. 6. The data transmission circuit according to claim 1, wherein the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is external to the semiconductor integrated circuit. A data transmission circuit, which is equal to a first step-down voltage generated inside the semiconductor integrated circuit based on a given power supply voltage. 7. The data transmission circuit according to claim 1, wherein the second differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is external to the semiconductor integrated circuit. A data transmission circuit, which is equal to a second step-down voltage generated inside the semiconductor integrated circuit based on a given power supply voltage. 8. The data transmission circuit according to claim 1, wherein the ground line of the first circuit is provided independently of the ground lines of other circuits in the semiconductor integrated circuit. Transmission circuit. 9. The data transmission circuit according to claim 1, wherein the operation of the second circuit is stopped in synchronization with the latching of the third differential signal by the third circuit. Data transmission circuit. 10. The data transmission circuit according to claim 1, further comprising a fourth circuit that equalizes the potential of the signal line pair. 11. The data transmission circuit according to claim 10, wherein the first differential signal is used to obtain the third differential signal in the first half of one data transmission cycle.
And the second circuit is operated, and in the latter half of the data transmission cycle, the operation of the second circuit is stopped in synchronization with the latching of the third differential signal by the third circuit, and The data transmission circuit, wherein the fourth circuit is operated so as to equalize the potential of the signal line pair. 12. A data line drive circuit for differentially driving a data line pair in a semiconductor integrated circuit, comprising: a pair of differential input terminals to which a first differential signal having a first amplitude is input. , A pair of differential output terminals connected to the data line pair so as to output a second differential signal having a second amplitude, and one terminal of one of the pair of differential input terminals. A first NMOS transistor having a gate, a drain connected to one terminal of the pair of differential output terminals, and a source connected to a power supply line; and one of the pair of differential input terminals A second NMOS transistor having a gate connected to the other terminal of the first NMOS transistor, a drain connected to the drain of the first NMOS transistor, and a source connected to a ground line; and the second NMOS transistor. A third NMOS transistor having a gate connected to the gate, a drain connected to the other terminal of the pair of differential output terminals, and a source connected to the power supply line; and the first NMOS transistor. A fourth NMOS transistor having a gate connected to the gate of the NMOS transistor, a drain connected to the drain of the third NMOS transistor, and a source connected to the ground line. Data line driving circuit. 13. The data line drive circuit according to claim 12, wherein the second amplitude of the second differential signal is smaller than the first amplitude of the first differential signal. Line drive circuit. 14. The data line drive circuit according to claim 12, wherein the first and second differential signals are logic signals each having a high level and a low level, and the low level of each logic signal is a ground level. A data line drive circuit characterized by being equal. 15. The data line driving circuit according to claim 12, wherein the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is external to the semiconductor integrated circuit. A data line drive circuit, which is equal to a power supply voltage given by the device. 16. The data line drive circuit according to claim 12, wherein the first differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is external to the semiconductor integrated circuit. A data line driving circuit, which is equal to a first step-down voltage generated inside the semiconductor integrated circuit on the basis of a power supply voltage supplied from the data line driving circuit. 17. The data line drive circuit according to claim 12, wherein the second differential signal is a logic signal having a high level and a low level, and the high level of the logic signal is outside the semiconductor integrated circuit. A data line drive circuit, which is equal to a second step-down voltage generated inside the semiconductor integrated circuit on the basis of a power supply voltage supplied from 18. The data line drive circuit according to claim 12, wherein the threshold voltages of the first and third NMOS transistors are lower than the threshold voltages of the second and fourth NMOS transistors. A data line drive circuit characterized by: 19. An amplifier circuit for amplifying a differential signal in a semiconductor integrated circuit, comprising: a pair of differential input terminals for inputting the differential signal; and an input through the pair of differential input terminals. An amplifier for amplifying a differential signal, a pair of differential output terminals for outputting the differential signal amplified by the amplifier, and to the amplifier based on outputs from the pair of differential output terminals. An amplifier circuit comprising: a power supply control unit that controls the power supply of the power supply. 20. The amplifier circuit according to claim 19, wherein the power supply control unit includes first and second PMOS transistors connected in series and interposed between a power supply line and the amplification unit, The gate of the first PMOS transistor is connected to one terminal of the pair of differential output terminals, and the gate of the second PMOS transistor is connected to the other terminal of the pair of differential output terminals. An amplifier circuit characterized in that. 21. A main power supply wiring system and a sub power supply wiring system, each of which has a power supply line and a ground line, a first circuit block directly connected to the main power supply wiring system, and a direct power supply wiring system. A connected second circuit block and a power supply system coupling interposed between the main power supply wiring system and the sub power supply wiring system so as to suppress noise propagation from the first circuit block to the second circuit block. And a semiconductor integrated circuit. 22. The semiconductor integrated circuit according to claim 21, wherein the second circuit block outputs a first differential signal having a first amplitude so as to differentially drive the data line pair. 1
A data line driving circuit for converting into a second differential signal having a second amplitude smaller than the amplitude of, wherein the first and second differential signals are logic signals having a high level and a low level, respectively. The low level of each logic signal is equal to the voltage level of the ground line of the sub power supply wiring system. 23. The semiconductor integrated circuit according to claim 21, wherein the power supply system coupling circuits are connected in parallel to each other and are interposed between the ground line of the main power supply wiring system and the ground line of the sub power supply wiring system. A gate of the first NMOS transistor is supplied with a control clock, and a gate of the second NMOS transistor is connected to a ground line of the sub power supply wiring system. A characteristic semiconductor integrated circuit. 24. The semiconductor integrated circuit according to claim 23, wherein the threshold voltage of the second NMOS transistor is 0V.
A semiconductor integrated circuit characterized by the following: 25. The semiconductor integrated circuit according to claim 21, wherein a step-down voltage is supplied to the second circuit block,
The power supply step-down circuit that generates the step-down voltage based on an externally-supplied power supply voltage is further provided, and the power supply step-down circuit has a reference potential generation circuit that generates a reference voltage of the step-down voltage. A semiconductor integrated circuit, wherein a ground line of the potential generating circuit is directly connected to a ground line of the sub power supply wiring system. 26. The semiconductor integrated circuit according to claim 25, wherein the power supply step-down circuit further includes a comparison circuit that compares the reference potential generated by the reference potential generation circuit with the step-down voltage. Is a pair of PMOS transistors each connected to a power supply line so as to form a parallel current mirror type current source, and a pair of PMOS transistors that are input with the reference potential and the step-down voltage. A pair of NMOS transistors connected to the ground side of the PMOS transistor, and a switch element interposed between the source of each of the pair of NMOS transistors and the ground line, the pair of NMOS transistors having a driving capability. A semiconductor integrated circuit, wherein each threshold voltage is set to be low so as to increase. 27. A data processing unit and at least one memory unit provided on the same semiconductor chip, and at least one of an input of a signal from the outside and an output of a signal to the outside provided on the semiconductor chip. A semiconductor memory device, comprising: a pad that performs one of the above, wherein the pad is arranged between a portion of the semiconductor chip where the memory portion is arranged and a portion where the data processing portion is arranged. 28. The semiconductor memory device according to claim 27,
The data transmission circuit may further include a data transmission circuit for transmitting data between the memory unit and the data processing unit, wherein the data transmission circuit has a first differential signal having a first amplitude smaller than the first amplitude. A first circuit for converting into a second differential signal having a second amplitude; a signal line pair for transmitting the second differential signal converted by the first circuit; and a signal line pair The second differential signal transmitted through the third
A second circuit for converting into a third differential signal having an amplitude of, and a third circuit for latching the third differential signal converted by the second circuit. Storage device. 29. The semiconductor memory device according to claim 27, wherein there are a plurality of said memory sections, and further comprising a data transmission circuit for transmitting data between said memory sections, wherein said data transmission circuit comprises: A first circuit for converting a first differential signal having an amplitude of 1 to a second differential signal having a second amplitude smaller than the first amplitude; and a second circuit converted by the first circuit. And a second differential signal transmitted through the signal line pair and a third differential signal transmitted through the signal line pair.
A second circuit for converting into a third differential signal having an amplitude of, and a third circuit for latching the third differential signal converted by the second circuit. Storage device. 30. The semiconductor memory device according to claim 27, wherein a plurality of the memory units are present, the data processing unit is arranged in a central portion of the semiconductor chip, and the plurality of memory units are provided in the semiconductor chip. A semiconductor memory device, wherein the pad is arranged in a peripheral portion, and the pad is arranged in an intermediate portion which is a portion between the central portion and the peripheral portion of the semiconductor chip. 31. The semiconductor memory device according to claim 30,
The data transmission circuit may further include a data transmission circuit for transmitting data between the memory unit and the data processing unit, wherein the data transmission circuit has a first differential signal having a first amplitude smaller than the first amplitude. A first circuit for converting into a second differential signal having a second amplitude; a signal line pair for transmitting the second differential signal converted by the first circuit; and a signal line pair The second differential signal transmitted through the third
A second circuit for converting into a third differential signal having an amplitude of, and a third circuit for latching the third differential signal converted by the second circuit. Storage device. 32. The semiconductor memory device according to claim 30,
The data transmission circuit further includes a data transmission circuit that transmits data between the memory units, and the data transmission circuit has a first differential signal having a first amplitude and a second amplitude that is smaller than the first amplitude. A first circuit for converting into a second differential signal; a signal line pair for transmitting the second differential signal converted by the first circuit; and a second line transmitted through the signal line pair. The differential signal of the third
A second circuit for converting into a third differential signal having an amplitude of, and a third circuit for latching the third differential signal converted by the second circuit. Storage device. 33. A memory array and a data processor provided on the same semiconductor chip, and a power supply voltage terminal for supplying a power supply voltage to the memory array and the data processor provided on the semiconductor chip.
A ground voltage terminal provided on the semiconductor chip for supplying a ground voltage to the memory array and the data processing unit;
A memory array supply voltage generating circuit provided in the semiconductor chip for receiving a power supply voltage from the power supply voltage terminal and a ground voltage from the ground voltage terminal and generating a memory array supply voltage to be supplied to the memory array; A semiconductor memory device further comprising: a through-current cutoff unit that is provided in the power supply voltage terminal and cuts off a through-current flowing through the memory array supply voltage generation circuit to the ground voltage terminal. 34. A memory array and a data processing unit provided on the same semiconductor chip, the first power supply voltage terminal provided on the semiconductor chip for supplying a power supply voltage to the memory array, and the semiconductor. A second power supply voltage terminal provided on a chip for supplying a power supply voltage to the data processing unit, and a memory provided on the semiconductor chip and receiving a power supply voltage from the first power supply voltage terminal and supplied to the memory array. A semiconductor memory device further comprising: a memory array supply voltage generation circuit for generating an array supply voltage.