JP2872253B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device.

(Prior art)

One of the semiconductor integrated circuit devices adopting the master slice method that can design many kinds in a small amount in a short time is a gate array. Gate arrays are mainly CPU (central process)
ssing unit). The gate array inputs an external signal to a gate formed in a logic region through an input buffer circuit in a peripheral portion, and outputs an output signal from a gate in the logic region to the outside through an output buffer circuit in the peripheral portion. I have. in this way,
Many input buffer circuits and many output buffer circuits are provided in the peripheral portion of the semiconductor chip constituting the gate array. A power supply potential Vcc, for example, 5 V, and a reference potential Vss, for example, (ground potential) OV must be supplied to the transistors constituting the input buffer circuit and the output buffer circuit. V
ss is supplied by a power supply voltage wiring or a reference voltage wiring extending on the input buffer circuit and the output buffer circuit.

[Problems to be solved by the invention]

As a result of studying the power supply wiring and the ground wiring, the present inventors have found the following problems.

The arrangement of the input buffer circuit and the output buffer circuit on the semiconductor chip varies depending on the user's desire. This change can be made by changing the wiring pattern (mask pattern in the wiring forming step) applied to the master wafer. In most cases, there are unused buffer circuits. On the other hand, since the CPU operates in parallel, such as 8 bits or 16 bits, the output buffer circuit of the gate array also changes from “H” level to “L” level to “L” level. There are switches which simultaneously switch from "H" level to "H" level, such as 8 or 16, which are integer multiples of bytes. As described above, when a large number of adjacent output buffer circuits are switched at the same time, the potential of the power supply voltage wiring or the reference voltage wiring connected thereto greatly fluctuates. In particular, in the case of the reference voltage wiring, when the large number of simultaneously switched output buffers are switched from the "H" level to the "L" level, they are accumulated in the load capacities of the multiple simultaneously switched output buffers. The discharged charge is discharged and an excessive current flows, so that the potential of the reference voltage wiring rises. As a result, other buffer circuits are likely to malfunction.

An object of the present invention is to effectively use bonding pads corresponding to unused buffer circuits.

The objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, in the semiconductor integrated circuit device, the first potential supply line for supplying the first potential is connected to the bonding pad corresponding to the unused buffer circuit.

(Operation)

According to the above-described means, it is possible to use the bonding pad which was originally unused, and to supply the first potential via the bonding pad.

(Example of the invention)

The present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device employing a master slice system.

In all of the drawings, components having the same function are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is a plan view schematically showing a semiconductor integrated circuit device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate made of single-crystal silicon, which constitutes a gate array type semiconductor integrated circuit device. Bonding pads around the semiconductor chip 1
2,2A, 2B, 2C are arranged. The bonding pad 2 is for input signals or output signals, the bonding pads 2A and 2B are for reference potentials such as OV, and the bonding pads 2C are for power supply potentials such as 5V. Inside the bonding pads 2, 2A, 2B, and 2C, there are I / O regions in which an input buffer circuit or an output buffer circuit of the semiconductor integrated circuit device is formed. An inner area surrounded by the I / O area is an internal circuit area. For example, as disclosed in Japanese Patent Application No. 146518/1985, for example, a MISFET array in which three P-channel MISFETs are connected in series is provided. Three N
C- composed of a MISFET array in which channel MISFETs are connected in series
The basic cell 4A is composed of MISFETs, and these are repeatedly arranged to form the basic cell row 4. The basic cells 4A and the basic cell columns 4 are connected by aluminum wiring to form various logic gates, clock buffers, and the like. I / O
On the area, there are provided reference voltage wirings 5, 5A for supplying a reference potential, for example, OV to the output buffer circuit in the I / O area, and a power supply wiring 6, for supplying a power supply potential, for example, 5 V to the inside thereof, Further, a reference voltage wiring 7 for supplying a reference potential to the internal circuit and a power supply voltage wiring 8 for supplying a power supply potential extend. The input buffer circuit is supplied with the reference potential and the power supply potential from the reference voltage wiring 7 and the power supply voltage wiring 8. These reference voltage wires 5, 5A, 7, power supply voltage wires 6, 8
Is formed of, for example, a second-layer aluminum film. Further, for example, an auxiliary power supply voltage wiring (not shown) extending in the same direction as the power supply voltage wirings 6 and 8 may be formed of, for example, a third-layer aluminum film.

The reference voltage wiring 5A is provided exclusively for an output buffer circuit that simultaneously switches from “H” level to “L” level and from “L” level to “H” level among many output buffer circuits. The output buffer circuit and the input buffer circuit which are not switched at the same time are not connected. An output buffer circuit other than the output buffer circuit that is switched at the same time is connected to a reference potential wiring 5A different from the reference potential wiring 5A.
Supply the reference potential Vss. In this way, by simultaneously providing the output buffer circuit that switches simultaneously and the reference potential wiring that supplies the reference potential to the other output buffer circuits separately to the reference potential wiring 5A and the reference potential wiring 5, the switching is performed simultaneously. When the output of the output buffer circuit changes from "H" level to "L" level, the rise in the potential of the reference potential wiring 5A caused by the discharge affects the output buffer circuit and the input buffer circuit which do not switch at the same time. Not to give.

Here, FIG. 2 schematically shows output buffer circuits that are simultaneously switched.

In FIG. 2, reference numeral 3A denotes an output buffer circuit which switches at the same time as the output buffer circuit, and supplies a reference potential via a reference potential wiring 5. 3B ₁ ~3B ₈ is an output buffer circuit switching operation is performed at the same time, it is powered by the reference potential wirings 5A to reference potential. 3C, the output buffer circuit 3A, 3B ₁ the output buffer circuit is not ～3B ₈ simultaneously Setsu換Ru, are powered by the reference potential wirings 5 and the reference potential. The power supply potential is the output buffer circuit 3A, 3B ₁
33B ₈ , 3C are all supplied by the same power supply wiring 6. Incidentally, at the same time that the switching operation is performed, not limited to the eight output buffer circuit 3B ₁ ~3B _8,
Two or more, for example, 16, 24, 32, etc., vary depending on the user's request.

Here, 3A may be such that the number of output buffer circuits that are switched at the same time does not affect the potential of the reference potential wiring, that is, about two to three.

The reference voltage wirings 5, 5A and the power supply voltage wiring 6 can be equivalently represented as shown in FIG. FIG.
FIG. 3 is a circuit diagram of an output buffer. Note Fig. 4, for simplification of the drawing shows an output buffer circuit 3A, 3B ₁ ~3B _4, 3C only. Then, these output buffer circuits 3A, 3B ₁ to
FIG. 5 shows a time chart when 3B ₄ and 3C change from “H” level to “L” level.

In Figure 4, L ₁ is the inductance of the power supply voltage line 6, similarly, L ₂ is the reference voltage wiring 5A, L ₃ when viewed reference voltage line 5 from the side of the output buffer circuit 3A of, L ₄ is a wiring reference voltage from the side of the output buffer circuit 3C 5
Are the respective inductances when looking at. C ₀ -C ₅
Is the load capacitance of each output buffer circuit 3A, 3B ₁ ~3B _4, 3C has. Now, the output buffer circuit 3A, the output of the 3B ₁ ~3B ₄ is in the "H" level, the output of the output buffer circuit 3C is referred to as being "L" level. Next, the output buffer circuit 3B ₁
When 3B ₄ switches from “H” level to “L” level at the same time,
Load capacitance C ₁ -C ₄ charges accumulated in is discharged to the reference voltage wiring 5A. At this time, since the reference voltage wiring 5A is an inductance L _2, the potential V _L2 of the reference voltage wiring 5A as in the fifth view is increased. Since the threshold value of the logic level is set to a low value of about 1.4 V, the potential increased by the discharge may exceed the threshold value as described above. However, in the present application, since the reference voltage wiring 5A is separated from the reference voltage wiring 5, the output of the output buffer circuit 3C at the “L” level is inverted due to the rise in the potential of the reference voltage wiring 5A. Nothing. On the other hand, the output when the buffer circuit 3B ₁ ~3B ₄ rises from the "L" level to the "H" level is, the potential of the reference voltage wiring 6 is reduced by the inductance L _1, logic threshold from the power supply potential Vcc example 5V Since the width up to a value of, for example, 1.4 V is large, the decrease in the potential does not fall below its threshold. In the present application therefore, 3B ₁ in the output buffer circuit 3A, 3B ₁ ~3B ₄ (FIG. 2 with the same supply voltage wiring 6
~ 3B ₈ ), 3C and the input buffer circuit are supplied with the power supply voltage Vcc.

The power supply in the case where the width of the up logic threshold is not so large from the potential Vcc, the output simultaneously Setsu換Ru output buffer circuit 3B ₁ ~3B ₄ to the supply voltage source voltage wiring other output to power the Vcc The power supply voltage wiring for supplying power to the buffer circuits 3A and 3C and the input buffer circuit may be independent.

For the reference voltage wiring 5A, a dedicated bonding pad 2A is provided separately from the bonding pad 2B to which the reference voltage wirings 5, 7 are connected. Power supply voltage wiring 6,8
Are connected to the same bonding pad 2C.

When the number of output buffer circuits that are simultaneously switched increases, the potential of the power supply voltage wiring 6 decreases when rising from the “L” level to the “H” level. The circuit portion may be provided separately. The power supply voltage wiring 6, which is provided separately from only the portion of the output buffer circuit in which the switching operation is performed at the same time, is provided separately from the bonding pad 2C, with a dedicated bonding pad 2 for supplying the power supply potential Vcc.
Should be provided.

Next, the reference voltage wirings 5, 5A, 7 and the power supply voltage wirings 6, 8
Will be described.

6 and 7 are diagrams for explaining the wiring design of the reference voltage wirings 5, 5A, 7 and the power supply voltage wirings 6, 8. FIG.

Circuit elements of the basic cell 4AI / O cell, for example, MIS (Meta
l Insulator semiconductor field effect transistors (MISFETs), resistors, and first-layer aluminum wiring are laid out as fixed patterns. The first-layer aluminum wiring includes a wiring for forming an input / output circuit in the I / O cell. In FIG. 6, each of 8X, 7X, 6X, 5X is a reference voltage wire 5, 5A, 7, a power supply voltage wire 6, 8
Is a fixed pattern of, for example, the second layer of aluminum film in designing the pattern of the second pattern. Regardless of what kind of buffer circuit is configured, the DA (Design Automated
ation), layout is performed at a predetermined interval in each I / O area. 7X between this fixed pattern 8X and 8X
7 and 7X, between 6X and 6X, and between 5X and 5X, that is, in FIG. 7 depending on whether or not the connection pattern Y made of the second-layer aluminum film is arranged at the portion indicated by the dotted line. As described above, the reference voltage wirings 5, 5A, 7 and the power supply voltage wirings 6, 8 are designed. According to this method, even if the arrangement of the output buffer circuits to be switched simultaneously on the chip 1 is variously changed, the reference voltage wiring 5A and the separated portions of the reference voltage wiring 5A and the reference voltage wiring 5 are changed. It can be placed anywhere on the semiconductor chip 1. In the design of the reference voltage wirings 5, 5A and 7, and the power supply voltage wirings 6 and 8, the fixed patterns 8X-8X, 7X-7X, 6X-6X, 5X
Whether or not to connect between −5X is determined by the user's request, and based on this information, the connection pattern Y is arranged and laid out by the DA.

In this embodiment, the reference voltage wiring 7 and the power supply voltage wiring are used.
Since there is no need for a disconnection part in 6, 8, the reference voltage wiring 7 and the power supply voltage wiring 6, 8 are not designed with the fixed patterns 6X, 7X, 8X and the connection pattern Y, but the reference voltage wiring 7, power supply The entirety of the voltage wirings 6, 8 may be a fixed pattern.

Next, installation of the bonding pad 2A for supplying the reference voltage to the reference voltage wiring 5A will be described with reference to FIG. Output buffer circuit 3B according to information from user
_{1 to} 3B ₈ are output buffer circuits whose output levels are simultaneously switched, and are connected to a reference voltage wiring 5A separated from the reference voltage wiring 5 to which other output buffer circuits and input buffer circuits are connected. You. A bonding pad corresponding to each output buffer circuit is provided, and is connected to each corresponding output buffer. When connecting the eight output buffers 3B ₁ ～3B ₈ with information from the user to a dedicated reference voltage wiring. 5A, 8 + 1, i.e. the output buffer 3B ₁ ~3B 'dedicated reference voltage wiring 5A The bonding pad corresponding to the output buffer 3B 'is a pad 2A for supplying a reference voltage to the reference voltage wiring 5A. Even if the number of output buffer circuits switched simultaneously changes variously, n + 1 output buffer circuits switched simultaneously are connected to a dedicated reference voltage wiring, and an extra output buffer is practically used. By using the bonding pad corresponding to the circuit as a reference potential power supply pad to the dedicated reference voltage wiring, power can be supplied to the dedicated reference voltage wiring without adding a power supply pad.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

For example, as shown in FIG. 9A, the connection pattern Y for connecting the fixed patterns 6X, 7X, 8X is the third pattern.
It may be formed by a layer of aluminum film. The connection between the connection pattern Y and the fixed patterns 6X, 7X, 8X is indicated by a circle for convenience. Further, the connection pattern Y may be changed to a wire. Further, as shown in FIG. 9 (b), the connection pattern Y is between all the fixed patterns 5X and 5X, 6X
And between 6X, 7X and 7X, between 8X and 8X, and whether or not to provide a connection portion ● between the connection pattern Y and the fixed pattern 5X, 6X, 7X, 8X, 5,5A, 6,7,8 may be designed. Further, in the present embodiment, the case where the present invention is applied to the gate array is described as an example.However, the present invention is not limited to this, and is configured such that macro cells and standard cells such as RAM, ROM, and ALU are mounted on a semiconductor substrate. You may.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

The bonding pads corresponding to the unused buffer circuits can be effectively used.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor chip, FIG. 2 is a circuit diagram schematically showing output buffer circuits that are simultaneously switched, FIG. 3 is a circuit diagram of an output buffer, and FIG. FIG. 5 is a time chart when the output buffer circuit changes from the “H” level to the “L” level, and FIGS. 6 to 8 are the reference voltages. 9A and 9B are diagrams for explaining the wiring design of the wiring for power supply and the wiring for power supply voltage, and FIGS. 9A and 9B are diagrams showing a modification of the wiring design. In the drawing, 1... Semiconductor chip, 2, 2A, 2B, 2C... Bonding pad, I / O... Area where input buffer circuit or output buffer circuit is formed, 4... Basic cell row, 4A. Cell, 5,5A, 7 …… ground wiring, 6,8 …… potential wiring, 3A, 3B ₁
33B ₈ , 3C… output buffer circuit, 5X, 6X, 7X, 8X… fixed pattern, Y… connection pattern.

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-161856 (JP, A) JP-A-62-169464 (JP, A) JP-A-63-202938 (JP, A)

Claims (4)

(57) [Claims] An internal circuit having a transistor; a plurality of buffer circuits for transmitting signals to and from the internal circuit; bonding pads respectively corresponding to the buffer circuits of the plurality of buffer circuits; In a semiconductor integrated circuit device including a first potential supply line for supplying a first potential and a second potential supply line for supplying a second potential to the plurality of buffer circuits on a semiconductor substrate, A bonding pad corresponding to an unused buffer circuit is connected to the first potential supply wiring, and the plurality of buffer circuits are divided into buffer circuit groups that are simultaneously switched, and at least one buffer is provided for each of the buffer circuit groups. The circuit is not used, and the bonding pad corresponding to the unused buffer circuit is connected to the first potential supply wiring. The semiconductor integrated circuit device according to claim. 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is a gate array. 3. The semiconductor integrated circuit device according to claim 1, wherein said first potential is a reference potential, and said second potential is a power supply potential. 4. The method according to claim 1, wherein each of said plurality of buffer circuits is an output buffer circuit.
Item 4. The semiconductor integrated circuit device according to any one of Items 3 to 3.