JP5440066B2 - Semiconductor device and method for evaluating semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor device evaluation method, and more particularly, to a semiconductor device and a semiconductor device evaluation method for evaluating characteristics of an SRAM (Static Random Access Memory) cell and characteristics of individual transistors constituting the SRAM cell. .

  The present SRAM cell includes a flip-flop in which two CMOS inverter circuits each composed of a P-channel MOS transistor (load transistor) and an N-channel MOS transistor (driver transistor) are cross-connected, and both nodes of the flip-flop are connected to a bit line. A six-transistor cell composed of two data transfer transistors (access transistors) connected to a pair is the mainstream. The SRAM cell is characterized in that data can be stably held because data is statically stored by a flip-flop. There is a static noise margin (hereinafter abbreviated as SNM) as an index indicating the cell stability during the read operation of the SRAM cell.

  The SNM characteristic is known as a so-called SRAM cell butterfly curve obtained by superimposing the input / output characteristics of the two inverter circuits constituting the flip-flop when the access transistor is turned on. It is common to define the length of one side of the largest square in contact as the SNM. The larger the SNM, the higher the stability of the data stored in the SRAM cell, and the less the data is destroyed due to power supply voltage noise in the chip. Therefore, taking a large SNM is an important point in designing an SRAM cell.

  On the other hand, with the miniaturization of the semiconductor device manufacturing process, the transistor characteristics vary from chip to chip due to various factors during manufacturing. These variations vary depending on the position of the chip on the wafer surface, the position of the transistor pattern in the chip and the element density (systematic variation), and the variation varies completely depending on the conditions during diffusion. It is roughly divided into variations (random variations). Among these, random variations that occur even between adjacent elements (in-plane distribution, variations that do not have in-chip distribution and do not cause processing dimensions, etc.) are the discreteness of channel implantation impurities for threshold control, The main cause is thought to be fluctuations in gate capacitance.

  For SRAM cells, this random variation is a major problem. This is because, as described above, when the characteristics of the six transistors constituting the cell, for example, the threshold voltage Vth vary randomly, the two inverter characteristics constituting the flip-flop are shifted from each other. As a result, the butterfly curve obtained by superimposing the input / output characteristics of the two inverter circuits becomes asymmetrical, and the SNM of the SRAM cell is determined by the smaller of the inscribed maximum squares.

  In addition, if the variation of the threshold voltage Vth becomes larger than a certain level and varies with a distribution, as a result, there are stochastic cells in which SNM is not ensured, and the capacity of the SRAM, that is, the number of SRAM cells increases. The more you increase the probability. In such a cell, if the word line is in a selected state and the access transistor is turned on, the stored data may be destroyed by that alone, causing a problem that normal operation as a memory cannot be performed.

  Therefore, when developing a fine semiconductor process, a TEG (Test Element Group) reflecting the cell layout is fabricated on a semiconductor wafer to set the process conditions based on the evaluation analysis results in order to evaluate and analyze SRAM characteristics. It is necessary to develop an element that can withstand mass production. Conventionally, as a TEG for evaluating the characteristics of individual transistors constituting such an SRAM cell, for example, there is a TEG disclosed in Patent Document 1 (see FIG. 1 of Patent Document 1).

JP 2003-172766 A

However, in the TEG, one electrode pad corresponds to one internal node of the SRAM cell, and the area per TEG is determined by the size and number of electrode pads. Therefore, only tens to hundreds of SRAM cells having the same layout can be arranged in the semiconductor chip, and a large amount of data cannot be evaluated.
In addition, by arranging a plurality of the TEGs on a chip, it is possible to evaluate SRAM cell characteristics or systematic variation (distribution of characteristics due to processes in a chip) of transistors constituting the SRAM cell. However, since a plurality of SRAM cells having the same layout are arranged adjacent to each other and lead-out lines and electrode pads corresponding to the internal nodes are not provided so that any of the SRAM cells can be measured. Variation (for example, variation due to the discreteness of impurities causing channel implantation, other line edge roughness, local thickness distribution of the gate oxide film, etc.) cannot be statistically evaluated.

  In other words, in the conventional TEG, it is impossible to analyze the memory cell characteristics or the random variation of the transistors constituting the memory cell in a semiconductor device in which a plurality of memory cells are arranged at a very high density in one chip. there were. This means that taking SRAM as an example, it is difficult to secure a non-defective product rate of a megabit order SRAM in a system LSI on which an SRAM cell is actually mounted.

  This is because, when conditions such as Vt of the transistors constituting the SRAM cell are set, the median value (median value M) and variation (standard deviation σ) of the SNM of the megabit memory cell can be obtained statistically. However, if large-scale data cannot be collected, an error occurs in statistical values, particularly σ, which makes production management difficult. Taking the SNM as an example, the median value M is determined so that the value of M−6σ is greater than 0, that is, a cell without an SNM is probabilistically generated and the yield as an SRAM is not lowered. There is a need to. Therefore, in order to set the Vt of the transistor that becomes the median value M, it is necessary to determine the process condition (ion implantation condition). However, when the value of σ cannot be accurately grasped, the setting becomes difficult. In order to avoid this difficulty, it is conceivable to take a large median value of the SNM in advance, but the SRAM characteristic also has a cell current characteristic (Icell characteristic) related to the high-speed operation of the memory. If it is increased, it decreases and hinders high-speed operation. Therefore, the SNM cannot be increased.

  Therefore, in order to ensure the yield in the early stage of process development, it is necessary to determine the median value for production management including random variations. For this purpose, so-called memory cells are arranged in an array. By measuring local variations, it is necessary to accurately collect σ values of SNMs caused by random variations. At that time, when an SRAM cell having an extremely small SNM is found, characteristics (threshold voltage Vt, drain current Ion) of individual transistors constituting the SRAM cell are evaluated in detail, and the cause is determined based on the evaluation result. There is also a need to provide feedback on process development.

In addition, the cell current characteristic (Icell characteristic), which is the decisive factor for high-speed operation, is also considered to vary with σ around the median value due to random variations, similar to SNM. Therefore, if the Icell lower limit is calculated based on the planned SRAM mounting capacity and the bit line amplification start time (sense amplifier activation time) is not determined under the speed worst condition, it will malfunction as an SRAM product. Become. Therefore, in order to increase the yield of the mounted SRAM, it is necessary to consider the random variation of Icell and feed back to the product design.
Therefore, in the conventional TEG, the variation data of the SRAM characteristics due to random variations, that is, the SNM characteristics and the Icell characteristics could not be measured. Therefore, it is appropriate for process development and product development based on the evaluation result of the SRAM cell. There was a problem that feedback could not be applied.

  In recent years, especially in a P-channel type MOS transistor, characteristic deterioration due to stress fluctuation, a so-called NBTI (Negative Bias Temperature Instability) problem has become prominent, and evaluation for clarifying this has become active. Even in the SRAM cell, if the memory cell is not accessed under actual use conditions after being mounted on a product, the load transistor can sufficiently deteriorate due to NBTI.

  For this reason, it is necessary to grasp the amount of deterioration of the load transistor due to NBTI at the initial stage of SRAM cell development and feed it back to the SRAM cell design. Specifically, the switching point of the output voltage with respect to the input voltage in the butterfly curve showing the SNM characteristic moves to the lower side of the input voltage when the load transistor performance deteriorates. The length of one side becomes shorter (SNM deteriorates).

Therefore, in the early stage of SRAM cell development, it is necessary to determine the size (L / W) of the load transistor that can withstand the service life, or to determine the setting conditions such as Vt at the time of manufacture. Therefore, in order to increase the accuracy when determining the conditions of the load transistor, it is necessary to collect reliability data regarding NBTI on a large scale.
However, in the conventional TEG, since NBTI stress can be applied to only one SRAM cell, it is necessary to produce a large number of semiconductor chips or wafers in order to accumulate large-scale reliability data. For this reason, there are problems that the evaluation cost increases and the time required for wafer evaluation also increases.

In order to solve the above problem, the present invention provides a semiconductor device for evaluating characteristics of an SRAM cell as a first solving means relating to a semiconductor device,
A plurality of evaluation cells having SRAM cells;
A selection line for supplying a selection signal for selecting the evaluation cell;
A main power supply line for supplying a power supply voltage of the SRAM cell;
A main gate power supply line for supplying an input voltage to the gates of the first data transfer transistor and the second data transfer transistor of the SRAM cell;
A first main input / output line for supplying an input voltage to the first latch node of the SRAM cell or detecting an output voltage thereof;
A second main input / output line for supplying an input voltage to the second latch node of the SRAM cell or detecting an output voltage thereof;
A first bit main power line for supplying a first bit line voltage to the first latch node via the first data transfer transistor of the SRAM cell;
A second bit main power supply line for supplying a second bit line voltage to the second latch node via the second data transfer transistor of the SRAM cell;
According to the selection signal, each of the evaluation cells includes its own SRAM cell, the main power supply line, the main gate power supply line, the first main input / output line, the second main input / output line, and the first main input line. The bit main power supply line and the second bit main power supply line are connected or disconnected.

Further, as a second solving means relating to the semiconductor device, in the first solving means,
The plurality of evaluation cells are arranged in a matrix of m rows and n columns (m and n are positive integers),
The selection signal supply selection line is provided for each row, and is provided for each column and a row selection signal for supplying a row selection signal for selecting the evaluation cell belonging to each row, and belongs to each column. A column selection line for supplying a column selection signal for selecting the evaluation cell;
Each of the evaluation cells includes its own SRAM cell, the main power supply line, the main gate power supply line, the first main input / output line, and the second response line in response to the row selection signal and the column selection signal. The main input / output line, the first bit main power supply line, and the second bit main power supply line are connected or disconnected.

Further, as a third solving means relating to the semiconductor device, in the second solving means,
A sub power supply line provided for each row or each column, for supplying the power supply voltage of the SRAM cell of the evaluation cell belonging to each said row or each column;
Connection / non-connection between the sub power supply line and the main power supply line according to a row selection signal belonging to the same row as the sub power supply line or a column selection signal belonging to the column. A power line switching circuit for switching between,
To supply a power supply voltage for supplying an input voltage to the gate of the first data transfer transistor and the second data transfer transistor of the SRAM cell of the evaluation cell belonging to each row or each column provided for each row or each column Sub-gate power supply line,
In response to a row selection signal belonging to the same row as the sub-gate power supply line or a column selection signal belonging to the column, the sub-gate power supply line and the main gate power supply line A gate power line switching circuit for switching connection / disconnection;
A first sub input / output line provided for each row or column and supplying an input voltage to the first latch node of the SRAM cell of the evaluation cell belonging to each row or column or detecting the output voltage; ,
The first sub input / output line is provided corresponding to the first sub input / output line, and the first sub input / output line corresponds to a row selection signal belonging to the same row as the first sub input / output line or a column selection signal belonging to the column. A first input / output line switching circuit for switching connection / disconnection between a line and the first main input / output line;
A second sub-input / output line that is provided for each row or each column and supplies an input voltage to the second latch node of the SRAM cell of the evaluation cell belonging to each row or each column or detects its output voltage; ,
The second sub input / output line is provided corresponding to the second sub input / output line, and the second sub input / output line corresponds to a row selection signal belonging to the same row as the second sub input / output line or a column selection signal belonging to the column. A second input / output line switching circuit for switching connection / disconnection between the line and the second main input / output line;
A first bit line voltage is supplied to the first latch node via the first data transfer transistor of the SRAM cell of the evaluation cell that is provided for each row or each column and belongs to each row or each column. A first bit sub-power supply line;
In response to a row selection signal belonging to the same row as the first bit sub-power supply line or a column selection signal belonging to a column, the first bit sub-power supply line and the first bit sub-power supply line A first bit power supply line switching circuit for switching connection / disconnection with the first bit main power supply line;
A second bit line voltage is supplied to the second latch node via the second data transfer transistor of the SRAM cell of the evaluation cell that is provided for each row or each column and belongs to each row or each column. A second bit sub-power supply line;
In response to a row selection signal belonging to the same row as the second bit sub-power supply line or a column selection signal belonging to a column, the second bit sub-power supply line and the second bit sub-power supply line And a second bit power supply line switching circuit for switching connection / disconnection with the second bit main power supply line.

Further, as a fourth solving means relating to the semiconductor device, in the third solving means,
Each of the evaluation cells is
One input terminal is connected to the row selection line belonging to its own row, and the other input terminal is connected to the column selection line belonging to its own column and supplied to the connected row selection line. A selection circuit that outputs a selection signal indicating selection / non-selection of its own SRAM cell in accordance with a row selection signal and a column selection signal supplied to a column selection line;
A first switch for switching connection / disconnection between the second sub input / output line belonging to the same row or column as the self and the second latch node of the self SRAM cell according to the selection signal;
A second switch for switching connection / disconnection between the first sub input / output line belonging to the same row or column as the self and the first latch node of the self SRAM cell according to the selection signal;
A third switch for switching connection / disconnection between the sub power supply line belonging to the same row or column as the self and a power supply terminal of the self SRAM cell according to the selection signal;
A fourth switch for switching connection / disconnection between the second bit sub-power supply line belonging to the same row or column as the self and the second bit line of the self SRAM cell according to the selection signal;
A fifth switch for switching connection / disconnection between the first bit sub-power supply line belonging to the same row or column as the self and the first bit line of the self SRAM cell according to the selection signal;
And a sixth switch for switching connection / disconnection between the sub-gate power supply line belonging to the same row or column as the self and the data transfer transistor of the own SRAM cell according to the selection signal. And

Further, as a fifth solving means relating to the semiconductor device, in the fourth solving means,
In each of the plurality of evaluation cells,
A total resistance comprising a wiring resistance of the first main input / output line, a switch resistance of the first input / output line switching circuit, a wiring resistance of the first sub input / output line, and a switch resistance of the second switch;
A total resistance composed of a wiring resistance of the second main input / output line, a switch resistance of the second input / output line switching circuit, a wiring resistance of the second sub input / output line, and a switch resistance of the first switch;
And the wiring resistance of the cell ground wiring for supplying the ground voltage to the SRAM cell, respectively,
Wiring resistance of the main power supply line, switch resistance of the power supply line switching circuit, wiring resistance of the sub power supply line, and total resistance consisting of switch resistance of the third switch,
A total resistance comprising a wiring resistance of the first bit main power supply line, a switch resistance of the first bit power supply line switching circuit, a wiring resistance of the first bit sub power supply line, and a switch resistance of the fifth switch;
A total resistance comprising a wiring resistance of the second bit main power supply line, a switch resistance of the second bit power supply line switching circuit, a wiring resistance of the second bit sub power supply line, and a switch resistance of the fourth switch;
The wiring resistance of the main gate line, the switch resistance of the gate power supply line switching circuit, the wiring resistance of the sub-gate power supply line, and the total resistance composed of the switch resistance of the sixth switch are set to be smaller than any of the above. Features.

Further, as sixth solving means relating to the semiconductor device, in the second to fifth solving means,
A selection signal supply circuit for supplying a column selection signal to each column selection line and supplying a row selection signal to each row selection line;
The selection signal supply circuit has a selection control signal, a clock signal, a column address signal, a row address signal, and two test signals as inputs,
Depending on the state of the two test signals, the mode shifts to a normal evaluation mode, a first test mode, or a second test mode,
In the normal evaluation mode, a first address mode that generates the column selection signal and the row selection signal based on the column address signal and the row address signal according to the state of the selection control signal, and the clock signal Performing a count operation in synchronization, and switching between the second address mode for generating the column selection signal and the row selection signal based on the count result;
In the first test mode, the column selection signal and the row selection signal for selecting all the evaluation cells are generated, and in the second test mode, the column for deselecting all the evaluation cells. A selection signal and the row selection signal are generated.

On the other hand, the present invention provides a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell as a first solving means relating to a semiconductor device evaluation method, wherein any one of the first to fifth solving means is provided. Use a semiconductor device that has
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated;
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power supply line, opening the second bit main power supply line, and supplying a first variable input voltage to the second main input / output line; A third step of detecting a change in the first output voltage of the first main input / output line and acquiring the first input / output characteristic;
The bit line voltage is supplied to the second bit main power supply line, the first bit main power supply line is opened, and a second variable input voltage is supplied to the first main input / output line. A fourth step of detecting a change in the second output voltage of the two main input / output lines and obtaining a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the static noise margin of the SRAM cell included in the evaluation cell.

Further, as a second solving means related to the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell, wherein the semiconductor device having any one of the first to fifth solving means is provided. use,
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated;
A second step of supplying a ground voltage to the first main input / output line and the second main input / output line to open the main power supply line;
Either one of the first bit main power supply line and the second bit main power supply line is in an open state, a desired voltage is supplied to the other, a variable gate voltage is supplied to the main gate power supply line, and the first And a third step of evaluating characteristics of the first data transfer transistor or the second data transfer transistor by measuring a current flowing through the other of the bit main power supply line and the second bit main power supply line. It is characterized by that.

Further, as a third solving means related to the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell, wherein the semiconductor device having any one of the first to fifth solving means is provided. use,
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated;
A second step of supplying a desired voltage to the main power supply line and a ground voltage to the main gate power supply line to open the first bit main power supply line and the second bit main power supply line;
A desired voltage is supplied to one of the first main input / output line and the second main input / output line, and a variable voltage is supplied to the other, and the first main input / output line and the second main input / output line are supplied. And a third step of evaluating the characteristics of the driver transistor by measuring a current flowing through one of the main input / output lines.

According to a fourth aspect of the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating characteristics of an SRAM cell having a load transistor, wherein any one of the first to fifth solutions is provided. Use a semiconductor device that has
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated;
A second step of supplying a desired voltage to the main power supply line and a ground voltage to the main gate power supply line to open the first bit main power supply line and the second bit main power supply line;
A desired voltage is supplied to one of the first main input / output line and the second main input / output line, and a variable voltage is supplied to the other, and the first main input / output line and the second main input / output line are supplied. And a third step of evaluating characteristics of the load transistor by measuring a current flowing through one of the main input / output lines.

Further, as a fifth solving means related to the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell, wherein the semiconductor device having the sixth solving means is used, and the normal When performing the characteristic evaluation using the first address mode of the evaluation mode,
The state of the two test signals input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit corresponds to the first address mode A first step of inputting a column address signal and a row address signal representing the position of the evaluation cell to be evaluated to the selection signal supply circuit;
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power supply line, opening the second bit main power supply line, and supplying a first variable input voltage to the second main input / output line; A third step of detecting a change in the first output voltage of the first main input / output line and acquiring the first input / output characteristic;
The bit line voltage is supplied to the second bit main power supply line, the first bit main power supply line is opened, and a second variable input voltage is supplied to the first main input / output line. A fourth step of detecting a change in the second output voltage of the two main input / output lines and obtaining a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the static noise margin of the SRAM cell included in the evaluation cell.

Further, as a sixth solving means relating to the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell, wherein the semiconductor device having the sixth solving means is used, and the normal When performing characteristic evaluation using the second address mode of the evaluation mode,
The state of the two test signals input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit corresponds to the second address mode A first step set to
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power supply line, opening the second bit main power supply line, and supplying a first variable input voltage to the second main input / output line; A third step of detecting a change in the first output voltage of the first main input / output line and acquiring the first input / output characteristic;
The bit line voltage is supplied to the second bit main power supply line, the first bit main power supply line is opened, and a second variable input voltage is supplied to the first main input / output line. A fourth step of detecting a change in the second output voltage of the two main input / output lines and obtaining a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the static noise margin of the SRAM cell included in the evaluation cell.

Further, as a seventh solving means relating to the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell, wherein the semiconductor device having the sixth solving means is used, When characterization is performed using the test mode 1
A first step of setting a state of two test signals input to the selection signal supply circuit to a state corresponding to a first test mode;
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power supply line, opening the second bit main power supply line, and supplying a first variable input voltage to the second main input / output line; A third step of detecting a change in the first output voltage of the first main input / output line and acquiring the first input / output characteristic;
The bit line voltage is supplied to the second bit main power supply line, the first bit main power supply line is opened, and a second variable input voltage is supplied to the first main input / output line. A fourth step of detecting a change in the second output voltage of the two main input / output lines and obtaining a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the static noise margin of the entire SRAM cell included in all evaluation cells.

Further, as an eighth means for solving the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell having a load transistor, wherein the semiconductor device having the sixth solution means is used. When performing the characteristic evaluation using the first test mode,
A first step of setting a state of two test signals input to the selection signal supply circuit to a state corresponding to a first test mode;
SRAM cell power supply voltage to the main power supply line, the power supply voltage to the main gate power supply line, the power supply voltage to one of the first bit main power supply line and the second bit main power supply line, A second step of supplying a ground voltage to the other side, opening the first main input / output line and the second main input / output line, and performing a stress test on the load transistors of the SRAM cells included in all the evaluation cells; It is characterized by having.

Further, as a ninth solving means relating to the semiconductor device evaluation method, there is provided a semiconductor device evaluation method for evaluating the characteristics of an SRAM cell, wherein the semiconductor device having the sixth solving means is used, When characterization is performed using the test mode 1
A first step of setting a state of two test signals input to the selection signal supply circuit to a state corresponding to a first test mode;
SRAM cell power supply voltage to the main power supply line, the power supply voltage to the main gate power supply line, the power supply voltage to one of the first bit main power supply line and the second bit main power supply line, A second step of supplying a ground voltage to the other to open the first main input / output line and the second main input / output line;
Supplying the power supply voltage to the other of the first bit main power supply line and the second bit main power supply line, then supplying a ground voltage to the main gate power supply line, and measuring a current flowing through the main power supply line; And a third step of measuring the leakage current of the SRAM cells included in all the evaluation cells.

  According to the present invention, a switch for applying a voltage to each node of an SRAM cell of evaluation cells arranged in a matrix of m rows and n columns is provided, and a row selection signal and a column selection signal are input to open and close the switch. The selection circuit is used. This makes it possible to selectively evaluate the SRAM cell of one evaluation cell among the m × n evaluation cells. Therefore, according to the present invention, variation data of SRAM characteristics due to random variation and variation data of each transistor constituting the SRAM cell can be measured. Therefore, statistical processing is performed based on the measurement result, and the process condition (ion implantation condition) is achieved. Therefore, appropriate feedback can be applied and the SRAM yield can be improved. In addition, since detailed evaluation of individual transistors can also be performed, the cause of variations in transistors with large variations is due to random variations, or due to defects in the manufacturing process, for example, characteristic deviation due to dust during ion implantation, etc. It is also possible to determine whether it is caused or not. In the latter case, it is possible to take measures against the manufacturing process. In addition, the lower limit of the cell current that becomes the decisive factor for high-speed operation can be obtained, the sense amplifier start time in the product design in which the SRAM is mounted can be accurately determined, and the yield of the mounted SRAM can be improved. In addition, a reliability evaluation test can be performed on a large-scale SRAM cell without an increase in evaluation cost.

It is a circuit block diagram of the semiconductor device which concerns on one Embodiment of this invention. It is a circuit block diagram of the evaluation cell in FIG. It is a figure which shows the characteristic of the SRAM cell used for description of FIG. It is a figure which shows the bias conditions at the time of measuring the evaluation cell shown in FIG. It is a figure which shows the parasitic resistance of the evaluation cell shown in FIG. It is a figure which shows the value of the parasitic resistance shown in FIG. 1 is an overall circuit configuration diagram of a semiconductor device according to an embodiment of the present invention. It is a circuit block diagram of the cell test circuit 20 in FIG. It is a truth table regarding the circuit operation of the cell test circuit 20 in FIG. It is a figure which shows the bias conditions at the time of evaluating using the semiconductor device which concerns on one Embodiment of this invention.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit configuration diagram of the semiconductor device according to the present embodiment. As shown in FIG. 1, the semiconductor device according to the present embodiment includes m × n evaluation cells C11 to Cnm arranged in a matrix of m rows and n columns (m and n are positive integers). 2 is a DMA (Device Matrix Array) -TEG for evaluating the characteristics of the SRAM cell provided in FIG. For convenience of explanation, in FIG. 1, the vertical direction is described as the row direction (X direction), and the horizontal direction is described as the column direction (Y direction). In one evaluation cell, for example, an SRAM cell MC manufactured by a fine process of 45 nm is provided. The connection relationship and internal circuit configuration of the evaluation cells C11 to Cnm will be described later.

  The semiconductor device according to the present embodiment has a normal evaluation mode and first and second test modes as its operation mode. In the normal evaluation mode, any evaluation cell can be selected from the above-mentioned m × n evaluation cells by two access methods, and the SRAM cell in the evaluation cell can be measured and evaluated. In the all-evaluation cell selection mode (first test mode), voltages are collectively supplied to the latch nodes of the SRAM cells of all the evaluation cells, and the SNMs of m × n SRAM cells are simultaneously measured and evaluated. it can. Furthermore, in the all evaluation cell non-selection mode (second test mode) test mode, a leak current generated in the semiconductor device can be measured.

In FIG. 1, a first main input / output line V0 (first main input / output line) is an input / output line that supplies an input voltage to the first latch node of the SRAM cell or detects its output voltage. And one end of which is connected to a first main input / output terminal V0P for connection to an external power supply device (not shown).
The second main input / output line V1 (second main input / output line) is an input / output line that supplies an input voltage to the second latch node of the SRAM cell or detects its output voltage. Is connected to a second main input / output terminal V1P for connection to an external power supply device.
The main power supply line VDD (main power supply line) is a power supply line for supplying the power supply voltage of the SRAM cell, and one end thereof is connected to a main power supply terminal VDDP for connection to an external power supply device.

Each of first sub input / output lines V01 to V0m (first sub input / output lines) is provided for each row, and supplies an input voltage to the first latch node of the SRAM cell of the evaluation cell belonging to each row. Or an input / output line for detecting the output voltage. Specifically, the first sub input / output line V01 is connected to the evaluation cells C11 to Cn1 belonging to the first row, and the first sub input / output line V0m is connected to the evaluation cells C1m to Vm belonging to the mth row. Connected to Cnm.
Each of the sub power supply lines VDD1 to VDDm (sub power supply line) is provided for each row, and is a power supply line for supplying a power supply voltage to the SRAM cell of the evaluation cell belonging to each row. Specifically, the sub power supply line VDD1 is connected to the evaluation cells C11 to Cn1 belonging to the first row, and the sub power supply line VDDm is connected to the evaluation cells C1m to Cnm belonging to the mth row.
Each of the second sub input / output lines V11 to V1m (second sub input / output lines) is provided for each row, and supplies an input voltage to the second latch node of the SRAM cell of the evaluation cell belonging to each row. Or an input / output line for detecting the output voltage. Specifically, the second sub input / output line V11 is connected to the evaluation cells C11 to Cn1 belonging to the first row, and the second sub input / output line V1m is connected to the evaluation cells C1m to C1m belonging to the mth row. Connected to Cnm.

The main gate power supply line WL (main gate power supply line) is a power supply line for supplying an input voltage to the gates of the first data transfer transistor and the second data transfer transistor of the SRAM cell, and one end thereof measures an external voltage. Is connected to a main gate power supply terminal WLP for connection to the device.
The first bit main power supply line BLT (first bit main power supply line) is a first bit main power supply that supplies the first bit line voltage to the first latch node via the first data transfer transistor of the SRAM cell. One end of the power supply line is connected to a first bit main power supply terminal BLTP for connection to an external voltage measuring device.
The second bit main power supply line BLC (second bit main power supply line) is a second bit main power supply for supplying a second bit line voltage to the second latch node via the second data transfer transistor of the SRAM cell. One end of the power supply line is connected to a second bit main power supply terminal BLCP for connection to an external voltage measuring device.

Each of the sub-gate power supply lines WL1 to WLn (sub-gate power supply lines) is provided for each column, and the gates of the first data transfer transistor and the second data transfer transistor of the SRAM cell included in the evaluation cell belonging to each column. And a power supply line for supplying an input voltage. Specifically, the sub-gate power supply line WL1 is connected to the evaluation cells C11 to C1m belonging to the first column, and the sub-gate power supply line WLn is connected to the evaluation cells Cn1 to Cnm belonging to the n-th column. .
Each of the first bit sub-power supply lines BLT1 to BLTn (first bit sub-power supply lines) is provided for each column, and the first bit sub-power supply lines BLT1 to BLTn are connected to the first data transfer transistor of the SRAM cell included in the evaluation cell belonging to each column. A first bit sub-power supply line for supplying a first bit line voltage to one latch node. Specifically, the first bit sub-power supply line BLT1 is connected to the evaluation cells C11 to C1m belonging to the first column, and the first bit sub-power supply line BLTn is connected to the evaluation cells Cn1 to Cnm belonging to the nth column. It is connected.
Each of the second bit sub-power supply lines BLC1 to BLCn (second bit sub-power supply lines) is provided for each column, and the second bit sub-power supply lines BLC1 to BLCn are provided via the second data transfer transistor of the SRAM cell included in the evaluation cell belonging to each column. This is a second bit sub-power supply line that supplies a second bit line voltage to two latch nodes. Specifically, the second bit sub-power supply line BLC1 is connected to the evaluation cells C11 to C1m belonging to the first column, and the second bit sub-power supply line BLCn is connected to the evaluation cells Cn1 to Cnm belonging to the nth column. It is connected.

  Each of the row selection lines X1 to Xm is provided for each row and is a selection line for selecting an evaluation cell belonging to each row. One end of each row selection line X1 to Xm is connected to an X select main decoder MDX (corresponding to the X select main decoder MDX in FIG. 7). X select signals (row selection signals) XS1 to XSm output from the X select main decoder MDX are input to the evaluation cells belonging to the respective rows via the respective row selection lines X1 to Xm. Specifically, for example, the row selection line X1 of the first row is connected to the evaluation cells C11 to Cn1 belonging to the first row, and the X selection signal XS1 output from the X selection main decoder MDX is the row selection line X1. To the evaluation cells C11 to Cn1. Similarly, for example, the row selection line Xm of the m-th row is connected to the evaluation cells C1m to Cnm belonging to the m-th row, and the X selection signal XSm output from the main decoder MDX for X selection passes through the row selection line Xm. To the evaluation cells C1m to Cnm.

  Each of the column selection lines Y1 to Yn is a selection line that is provided for each column and for selecting an evaluation cell belonging to each column. One end of each column selection line Y1 to Yn is connected to a Y select main decoder MDY (corresponding to the Y select main decoder MDY in FIG. 7). Y select signals (column selection signals) YS1 to YSn output from the Y select main decoder MDY are input to the evaluation cells belonging to the respective columns via the respective column selection lines Y1 to Yn. Specifically, for example, the column selection line Y1 in the first column is connected to the evaluation cells C11 to C1m belonging to the first column, and the Y selection signal YS1 output from the Y selection main decoder MDY is the column selection line Y1. To the evaluation cells C11 to C1m. Similarly, for example, the column selection line Yn of the nth column is connected to the evaluation cells Cn1 to Cnm belonging to the nth column, and the Y select signal YSn output from the Y select main decoder MDY is passed through the column selection line Yn. To the evaluation cells Cn1 to Cnm.

Each of the power supply line switching circuits PSW1 to PSWm is provided for each row, and in response to an X select signal supplied to a row selection line belonging to each row, first sub input / output lines V01 to V0m ( The first sub input / output line) and the first main input / output line V0 (first main input / output line) are connected or disconnected, and the second sub input / output lines V11 to V1m (second) belonging to the row are connected. And the second main input / output line V1 (second main input / output line) are connected or disconnected, and the sub power lines VDD1 to VDDm (sub power lines) belonging to the row and the main power source are connected. This circuit connects or disconnects the line VDD (main power supply line).
Each of the power supply line switching circuits PSW1 to PSWm is composed of three N-channel MOS transistors. Specifically, for example, the power supply line switching circuit PSW1 belonging to the first row includes a transistor V0T1 (first input / output line switching circuit), a transistor VDDT1 (power supply line switching circuit), and a transistor V1T1 (second input / output line). Switching circuit).

  The drain terminal of the transistor V0T1 is connected to the first main input / output line V0, the source terminal is connected to the first sub input / output line V01 belonging to the first row, and the gate terminal is connected to the row selection line X1 belonging to the first row. Connected with. The drain terminal of the transistor VDDT1 is connected to the main power supply line VDD, the source terminal is connected to the sub power supply line VDD1 belonging to the first row, and the gate terminal is connected to the row selection line X1 belonging to the first row. The drain terminal of the transistor V1T1 is connected to the second main input / output line V1, the source terminal is connected to the second sub input / output line V11 belonging to the first row, and the gate terminal is connected to the row selection line X1 belonging to the first row. Connected with.

  Similarly, the power supply line switching circuit PSWm belonging to the m-th row includes a transistor V0Tm, a transistor VDDTm, and a transistor V1Tm. The drain terminal of the transistor V0Tm is connected to the first main input / output line V0, the source terminal is connected to the first sub input / output line V0m belonging to the m-th row, and the gate terminal is connected to the row selection line Xm belonging to the m-th row. Connected with. The drain terminal of the transistor VDDTm is connected to the main power supply line VDD, the source terminal is connected to the sub power supply line VDDm belonging to the mth row, and the gate terminal is connected to the row selection line Xm belonging to the mth row. The drain terminal of the transistor V1Tm is connected to the second main input / output line V1, the source terminal is connected to the second sub input / output line V1m belonging to the m-th row, and the gate terminal is connected to the row selection line Xm belonging to the m-th row. Connected with.

Each of power supply line switching circuits SSW1 to SSWn is provided for each column, and in response to a Y select signal supplied to a column selection line belonging to each column, subgate power supply lines WL1 to WLn (subgates belonging to that column) Power line) and main gate power line WL (main gate power line) are connected or disconnected, and first bit sub power lines BLT1 to BLTn (first bit sub power lines) and first bit main power lines belonging to the column are connected. BLT (first bit main power supply line) is connected or disconnected, and second bit sub power supply lines BLC1 to BLCn (second bit sub power supply line) and second bit main power supply line BLC (second bit) belonging to the column are connected. This circuit connects or disconnects the main power line.
Each power supply line switching circuit SSW1 to SSWn is composed of three N-channel MOS transistors. Specifically, for example, the power line switching circuit SSW1 belonging to the first column includes a transistor BLTT1 (first bit power line switching circuit), a transistor BLCT1 (second bit power line switching circuit), and a transistor WLT1 (gate power line switching). Circuit).

  The drain terminal of the transistor BLTT1 is connected to the first bit main power supply line BLT, the source terminal is connected to the first bit sub power supply line BLT1 belonging to the first column, and the gate terminal is connected to the column selection line Y1 belonging to the first column. Has been. The drain terminal of the transistor BLCT1 is connected to the second bit main power supply line BLC, the source terminal is connected to the second bit sub power supply line BLC1 belonging to the first column, and the gate terminal is connected to the column selection line Y1 belonging to the first column. Has been. The drain terminal of the transistor WLT1 is connected to the main gate power supply line WL, the source terminal is connected to the sub-gate power supply line WL1 belonging to the first column, and the gate terminal is connected to the column selection line Y1 belonging to the first column.

  Similarly, the power supply line switching circuit SSWn belonging to the nth column includes a transistor BLTTn, a transistor BLCTn, and a transistor WLTn. The drain terminal of the transistor BLTTn is connected to the first bit main power supply line BLT, the source terminal is connected to the first bit sub power supply line BLTn belonging to the nth column, and the gate terminal is connected to the column selection line Yn belonging to the nth column. Has been. The drain terminal of the transistor BLCTn is connected to the second bit main power supply line BLC, the source terminal is connected to the second bit sub power supply line BLCn belonging to the nth column, and the gate terminal is connected to the column selection line Yn belonging to the nth column. Has been. The drain terminal of the transistor WLTn is connected to the main gate power supply line WL, the source terminal is connected to the sub-gate power supply line WLn belonging to the nth column, and the gate terminal is connected to the column selection line Yn belonging to the nth column.

Next, a detailed internal circuit configuration of the evaluation cells C11 to Cnm will be described. Since the internal circuit configuration of each of the evaluation cells C11 to Cnm is common, the following description will be given with reference to FIG. 2 in which only the circuit portion related to the evaluation cell C11 is extracted from FIG.
In FIG. 2, the power supply line switching circuit PSW1 and the power supply line switching circuit SSW1 are omitted, the drain terminal of the first transistor T1 is directly connected to the second main input / output line V1, and the drain of the second transistor T2 is connected. The terminal is directly connected to the first main input / output line V0, the drain terminal of the third transistor T3 is directly connected to the main power supply line VDD, and the drain terminal of the fourth transistor T4 is connected to the second bit main power supply line BLC. Are connected directly, the drain terminal of the fifth transistor T5 and the first bit main power supply line BLT are directly connected, and the drain terminal of the sixth transistor T6 and the main gate power supply line WL are directly connected.
As shown in FIG. 2, the evaluation cell C11 includes an SRAM cell MC, a selection circuit 10, and a first transistor T1 to a sixth transistor T6.
Here, the first transistor T1 to the sixth transistor T6 are 3V type N-channel MOS transistors having stable characteristics, and the selection circuit 10 is also composed of 3V type MOS transistors manufactured by the same process. Yes.

  The SRAM cell MC is connected to the complementary bit lines BT and BC via first and second N-channel MOS transistors Ta1 and Ta2 (data transfer transistors, hereinafter referred to as access transistor Ta1 and access transistor Ta2). And first and second CMOS inverter circuits which are cross-coupled to each other. The SRAM cell MC is a six-transistor type SRAM cell manufactured by a fine process of 45 nm, for example. The first CMOS inverter circuit (hereinafter referred to as inverter circuit I1) includes an N-channel MOS transistor N1 (hereinafter referred to as driver transistor N1) and a P-channel MOS transistor P1 (hereinafter referred to as load transistor P1). ing. The second CMOS inverter (hereinafter referred to as inverter circuit I2) is composed of an N-channel MOS transistor N2 (hereinafter referred to as driver transistor N2) and a P-channel MOS transistor P2 (hereinafter referred to as load transistor P2). Has been. Here, the access transistors Ta1 and Ta2, the driver transistors N1 and N2, and the load transistors P1 and P2 have the same gate length (L), the same gate width (W), and the same threshold voltage (Vth), respectively. Designed to have.

  When the SRAM cell MC is mounted on a product, in the read operation, the gate voltage of the access transistors Ta1 and Ta2 is set to the H level, and one of the bit lines BT and BC is driven to the L level by the cell current Icell. As a result, in the product, a differential voltage is generated between the bit lines, which is amplified by the sense amplifier, and the data is read to the outside. For example, when the memory cell holds data “1”, the voltage of the latch node LN2 that is the output of the inverter circuit I2 is L level (VSSC voltage level), and the latch node LN1 that is the output of the inverter circuit I1. Is at the H level (voltage level of the main power supply line VDD). In this case, the SRAM cell MC causes the cell current Icell to flow through the series circuit including the access transistor Ta2 and the driver transistor N2, and discharges the bit line BC to the L level.

  When the SRAM cell MC is mounted on a product, the gate voltage of the access transistors Ta1 and Ta2 is similarly set to the H level in the write operation, and one of the bit lines BT and BC is set to the H level and the other is set to the L level. By biasing, data is written. For example, when rewriting data from “1” to “0”, the bit line BT is set to L level, the bit line BC is set to H level, the flip-flop circuit composed of the inverter circuits I1 and I2 is inverted, and the output of the inverter circuit I2 The voltage of the latch node LN2 is set to H level, and the voltage level of the latch node LN1 that is the output of the inverter circuit I1 is set to L level.

  FIG. 3 is a diagram of a bistable characteristic (butterfly curve) showing data storage stability in the SRAM cell MC configured as described above. This is because, as shown in FIG. 2, the transfer curves of the inverter circuit I1 are plotted with the voltages of the latch nodes LN1 and LN2 of the SRAM cell MC being V0 and V1, respectively, with the horizontal axis V1 and the vertical axis V0. (V1-V0 static characteristics) and the transfer curve of the inverter circuit I2 plotted with V0 on the horizontal axis and V1 on the vertical axis are superimposed. Here, the gates of the access transistors Ta1 and Ta2 and the bit lines BT and BC are biased to the power supply voltage to reflect the actual operation in the product. In FIG. 3, the state in which the SRAM cell holds data “1”, that is, the state in which the voltage (V0) of the latch node LN1 is at the H level and the voltage (V1) at the latch node LN2 is at the L level. The state holding the data “0” corresponding to the intersection XA of the curve corresponds to the intersection XB.

  In addition, the length of one side of the maximum square inscribed in two regions surrounded by two transfer curves is defined as a static noise margin (SNM). In general, the larger the static noise margin, the higher the stability of the data stored in the SRAM cell, and the less the data is destroyed due to power supply voltage noise in the chip. Therefore, taking a large static noise margin is an important point in designing an SRAM cell.

  Further, the X coordinate of the point A at which the transfer curve starts to drop from the power supply voltage is affected by the threshold voltage Vthn of the driver transistor N1 and the threshold voltage Vthp of the load transistor P1. As the threshold voltage Vthn is higher and the absolute value of the threshold voltage Vthp is lower, the point A moves to the right in the figure and the SNM increases. However, if the threshold voltage Vthn of the driver transistor N1 is set high, the cell current Icell decreases and the operation speed decreases. Further, if the absolute value of the threshold voltage Vthp of the load transistor P1 is lowered, the current during standby (standby) of the SRAM cell MC increases. If the threshold voltage Vthn is high and the absolute value of the threshold voltage Vthp is low, the flip-flop composed of the inverter circuits I1 and I2 becomes difficult to invert, which means that it becomes difficult to invert the flip-flop in the write operation. However, the writing operation is difficult.

  Further, the Y coordinate of the point B after the transfer curve falls to the L level is determined by the ratio of the driving capabilities of the driver transistor N1 and the access transistor Ta1. That is, by increasing the driving capability of the driver transistor N1 with respect to the driving capability of the access transistor Ta1, the value of the Y coordinate of the point B is decreased and the SNM can be increased. However, in order to increase the driving capability of the driver transistor, it is necessary to increase the channel width W, which leads to an increase in the memory cell size of the SRAM cell MC.

  As described above, improving the data storage stability (increasing SNM) in the SRAM cell MC includes increasing the cell current Icell, reducing the memory cell size, and increasing the write operation margin. There is a trade-off relationship. In recent years, as the miniaturization of the SRAM cell and the accompanying lowering of the voltage have progressed, the random variation of each of the transistors constituting the SRAM cell has increased, and the threshold voltage setting window for achieving all of these has narrowed, and process development In the initial stage, the problem that it becomes difficult to determine the cell design and the cell size has become apparent. The setting window is, for example, a graph in which the threshold voltage Vtn of the N-channel transistor constituting the SRAM is set as the X-axis and the absolute value Vtp of the threshold voltage of the P-channel transistor is set as the Y-axis in determining the process conditions (ion conditions). Is a boundary region surrounded by a point (Vtn, Vtp) at which SNM and Icell are optimal. That is, in the setting window, even if Vtn and Vtp vary, the SNM and Icell are secured, and the SRAM yield is secured. The semiconductor device of the present invention is configured to collect variation data so that the setting window can be obtained for the designed SRAM cell. In addition, when an SRAM cell having an abnormal characteristic is found, a configuration in which the characteristics of individual transistors can be evaluated in detail is adopted. That is, in the semiconductor device of the present invention, each of the m × n evaluation cells is connected to the SRAM so that the evaluation of the SRAM cell (SNM, Icell characteristics evaluation) and the characteristics of the individual transistors constituting the SRAM cell can be performed. The cell MC, the selection circuit 10, and the first transistor T1 to the sixth transistor T6 are configured as follows so that a voltage can be supplied to or detected from each node of the selected SRAM cell MC. Can be connected to each power line.

  In FIG. 2, the first transistor T1 is ON / OFF controlled by the output of the selection circuit 10 input to the gate terminal. The drain terminal of the first transistor T1 is connected to a second main input / output line V1 that supplies a voltage to the latch node LN2 or detects its output voltage. The source terminal of the first transistor T1 is connected to the latch node LN2 (the output of the inverter circuit I2 and the input of the inverter circuit I1) of the SRAM cell MC.

  The second transistor T2 is on / off controlled by the output of the selection circuit 10 input to the gate terminal. The drain terminal of the second transistor T2 is connected to a first main input / output line V0 that supplies a voltage to the latch node LN1 or detects its output voltage. The source terminal of the second transistor T2 is connected to the latch node LN1 (the output of the inverter circuit I1 and the input of the inverter circuit I2) of the SRAM cell MC.

  The third transistor T3 is on / off controlled by the output of the selection circuit 10 input to the gate terminal. The drain terminal of the third transistor T3 is connected to the main power supply line VDD for supplying the power of the SRAM cell MC (the power of the inverter circuit I1 and the inverter circuit I2). The source terminal of the third transistor T3 is connected to the power supplies of the inverter circuit I1 and the inverter circuit I2. In this embodiment, the N well layer in which the load transistors P1 and P2 are formed is supplied with a voltage by a cell power line VDDC provided separately from the main power line VDD. Further, the P-well layer in which the access transistors Ta1 and Ta2 and the driver transistors N1 and N2 are formed and the source terminals of the driver transistors N1 and N2 are provided separately from the ground line VSS commonly used in the entire semiconductor device. A ground voltage is supplied by the cell ground line VSSC.

  The fourth transistor T4 is ON / OFF controlled by the output of the selection circuit 10 input to the gate terminal. The drain terminal of the fourth transistor T4 is connected to the second bit main power supply line BLC that supplies the bit line voltage to the bit line BC. The source terminal of the fourth transistor T4 is connected to the bit line BC.

  The fifth transistor T5 is on / off controlled by the output of the selection circuit 10 input to the gate terminal. The drain terminal of the fifth transistor T5 is connected to the first bit main power supply line BLT that supplies the bit line voltage to the bit line BT. The source terminal of the fifth transistor T5 is connected to the bit line BT.

  The sixth transistor T6 is on / off controlled by the output of the selection circuit 10 input to the gate terminal. The drain terminal of the sixth transistor T6 is connected to the main gate power supply line WL that supplies the word line voltage to the gate terminals of the access transistors Ta1 and Ta2. The source terminal of the sixth transistor T6 is connected to the gate terminals of the access transistors Ta1 and Ta2.

  In the selection circuit 10, one input terminal is connected to a row selection line (Xm in this case) belonging to its own row (where the evaluation cell is located in the DMA), and the other input terminal is a column belonging to its own column. The SRAM cell is connected to a selection line (here, Yn), and in accordance with the X selection signal XSm supplied to the connected row selection line Xm and the Y selection signal YSn supplied to the column selection line Yn. A selection signal indicating selection / non-selection of MC is output. Specifically, the selection circuit 10 includes a NAND circuit 10a (negative AND circuit) and a logic inversion circuit 10b (inverter circuit).

In the NAND circuit 10a, one input terminal is connected to a row selection line (here, Xm) belonging to its own row, and the other input terminal is connected to a column selection line (here, Yn) belonging to its own column. . Then, a negative logical product signal of the X select signal XSm supplied to the row selection line Xm and the Y select signal YSn supplied to the column selection line Yn is output to the logic inversion circuit 10b. The logic inversion circuit 10b logically inverts the output signal of the NAND circuit 10a and sends a selection signal indicating selection / non-selection of the SRAM cell MC to the first transistor T1 (first switch) to the sixth transistor. Output to T6 (sixth switch).
Since the power supply voltage of the selection circuit 10 needs to be higher than the voltage supplied to the main power supply line VDD, it is connected to the peripheral power supply line VDDPERI like the peripheral circuit. The selection circuit 10 operates at 3V by supplying a voltage of 3V to the peripheral power supply terminal VDDPERIP, for example. Note that the ground voltage supplied to the selection circuit 10 is 0 V because it is connected to the ground line VSS in the same manner as the peripheral circuit and a voltage of 0 V is supplied from the ground terminal VSSP.

  As described above, in the semiconductor device according to the present embodiment, the circuit configuration of the evaluation cell is evaluated according to the X select signal XSm supplied to the row selection line Xm and the Y select signal YSn supplied to the column selection line Yn. Each node of the SRAM cell included in the cell is connected to the main power supply line VDD or the like. Hereinafter, before describing the operation of the semiconductor device according to the present embodiment, evaluation when the SRAM cell MC of the evaluation cell C11 shown in FIGS. 1 and 2 is selected will be described with reference to FIG.

  First, when the X select signal XS1 and Y select signal YS1 indicating “1” are supplied to the row selection line X1 and the column selection line Y1, respectively, and the evaluation cell C11 is selected, the power line switching circuit belonging to the first row. Since the transistor V1T1, the transistor VDDT1, and the transistor V0T1 in the PSW1 are all turned on, the second sub input / output line V11 and the second main input / output line V1 belonging to the first row are connected, and the sub power supply line VDD1 The main power supply line VDD is connected, and the first sub input / output line V01 and the first main input / output line V0 are connected.

  On the other hand, since the X select signals XS2 to XSm indicating “0” are supplied to the row selection lines X2 to Xm belonging to the other rows (second to m-th rows), the second to m-th rows. The transistors in the power supply line switching circuits PSW2 to PSWm belonging to the eyes are turned off, and the second sub input / output lines V12 to V1m, the sub power supply lines VDD2 to VDDm and the first sub input belonging to the second to mth rows are turned on. The output lines V02 to V0m are not connected to the second main input / output line V1, the main power supply line VDD, and the first main input / output line V0.

  At this time, since the transistors BLCT1, WLT1, and BLTT1 in the power supply line switching circuit PSW1 belonging to the first column are all turned on, the second bit sub-power supply line BLC1 and the second bit main power supply belonging to the first column are turned on. The line BLC is connected, the sub-gate power supply line WL1 and the main gate power supply line WL are connected, and the first bit sub-power supply line BLT1 and the first bit main power supply line BLT are connected.

  On the other hand, since the Y select signals YS2 to YSn indicating “0” are supplied to the column selection lines Y2 to Yn belonging to the other columns (the second column to the nth column), the second column to the nth column. The transistors in the power supply line switching circuits PSW2 to PSWn belonging to the eyes are turned off, and the second bit subpower supply lines BLC2 to BLCm, the subgate power supply lines WL2 to WLm and the first bit subpower supply belonging to the second to nth columns. The lines BLT2 to BLTm are disconnected from the second bit main power supply line BLC, the main gate power supply line WL, and the first bit main power supply line BLT.

  In the evaluation cell C11, a selection signal indicating “1” is output from the selection circuit 10, all of the first transistor T1 to the sixth transistor T6 are turned on, and the latch node LN2 of the SRAM cell MC is in the second state. The sub input / output line V11 (that is, the second main input / output line V1) is connected, the bit line BC is connected to the second bit sub power supply line BLC1 (that is, the second bit main power supply line BLC), and the latch node LN1 is The SRAM cell is connected to the first sub input / output line V01 (that is, the first main input / output line V0), and the bit line BT is connected to the first bit sub power supply line BLT1 (that is, the first bit main power supply line BLT). Is connected to the sub power supply line VDD1 (that is, the main power supply line VDD), and the gate terminals of the access transistors Ta1 and Ta2 The sub gate power supply line WL1 (ie main gate power supply line WL), are connected.

  In this state, an external power supply device such as a tester, the second main input / output terminal V1P (second main input / output line V1), and the first main input / output terminal V0P (first main input / output) Line V0), main power supply terminal VDDP (main power supply line VDD), second bit main power supply terminal BLCP (second bit main power supply line BLC), first bit main power supply terminal BLTP (first bit main power supply line BLT), main The gate power supply terminal WLP (main gate power supply line WL) is connected / disconnected (opened), and the voltage supplied from the power supply device is adjusted so that each node of the SRAM cell MC has a desired voltage. For example, the characteristics of the SRAM cell MC are evaluated by fixing the voltage supplied to each terminal, or by varying the voltage in a desired range and measuring the flowing current. In order to measure the current, an ammeter may be connected in series between the terminal and the power supply device.

4 shows a state where the evaluation cell C11 in FIG. 1 is selected, that is, in a state where 3V is supplied to the gate terminals of the first transistor T1 to the sixth transistor T6, the main power supply line from the external power supply device. The voltage value supplied to etc. is shown. In FIG. 4, measurement items include (1) SNM characteristic measurement, (2) access transistor Ta2 characteristic measurement, (3) driver transistor N2 characteristic measurement, and (4) load transistor P2 characteristic measurement. The supply voltage to the SRAM cell is shown.
In the figure, PMOS_Well (VDDC) is a voltage supplied to an N well where a P channel transistor (load transistor) is formed, and NMOS_Well (VSSC) is an N channel transistor (driver transistor). The voltage supplied to the P-well is indicated, and Transfer_MOS_Well (VSSC) indicates the voltage supplied to the P-well in which the N-channel transistor (access transistor) is formed. In the case of (1) SNM characteristics, since the transfer curves of the inverter circuits I1 and I2 are measured as described above, two conditions of bias 1 and bias 2 are shown.

  (1) When measuring the SNM characteristics, 1.2 V is supplied to the main power supply line VDD and the cell power supply line VDDC, and the power supply voltage of the SRAM cell MC is supplied. Further, 0V is supplied to the cell ground line VSSC. Similarly, 1.2 V is supplied to the main gate power supply line WL, and the access transistor Ta1 and the first bit main power supply line BLT are connected, and the access transistor Ta2 and the second bit main power supply line BLC are connected. In the figure, the state of bias 1 is a condition for measuring the transfer curve of the inverter circuit I2, and the first bit main power supply line BLT is in an open state (not connected to the driver pin of the power supply device or in a high impedance state). And a current flows between the latch node LN1 (the output of the inverter circuit I1 and the input of the inverter circuit I2) that changes the voltage from 0V to 1.2V and the first bit main power supply line BLT via the access transistor Ta1. Do not flow.

  In this way, the voltage supplied to the second bit main power supply line BLC is set to 1.2 V, and the voltage is supplied to the first main input / output line V0 between 0 V and 1.2 V (power supply voltage). The input / output characteristics of the inverter circuit I2 are measured by monitoring (detecting) the voltage of the second main input / output line V1. This makes it possible to obtain one transfer curve having the horizontal axis V0 and the vertical axis V1 out of the butterfly curves described above. If the current flowing through the second bit main power supply line BLC is monitored with 1.2 V supplied to the first main input / output line V0, for example, the cell current Icell flowing into the bit line BC side of the SRAM cell MC. Can be measured.

  In the bias 2 state, the second bit main power supply line BLC is opened, the voltage supplied to the first bit main power supply line BLT is 1.2 V, and the second main input / output line V1 is set to 0 V to 1.2 V. The voltage of the first main input / output line V0 is monitored (detected) to measure the input / output characteristics of the inverter circuit I1. This makes it possible to obtain the other transfer curve of the butterfly curve with the horizontal axis being V1 and the vertical axis being V0. The two transfer curves thus obtained are overlapped to create a butterfly curve, the value of one side of the square inscribed in the butterfly curve is calculated, and the SNM of the SRAM cell MC is obtained. If the current flowing through the first bit main power supply line BLT is monitored with 1.2 V supplied to the second main input / output line V1, for example, the cell current Icell flowing into the bit line BT side of the SRAM cell MC. Can be measured.

  (2) When measuring the access transistor characteristics, for example, when measuring the access transistor Ta2, the main power supply line VDD, the cell power supply line VDDC, and the first bit main power supply line BLT are opened. Then, 0V is supplied to the cell ground line VSSC, 0V is supplied to the first main input / output line V0, 0V is supplied to the second main input / output line V1, and 0.1V is supplied to the second bit main power supply line BLC. The voltage supplied to WL is increased from 0V to the positive side. That is, by setting the drain-source voltage of the access transistor Ta2 to 0.1 V and applying a voltage between the gate and the source, for example, when the drain current flows 0.1 μA, the threshold voltage Vt is defined and Vt is measured. can do.

  At this time, the reason why 0 V is supplied to the first main input / output line V0 is that the driver transistor N2 is not turned on. The reason why the main power supply line VDD and the cell power supply line VDDC are opened is to prevent current from flowing from the load transistor P2 to the latch node. The reason for opening the first bit main power supply line BLT is to prevent current from flowing from the first main input / output line V0 to the first bit main power supply line BLT via the access transistor Ta1.

  Although not shown in FIG. 4, the measurement items include not only the threshold voltage Vt but also, for example, by supplying 1.2V to the main gate power supply line WL and 1.2V to the second bit main power supply line BLC. The drain current of the access transistor Ta2 at 1.2 V can also be measured. In the above example, the measurement of the access transistor Ta2 has been described. However, the access transistor Ta1 can also be measured. For example, when measuring Vt, the main power supply line VDD, the cell power supply line VDDC, and the second bit main power supply line BLC are opened. Then, 0V is supplied to the cell ground line VSSC, 0V is supplied to the first main input / output line V0, 0V is supplied to the second main input / output line V1, and 0.1V is supplied to the first bit main power supply line BLT. The voltage supplied to WL is increased from 0V to the positive side. That is, Vt can be measured by setting the voltage between the drain and the source of the access transistor Ta1 to 0.1 V and applying a voltage between the gate and the source.

  (3) When measuring the driver transistor characteristics, for example, when measuring the driver transistor N2, the main power supply line VDD, the cell power supply line VDDC, the first bit main power supply line BLT, and the second bit main power supply line BLC are opened. Then, 0 V is supplied to the cell ground line VSSSC, 0.1 V is supplied to the second main input / output line V1, 0V is supplied to the main gate power supply line WL, and the voltage supplied to the first main input / output line V0 is increased from 0V. Raise towards. That is, by setting the voltage between the drain and source of the driver transistor N2 to 0.1 V and applying a voltage between the gate and source, for example, when the drain current flows 0.1 μA, the threshold voltage Vt is defined and Vt is measured. can do.

  At this time, the reason why the main power supply line VDD and the cell power supply line VDDC are opened is to prevent current from flowing from the load transistors P2 and P1 to the respective latch nodes. The reason why the first bit main power supply line BLT and the second bit main power supply line BLC are opened is that the first main input / output line V0 and the second main input / output line V1 are connected to the access transistors Ta1 and Ta2, respectively. This is to prevent leakage current from flowing into the first bit main power supply line BLT and the second bit main power supply line BLC.

  Although not shown in FIG. 4, the measurement items include not only the threshold voltage Vt but also 1.2V to the first main input / output line V0 and 1.2V to the second main input / output line V1. Thus, the drain current of the driver transistor N2 at 1.2V can also be measured. At this time, a current flows from the driver transistor N1 to the cell ground line VSSC. However, since the load transistor P2 and the access transistor Ta2 are turned off for the driver transistor N2, the drain current flows to another node. The drain current can be accurately measured.

  In the above example, the measurement of the driver transistor N2 has been described. However, the driver transistor N1 can also be measured. For example, when measuring Vt, the main power supply line VDD, the cell power supply line VDDC, the first bit main power supply line BLT, and the second bit main power supply line BLC are opened. Then, 0V is supplied to the cell ground line VSSSC, 0.1V is supplied to the first main input / output line V0, 0V is supplied to the main gate power supply line WL, and the voltage supplied to the second main input / output line V1 is increased from 0V. Raise towards. That is, Vt can be measured by setting the voltage between the drain and source of the driver transistor N1 to 0.1 V and applying a voltage between the gate and source.

  (4) When measuring the load transistor characteristics, for example, when measuring the load transistor P2, the cell ground line VSSSC, the first bit main power supply line BLT, and the second bit main power supply line BLC are opened. Then, 1.2V is supplied to the main power supply line VDD, 1.2V is supplied to the cell power supply line VDDC, 0V is supplied to the main gate power supply line WL, and 1.1V is supplied to the second main input / output line V1. The voltage supplied to the line V0 is lowered from 1.2V toward the minus side. That is, by defining a voltage between the drain and source of the load transistor P2 as 0.1 V and applying a negative voltage between the gate and the source, for example, when the drain current flows 0.1 μA is defined as the threshold voltage Vt, Can be measured.

  At this time, the reason why the cell ground line VSSC is opened is to prevent a current from flowing out from each latch node via the driver transistors N1 and N2. The reason why the first bit main power supply line BLT and the second bit main power supply line BLC are opened is that the first main input / output line V0 and the second main input / output line V1 are connected to the access transistors Ta1 and Ta2, respectively. This is to prevent leakage current from flowing into the first bit main power supply line BLT and the second bit main power supply line BLC.

  Although not shown in FIG. 4, the measurement items are not only the threshold voltage Vt but also by supplying 0V to the first main input / output line V0 and 1.2V to the second main input / output line V1. The drain current of the load transistor P2 at 1.2V can also be measured. At this time, a leak current flows from the cell power line VDDC to the first main input / output line V0 via the load transistor P1, but for the load transistor P2, the driver transistor N2 and the access transistor Ta2 are turned off. Therefore, the drain current does not flow to other nodes, and the drain current can be accurately measured.

  In the above example, the measurement of the load transistor P2 has been described. However, the load transistor P1 can also be measured. For example, when measuring Vt, the cell ground line VSSSC, the first bit main power supply line BLT, and the second bit main power supply line BLC are opened. Then, 1.2V is supplied to the main power supply line VDD, 1.2V is supplied to the cell power supply line VDDC, 0V is supplied to the main gate power supply line WL, and 1.1V is supplied to the first main input / output line V0. The voltage supplied to the line V1 is lowered from 1.2V toward the minus side. That is, Vt can be measured by setting the drain-source of the load transistor P1 to 0.1 V and applying a negative voltage between the gate and the source.

As described above, in the evaluation cell of the present invention, the switch (transistor) is provided corresponding to the latch node of the SRAM cell MC, so that SNM evaluation is possible, and detailed evaluation of individual transistors is also possible. . As described above, while the evaluation cell C11 is selected and the characteristic evaluation of the SRAM cell MC is performed, the first transistor T1 to the sixth transistor in the other evaluation cells C21 to Cn1 belonging to the first row. Since all of T6 are turned off, the SRAM cell MC in the evaluation cells C21 to Cn1 is electrically connected to the second sub input / output line V11, the sub power supply line VDD1, and the first sub input / output line V01 belonging to the first row. It will be in the state where it was cut off. Since all of the first transistor T1 to the sixth transistor T6 in the other evaluation cells C12 to C1m belonging to the first column are turned off, the SRAM cell MC in the evaluation cells C12 to Cn1 belongs to the first column. The second bit sub power supply line BLC1, the first bit sub power supply line BLT1, and the sub gate power supply line WL1 are electrically disconnected. Further, since the first transistor T1 to the sixth transistor T6 are made of 3V transistors, there is little off-leakage, and the voltage drop of the sub power supply line VDD1 or the like when evaluating the evaluation cell C11 is small. .
Since most of the evaluation cells in the DMA are different from the evaluation cell C11 in either row or column, the power supply line switching circuit connected to the main power supply line VDD is different, so that the voltage drop of the sub power supply line VDD1 etc. Will not be affected.

In addition, regarding the voltage drop of the main power supply line VDD and the like, since a series circuit such as a power supply line switching circuit and the first transistor T1 is formed between the wiring and the evaluation cell, the voltage drop due to leakage is small. It becomes.
That is, in the semiconductor evaluation circuit according to the present embodiment, the second sub input / output line V11, the sub power supply line VDD1, and the first sub input / output line in the row (here, the first row) to which the evaluation cell C11 to be selected belongs. Only V01 is connected to the second main input / output line V1, the main power supply line VDD, and the first main input / output line V0, and the second sub input / output line V12 of the other row (second to m-th rows). To V1m, the sub power supply lines VDD2 to VDDm, and the first sub input / output lines V02 to V0m are connected to the second main input / output line V1, the main power supply line VDD, and the first main input by the power supply line switching circuits PSW2 to PSWm. The output line V0 is electrically disconnected.

On the other hand, in the column direction as well, only the second bit sub power supply line BLC1, the first bit sub power supply line BLT1, and the sub gate power supply line WL1 of the column to which the evaluation cell C11 to be selected belongs (here, the first column) Connected to the 2-bit main power supply line BLC, the first bit main power supply line BLT, the main gate power supply line WL, the second bit sub power supply lines BLC2 to BLCn in the other columns (second column to nth column), the first bit The sub power supply lines BLT2 to BLTn and the sub gate power supply lines WL2 to WLn are electrically connected to the second bit main power supply line BLC, the first bit main power supply line BLT, and the main gate power supply line WL by the power supply line switching circuits SSW2 to SSWn. It is in a disconnected state.
As described above, by providing the power line switching circuit corresponding to each row or each column, the power line switching circuit and the first line between the wiring and the evaluation cell can be reduced even for the voltage drop of the main power line VDD or the like. Since a series circuit such as the transistor T1 is configured, a voltage drop of the main power supply line VDD or the like due to leakage is small.

  As described above, according to the semiconductor evaluation circuit according to the present embodiment, since the total leakage current generated in the entire semiconductor evaluation circuit is reduced, the voltage drop of the sub-wiring VDD1 and the like is reduced during measurement, and the selection target The characteristics of the SRAM cell can be measured with high accuracy. In the evaluation, depending on the position of the evaluation cell in the matrix array, there is no difference in the characteristics of the evaluation cell depending on the distance from the terminal supplying the voltage to the main power supply line or the like to the SRAM cell MC. As described above, it is desirable to suppress the ON resistance and the wiring resistance of the switching circuit and the first transistor T1 to the sixth transistor T6 as much as possible. However, each evaluation cell requires six sub-wirings such as the sub power supply lines VDDi (i = 1 to m) connected to the gate terminals of the first transistor T1 to the sixth transistor T6. Therefore, it is not practical to make all the wiring resistances equally low. Therefore, in the semiconductor device of this embodiment, as will be described below, the resistance value is preferentially lowered for the wiring that affects the evaluation of the characteristics of the SRAM cell MC, and the characteristics of the SRAM cell are highly accurate. It is configured to be able to measure.

  FIG. 5 is a diagram showing parasitic resistance from the terminals of the evaluation cell shown in FIG. The latch node LN1 of the SRAM cell MC includes the first main input / output terminal V0P to the first main input / output line V0, the transistor V0Ti constituting the power supply line switching circuit PSWi (i = 1 to m), the first sub input / output. A voltage is supplied through the output line V0i and the second transistor T2, or the voltage is detected. In FIG. 5, the resistance RMV0 represents the wiring resistance of the first main input / output line V0 from the first main input / output terminal V0P to the transistor V0Ti, and the first sub input from the transistor V0Ti to the second transistor T2 is shown. The wiring resistance of the output line V0i is indicated by RSV0.

  The latch node LN2 of the SRAM cell MC includes a second main input / output terminal V1P to a second main input / output line V1, a transistor V1Ti constituting the power supply line switching circuit PSWi (i = 1 to m), a second A voltage is supplied through the sub input / output line V1i and the first transistor T1, or the voltage is detected. In FIG. 5, the resistance of the second main input / output line V1 from the second main input / output terminal V1P to the transistor V1Ti is indicated by a resistor RMV1, and the second sub input from the transistor V1Ti to the first transistor T1 is shown. The wiring resistance of the output line V1i is indicated by RSV1.

  The power of the SRAM cell MC (the source terminal of the load transistor) is supplied from the main power supply terminal VDDP to the main power supply line VDD, the power supply line switching circuit PSWi (i = 1 to m), the transistor VDDTi, the sub power supply line VDDi, and the second power supply line VDDi. The voltage is supplied via the third transistor T3. In FIG. 5, the wiring resistance of the main power supply line VDD from the main power supply terminal VDDP to the transistor VDDTi is indicated by a resistor RMVDD, and the wiring resistance of the sub power supply line VDDi from the transistor VDDTi to the third transistor T3 is indicated by RSVDD. .

  The bit line BC of the SRAM cell MC includes the second bit main power supply terminal BLCP to the second bit main power supply line BLC, the transistor BLCTj constituting the power supply line switching circuit SSWj (j = 1 to n), the second bit sub power supply. A voltage is supplied via the line BLCj and the fourth transistor T4. In FIG. 5, the wiring resistance of the second bit main power supply line BLC from the second bit main power supply terminal BLCP to the transistor BLCTj is indicated by a resistor RMBLC, and the second bit sub power supply line BLCj from the transistor BLCTj to the fourth transistor T4 is shown. The wiring resistance is indicated by RSBLC.

  The bit line BT of the SRAM cell MC includes a first bit main power supply terminal BLTP, a first bit main power supply line BLT, a transistor BLTTj constituting a power supply line switching circuit SSWj (j = 1 to n), a first bit sub power supply. A voltage is supplied via the line BLTj and the fifth transistor T5. In FIG. 5, the resistance of the first bit main power supply line BLT from the first bit main power supply terminal BLTP to the transistor BLTTj is indicated by a resistor RMBLT, and the first bit sub power supply line BLTj from the transistor BLTTj to the fifth transistor T5 is shown. The wiring resistance is indicated by RSBLT.

The word line (gate terminal of the access transistor) of the SRAM cell MC is connected to the main gate power supply line WL, the main gate power supply line WL, the transistor WLTj constituting the power supply line switching circuit SSWj (j = 1 to n), and the sub-gate power supply. A voltage is supplied via the line WLj and the sixth transistor T6. In FIG. 5, the wiring resistance of the main gate power supply line WL from the main gate power supply terminal WLP to the transistor WLTj is indicated by a resistor RMWL, and the wiring resistance of the sub-gate power supply line WLj from the transistor WLTj to the sixth transistor T6 is indicated by RSWL. Show.
Further, the resistance from the cell power supply terminal VDDCP for supplying a voltage to the N well where the load transistor of the SRAM cell MC is formed to the well is a resistance RVDDC, and the cell ground terminal VSSCP for supplying the ground voltage to the SRAM cell MC to the SRAM. A resistance to the source of the driver transistor of the cell MC is indicated by a resistance RVSSC.

  In the present invention, it is necessary to lower the total resistance from the latch nodes LN1 and LN2 to the first main input / output terminal V0P and the second main input / output terminal V1P, respectively. This is because, as described above, when the SNM characteristics are evaluated, the output voltage of the latch node is accurately monitored. Further, when the resistance value of the resistor RVSSC is high, the resistance of the source terminal of the driver transistor causes a resistance to be monitored, so that the cell current Icell is monitored less. Also, the decrease of the Icell makes it difficult for the flip-flop to be inverted. Will be monitored larger, so it is necessary to lower the resistance value.

FIG. 6 is a diagram showing the wiring resistance value, the on-resistance value of the transistor, and the total resistance value up to the terminal in FIG. 5. For the evaluation cell having the highest resistance value in the matrix array, the power line switching circuit PSWi is set. The case where the ON resistance of the transistor V1Ti is 30Ω is shown.
As shown in this figure, in the present invention, the total resistance from the first main input / output terminal V0P, the second main input / output terminal V1P, and the cell ground terminal VSSSCP to the SRAM cell MC is smaller than that of the other terminals. It is set so that the value is around 200Ω. If the resistance value is suppressed to this level, for example, if the cell current Icell of the SRAM cell MC is 20 μA to 40 μA when the power supply voltage is 1.2 V, the voltage of the source terminal of the driver transistor in the SRAM cell MC increases. Is suppressed to about 4 mV to 8 mV, so that it is considered that no problem occurs in the evaluation accuracy of the SRAM cell. For example, when evaluating the SNM characteristic, the value of the Y coordinate of the intersection XB of the butterfly curve shown in FIG. 2 is the value of the output voltage of the latch node LN1. At this time, both the access transistor Ta1 and the driver transistor N1 are on. Therefore, the voltage at the latch node rises only by dividing the voltage rise at the source terminal by both transistors, so that it is considered that the influence on the SNM characteristics is small.

Next, the configuration and operation of the semiconductor device according to the present embodiment and the SRAM cell evaluation method will be described in detail with reference to FIGS.
FIG. 7 is an overall circuit diagram of a semiconductor evaluation circuit including a circuit that supplies X select signals XS1 to XSm to the row selection lines X1 to Xm and supplies Y select signals YS1 to YSn to the column selection lines Y1 to Yn. . As shown in FIG. 7, the semiconductor evaluation circuit according to the present embodiment includes a cell test circuit 20, an X select predecoder PDX, and a Y select predecoder as circuits for supplying an X select signal and a Y select signal. PDY, X-select main decoder MDX and Y-select main decoder MDY are provided. In FIG. 7, a case where n = m = 512 is assumed. The cell test circuit 20, the X select predecoder PDX, the Y select predecoder PDY, the X select main decoder MDX, and the Y select main decoder MDY constitute a selection signal supply circuit in the present invention.

  As shown in FIG. 7, the semiconductor device according to the present embodiment includes a peripheral power supply terminal VDDPERIP, a ground terminal VSSSP, a cell power supply terminal VDDCP, and a cell ground terminal VSSSCP as external terminals for supplying power. The peripheral power supply terminal VDDPERIP and the ground terminal VSSP are terminals for supplying a voltage to the power supply of the selection signal supply circuit and the selection circuit 10 in the DMA (not shown in FIG. 7). The cell power supply terminal VDDCP is a terminal that supplies a voltage to an N well in which a load transistor constituting the SRAM cell is formed. The cell ground terminal VSSSCP is a terminal for supplying a voltage to the P-well in which the N-channel type MOS transistor constituting the SRAM cell is formed and the source terminal of the driver transistor.

In addition, as described above, the semiconductor device according to the present embodiment serves as a terminal for supplying a voltage to each node of the SRAM cell in the DMA, as described above, the first main input / output terminal V0P, the second main input / output terminal V1P, the main A power supply terminal VDDP, a first bit main power supply terminal BLTP, a second bit main power supply terminal BLCP, and a main gate power supply terminal WLP are provided.
In the semiconductor device according to the present embodiment, the selector control signal input terminal SELCONTP, the clock signal input terminal CLKP, the X address input terminals AX0P to AX8P, the Y address input terminals AY0P to AY8P, and the test signal input are used as signal input terminals. A terminal TEST0P and a test signal input terminal TEST1P are provided. These input terminals are connected to the cell test circuit 20.

  The cell test circuit 20 includes a selector control signal (selection control signal) SELCONT, a clock signal CLK, a 9-bit X address signal (row address signal) AX0 to AX8, a 9-bit Y address signal (column address signal) AY0 to AY8, The test signals TEST0 and TEST1 are input, and X address decode signals AXDEC <8: 0> and AXDECB <8: 0> are generated based on these signals and output to the X select predecoder PDX and Y address decode Signals AYDEC <8: 0> and AYDECB <8: 0> are generated and output to the Y-select predecoder PDY. AXDEC <8: 0> is an integrated representation of 9-bit signals AXDEC0 to AXDEC8, and AXDECB <8: 0> is a logical inversion signal of AXDEC <8: 0>. . The same applies to AYDEC <8: 0> and AYDECB <8: 0>.

  FIG. 8 is an internal circuit configuration diagram of the cell test circuit 20. As shown in FIG. 8, the cell test circuit 20 includes a counter circuit CT, 18 selector circuits ST0 to ST17, and 18 decode signal output circuits DC0 to DC17.

  The counter circuit CT receives the selector control signal SELCONT and the clock signal CLK. When the selector control signal SELCONT is “1”, the counter circuit CT performs a count operation in synchronization with the rising edge of the clock signal CLK, and the count result is 18 bits. Counter address signals CA0 to CA17. The counter address signal CA0 of the 0th bit is output to the selector circuit ST0, the counter address signal CA1 of the 1st bit is output to the selector circuit ST1, and similarly, the counter address signal CA17 of the 17th bit is the selector circuit ST17. Is output.

  The selector circuit ST0 receives a SEL signal that is a logical inversion signal of the selector control signal SELCONT, a 0-bit counter address signal CA0, and a 0-bit Y address signal AY0, and outputs a counter according to the level of the SEL signal. Either one of the address signal CA0 and the Y address signal AY0 is selectively output. Specifically, when the SEL signal is “0” (that is, the selector control signal SELCONT is “1”), the counter address signal CA0 is output, and the SEL signal is “1” (that is, the selector control signal SELCONT is “0”). ), The Y address signal AY0 is output.

  The same applies to the selector circuits ST1 to ST8. That is, for example, the selector circuit ST8 receives the SEL signal, the 8-bit counter address signal CA8, and the 8-bit Y address signal AY8, and the counter address signal CA8 and the Y address according to the level of the SEL signal. One of the signals AY8 is selectively output.

  The selector circuit ST9 receives the SEL signal, the 9th bit counter address signal CA9, and the 0th bit X address signal AX0, and outputs the counter address signal CA9 and the X address signal AX0 according to the level of the SEL signal. Either one is selectively output. Specifically, the counter address signal CA9 is output when the SEL signal is “0”, and the X address signal AX0 is output when the SEL signal is “1”.

The same applies to the selector circuits ST10 to ST17. That is, for example, the selector circuit ST17 receives the SEL signal, the 17-bit counter address signal CA17, and the 8-bit X address signal AX8 and inputs the counter address signal CA17 and the X address according to the level of the SEL signal. One of the signals AX8 is selectively output.
Thus, among the counter address signals CA <17: 0> output from the counter circuit CT, CA <8: 0> has a corresponding relationship with the Y address signal AY <8: 0>, and CA <17: 9. > Corresponds to the X address signal AX <8: 0>.

  The decode signal output circuit DC0 receives the output signal of the selector circuit ST1, the logic inversion signal TESTB0 of the test signal TEST0, and the logic inversion signal TESTB1 of the test signal TEST1, and both the TESTB0 signal and the TESTB1 signal are “1”. In this case (that is, when both the test signals TEST0 and TEST1 are “0”), the output signal (either CA0 or AY0) of the selector circuit ST1 is output as the Y-bit decode address AYDEC0 of the 0th bit and its logic The inverted signal is output as AYDECB0. Further, the decode signal output circuit DC0 is “0” as the Y address decode signal AYDEC0 when the test signal TEST0 is “1” (TESTB0 is “0”) and the test signal TEST1 is “0” (TESTB1 is “1”). "Is output (AYDECB0 is also" 0 "). Further, when the test signal TEST1 is “1” (TESTB1 is “0”) regardless of the level of the test signal TEST0, the decode signal output circuit DC0 outputs “1” as the Y address decode signal AYDEC0 (AYDECB0 is also “ 1 ").

  The same applies to the decode signal output circuits DC1 to DC8. That is, for example, the decode signal output circuit DC8 receives the output signal of the selector circuit ST8, the TESTB0 signal, and the TESTB1 and outputs the output signals (CA8 and AY8 of the selector circuit ST8 according to the levels of the TESTB0 signal and the TESTB1 signal). Either), “0” or “1” is output as the Y-bit decode signal AYDEC8 (AYDECB8) of the eighth bit.

  The decode signal output circuit DC9 receives the output signal of the selector circuit ST9, the TESTB0 signal and the TESTB1, and outputs an output signal of the selector circuit ST9 (either CA9 or AX0) according to the levels of the TESTB0 signal and the TESTB1 signal. Either “0” or “1” is output as the X-address decode signal AXDEC0 (AXDECB0) of the 0th bit.

  The same applies to the decode signal output circuits DC10 to DC17. That is, for example, the decode signal output circuit DC17 receives the output signal of the selector circuit ST17, the TESTB0 signal, and the TESTB1 as input, and outputs the output signal (CA17 and AX8 of the selector circuit ST17 according to the levels of the TESTB0 signal and the TESTB1 signal). Either), “0” or “1” is output as the X-bit decode address signal AXDEC8 (AYDECB8) of the eighth bit.

  A truth table showing the relationship between the input signal and the output signal of the cell test circuit 20 as described above is shown in FIG. As shown in FIG. 9, when both the test signals TEST0 and TEST1 are “0” and the selector control signal SELCONT is “0”, the cell test circuit 20 is in the normal mode (random access: the first in the normal evaluation mode). Address mode) state, and the input Y address signal AY <8: 0> and X address signal AX <8: 0> are directly used as the Y address decode signal AYDEC <8: 0> (AYDECB <8: 0>) and An X address decode signal AXDEC <8: 0> (AXDECB <8: 0>) is output.

  When both the test signals TEST0 and TEST1 are “0” and the selector control signal SELCONT is “1”, the cell test circuit 20 is in a normal mode (counter access: second address mode in the normal evaluation mode), The counter address signal CA <8: 0> output from the counter circuit CT is output as a Y address decode signal AYDEC <8: 0> (AYDECB <8: 0>), and the counter address signal CA output from the counter circuit CT. <17: 9> is output as the X address decode signal AXDEC <8: 0> (AXDECB <8: 0>).

  When the test signal TEST0 is “1” and TEST1 is “0”, the cell test circuit 20 enters a test mode (all evaluation cell non-selection: second test mode), and the Y address decode signal AYDEC <8: 0. > And X address decode signals AXDEC <8: 0> are all “0” (AYDECB <8: 0> and AXDECB <8: 0> are all “0”).

When TEST1 is “1” regardless of the level of the test signal TEST0, the cell test circuit 20 enters the test mode (all evaluation cell selection: first test mode), and the Y address decode signal AYDEC <8: 0>. The X address decode signals AXDEC <8: 0> are all “1” (AYDECB <8: 0> and AXDECB <8: 0> are all “1”).
The above is the description of the cell test circuit 20, and the description will be continued below by returning to FIG.

The X select predecoder PDX predecodes the X address decode signals AXDEC <8: 0> and AXDECB <8: 0> input from the cell test circuit 20, and then outputs a predecode signal as a result of the process to the Xdecode signal XX Output to the main decoder MDX for selection. The X select main decoder MDX generates X select signals XS1 to XSm (m = 512) based on the predecode signal input from the X select predecoder PDX, and supplies them to the row select lines X1 to Xm.
The Y select predecoder PDY predecodes the Y address decode signals AYDEC <8: 0> and AYDECB <8: 0> input from the cell test circuit 20, and then outputs a predecode signal as a result of the Y decode. Output to select main decoder MDY. The Y select main decoder MDY generates Y select signals YS1 to YSn (n = 512) based on the predecode signal input from the Y select predecoder PDY and supplies them to the column select lines Y1 to Yn.

As described above, by including the cell test circuit 20, the X-select predecoder PDX, the Y-select predecoder PDY, the X-select main decoder MDX, and the Y-select main decoder MDY, the semiconductor evaluation circuit performs the following operations. Do.
In the normal mode (when the test signals TEST0 and TEST1 are “0”), the Y address signal AY <8: 0> and the X address signal AX <8: 0> remain unchanged while the selector control signal SELCONT is “0”. The Y address decode signal AYDEC <8: 0> and the X address decode signal AXDEC <8: 0> are output. That is, in this case, the evaluation cell arranged at a desired XY coordinate (row and column) by freely setting the Y address signal AY <8: 0> and the X address signal AX <8: 0> by the user. SRAM cells can be selected (random access).

  In the normal mode, during the period when the selector control signal SELCONT is “1”, the counter address signal CA <17: 0> is counted up in synchronization with the rising edge of the clock signal CLK, and the counter address signal CA < Of 17: 0>, CA <8: 0> is output as Y address decode signal AYDEC <8: 0>, and CA <17: 9> is output as X address decode signal AXDEC <8: 0>. That is, in this case, in synchronization with the count-up operation of the counter address signal CA <17: 0>, the evaluation of the m (= 512) row n (= 512) column from the evaluation cell of the first row and first column is automatically performed. The cells are sequentially selected (counter access).

  As described above, in the normal mode, either random access or counter access can be used depending on the level of the selector control signal SELCONT. In either access method, the SRAM cell of the selected evaluation cell is selected. The evaluation method is the same. In the counter access mode, 18 of the Y address signal AY (8: 0) and the X address signal AX (8: 0) are not necessary, so that the X address input terminals AX0P to AX8P and the Y address input terminals AY0P to AY8P are connected. There is no need to provide it, and the number of terminals for evaluation can be reduced.

  FIG. 10 shows an SRAM cell evaluation method in each mode. As shown in FIG. 10, in the normal mode, (1) SNM evaluation, (2) access transistor evaluation, (3) driver transistor evaluation, and (4) load transistor evaluation of the selected SRAM cell can be performed. . These evaluation contents are the same as the evaluation contents of the evaluation cell described with reference to FIG. 4, but in random access in normal mode, one of m × n evaluation cells is arbitrarily selected as described above. Therefore, each evaluation of (1) to (4) can be performed in detail by applying the bias shown in FIG. 10 to each terminal in a state where one of the evaluation cells is selected. In the counter access, 256k SRAM cells are automatically selected sequentially, so that, for example, as described in FIG. 4, the drain current of the transistors constituting the SRAM cell is first set to 256k under a constant bias condition. It is also possible to evaluate the transistor in detail by collecting all of them and finding an evaluation cell having an extremely small current value and then selecting the evaluation cell by random access.

In the test mode (all evaluation cell selection), all evaluation cells are selected simultaneously. In this case, as shown in FIG. 10, (1) SNM evaluation of all SRAM cells, (2) NBTI stress application to all SRAM cells, and (3) leakage current measurement of all SRAM cells can be performed. Hereinafter, it demonstrates in order.
(1) The voltage supply conditions to each terminal in the SNM evaluation of all SRAM cells are the same as those in the normal mode (1) except for the test signal input terminals TEST0P and TEST1P. In the present embodiment, since a butterfly curve based on the average value of the six transistors constituting the SRAM cell can be acquired, the average value of 256 kbit SNMs can be obtained. Although not shown, if evaluation is performed under the bias conditions (2) to (4) in the normal mode, an average value of 256 kbit transistor characteristics can be obtained.

(2) In NBTI stress application, 1.2V is supplied to the main power supply line VDD, 1.2V is supplied to the cell power supply line VDDC, 1.2V is supplied to the main gate power supply line WL, and 0V is supplied to the cell ground line VSSSC.
Further, the first main input / output line V0 and the second main input / output line V1 are opened. Then, 0V is supplied to the first bit main power supply line BLT and 1.2V is supplied to the second bit main power supply line BLC, and this state is maintained for a desired time. During this period, the latch node LN1 of all SRAM cells is 0V and the latch node LN2 is 1.2V. Therefore, the load transistor P2 of all SRAM cells is 1.2V at the source terminal and drain terminal, and at the gate terminal. OVTI is continuously applied, and the NBTI stress application state is maintained.

  Further, by evaluating the load transistor P2 in the normal mode before and after the test mode period, it is possible to acquire the characteristic deterioration amount due to the NBTI stress for a large-scale SRAM cell. If the lifetime of the SRAM cell calculated based on these characteristic deterioration amounts, for example, the time when the SNM becomes zero, satisfies the lifetime of the product on which the SRAM is mounted (for example, 10 years), the SRAM cell from the viewpoint of NBTI The design is complete. On the other hand, if the condition is not satisfied, measures such as lowering the absolute value of the threshold voltage Vt of the load transistor or adjusting the channel width W of the load transistor back to the cell design so as to ensure SNM in the manufacturing conditions. Can take. That is, in the semiconductor device of the present invention, by performing a reliability test, feedback can be promptly performed for process development and product development.

  When stress is applied to the load transistor P1, as described above, the main power supply line VDD is 1.2V, the cell power supply line VDDC is 1.2V, the main gate power supply line WL is 1.2V, and the cell ground line VSSSC. Is supplied with 0V. Further, the first main input / output line V0 and the second main input / output line V1 are opened. Then, 1.2V may be supplied to the first bit main power supply line BLT and 0V to the second bit main power supply line BLC, and this state may be maintained for a desired time.

  (3) In the SRAM leakage current measurement, 1.2 V is supplied to the main power supply line VDD, 1.2 V is supplied to the cell power supply line VDDC, and 0 V is supplied to the cell ground line VSSSC. Further, the first main input / output line V0 and the second main input / output line V1 are opened. In the initial stage of the test mode period, 0V is supplied to the first bit main power supply line BLT, 1.2V is supplied to the second bit main power supply line BLC, and 1.2V is supplied to the main gate power supply line WL. The voltage supplied to WL is set to 0V, and the first bit main power supply line BLT is set to 1.2V. In the initial period, the latch node LN1 of all SRAM cells is 0V and the latch node LN2 is 1.2V. Therefore, data “0” is written in all SRAM cells. Further, in the period after the voltage supplied to the first bit main power supply line BLT is set to 1.2 V, all SRAM cells are in a standby state. Therefore, an ammeter is connected to the main power supply terminal VDDP and the cell power supply terminal VDDCP. By monitoring this value, the leakage current of all SRAM cells in the state of data “0” at 1.2 V can be measured.

  When measuring the leakage current in the data “1” state, 1.2 V is supplied to the first bit main power supply line BLT and 0 V is supplied to the second bit main power supply line BLC in the initial stage of the test mode period. After the voltage supplied to the gate power supply line WL is set to 0V, the second bit main power supply line BLC may be set to 1.2V. In addition, if the voltage supplied to each power supply line is changed to other voltage value instead of 1.2V and measured at a plurality of voltage values, it is possible to take the dependence of the SRAM leakage current on the power supply voltage. These leakage current values can be used as design data because the leakage current value of only the SRAM cell is required when estimating the standby current of the product in product design.

  In the test mode (all evaluation cells are not selected), since all the evaluation cells are simultaneously unselected, no bias is applied to all SRAM cells. For this reason, during the test mode period, a voltage is supplied to the peripheral power supply terminal VDDPERIP and connected to the ammeter, so that the leakage current of all peripheral circuits (including the selection circuit 10) excluding all SRAM cells from the entire semiconductor device of the present invention. Can be measured. Note that by adding the SRAM leakage current obtained in the above-described all selection (3), the total leakage current generated in the entire semiconductor device can be calculated.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included. For example, the number of SRAM cells is not limited to the above-described example, and a large-scale matrix configuration may be used by increasing the number of address terminals. In addition, the relationship between rows and columns may be interchanged. In the above-described embodiment, the first sub input / output line, the second sub input / output line, and the sub power supply line are provided in the row direction, and the first bit sub power supply line, the second bit sub power supply line, and the sub power supply line are provided. Although the case where three gate power supply lines are provided in the column direction has been illustrated, it is not determined whether each of these lines is provided in the row direction or the column direction. It may be provided on one side in the column direction, or 6 may be divided into 4 and 2 to provide 2 rows and 4 columns. Further, the first sub input / output line, the second sub input / output line, and the cell ground line VSSSC may be wired so as to have a low resistance value, and the rest may be wired according to the aspect ratio of the SRAM cell.

  In the above embodiment, as shown in FIG. 2 as the internal circuit configuration of the evaluation cell, the voltage of the P-well in which the NMOS transistor constituting the SRAM cell is formed and the voltage supplied to the source terminal of the driver transistor are Although the configuration is such that the cell ground line VSSSC is used for the supply, the P well voltage supply line may be the cell ground line VSSSC, and the source terminal of the driver transistor may be connected to the ground line VSS. In this way, the voltage supplied to the cell ground line VSSSC can be changed, the back bias characteristics of the NMOS transistor can be changed, and the characteristics of the single transistor can be evaluated in more detail. In the above embodiment, the six-transistor cell is used. However, the SRAM cell has a four-transistor type that holds data by connecting a high resistance load element, one end of which is connected to the power source of the SRAM cell, to the latch node. It may be a cell.

C11, C12, C21, Cn1, C1m, Cnm ... evaluation cell,
V1 ... second main input / output line, VDD ... main power supply line, V0 ... first main input / output line,
V11, V12, V1i, V1m, second sub input / output lines,
VDD1, VDD2, VDDi, VDDm ... sub power line,
V01, V02, V0i, V0m... First sub input / output line,
BLC ... second bit main power supply line, WL ... main gate power supply line, BLT ... first bit main power supply line,
BLC1, BLC2, BLCj, BLCn ... 2nd bit sub power supply line,
WL1, WL2, WLj, WLn ... sub-gate power supply line,
BLT1, BLT2, BLTj, BLTn... First bit sub power line,
VSSC: Cell ground line, VDDC: Cell power line, VSS: Ground line, VDDPERI: Peripheral power line,
Y1, Y2, Yn ... column selection lines, X1, X2, Xm ... row selection lines,
PSW1, PSW2, PSWi, PSWm, SSW1, SSW2, SSWj, SSWn ... power line switching circuit,
DESCRIPTION OF SYMBOLS 10 ... Selection circuit, 10a ... NAND circuit, 10b ... Logic inversion circuit, 20 ... Cell test circuit, DC0, DC1, DC8, DC9, DC10, DC17 ... Decode signal output circuit,
ST0, ST1, ST8, ST9, ST10, ST17 ... selector circuit, CT ... counter circuit,
AY, AY0, AY8 ... Y address signal,
AX, AX0, AX8 ... X address signal,
CA, CA0, CA1, CA8, CA9, CA17... Counter address signal,
SELCONT ... selector control signal, CLK ... clock signal, TEST0, TEST1 ... test signal,
T1 ... 1st transistor, T2 ... 2nd transistor, T3 ... 3rd transistor,
T4 ... fourth transistor, T5 ... fifth transistor, T6 ... sixth transistor,
PDX ... X select predecoder, PDY ... Y select predecoder,
MDX ... X select main decoder, MDY ... Y select main decoder,
V1P: second main input / output terminal, V0P: first main input / output terminal, VDDP: main power supply terminal,
BLCP ... 2nd bit main power supply terminal, BLTP ... 1st bit main power supply terminal, WLP ... main gate power supply terminal, VSSCP ... cell ground terminal, VDDCP ... cell power supply terminal, VDDPERIP ... peripheral power supply terminal, VSSSP ... ground terminal, SELCONTP ... Selector control signal input terminal, CLKP ... clock signal input terminal, TEST0P, TEST1P ... test signal input terminal, AX0P ... X address input terminal, AY0P ... Y address input terminal

Claims (15)

A semiconductor device for evaluating the characteristics of an SRAM cell,
A plurality of evaluation cells having SRAM cells;
A selection line for supplying a selection signal for selecting the evaluation cell;
A main power supply line for supplying a power supply voltage of the SRAM cell;
A main gate power supply line for supplying an input voltage to the gates of the first data transfer transistor and the second data transfer transistor of the SRAM cell;
A first main input / output line for supplying an input voltage to the first latch node of the SRAM cell or detecting an output voltage thereof;
A second main input / output line for supplying an input voltage to the second latch node of the SRAM cell or detecting an output voltage thereof;
A first bit main power line for supplying a first bit line voltage to the first latch node via the first data transfer transistor of the SRAM cell;
A second bit main power supply line for supplying a second bit line voltage to the second latch node via the second data transfer transistor of the SRAM cell;
Based on the selection signal, each of the evaluation cells includes its own SRAM cell, the main power supply line, the main gate power supply line, the first main input / output line, the second main input / output line, A control circuit that outputs a control signal to a transistor having a lower off-leakage than a transistor constituting the SRAM cell, wherein the first bit main power supply line and the second bit main power supply line are connected or disconnected;
The control circuit is constituted by a transistor having less off-leakage than a transistor constituting the SRAM cell, and outputs the control signal in response to the selection signal that is higher than a power supply voltage supplied to the SRAM cell. And the main power supply line, the main gate power supply line, the first main input / output line, the second main input / output line, the first bit main power supply line, and the second bit main power supply line. Alternatively, the semiconductor device is not connected. The plurality of evaluation cells are arranged in a matrix of m rows and n columns (m and n are positive integers),
The selection signal supply selection line is provided for each row, and is provided for each column and a row selection signal for supplying a row selection signal for selecting the evaluation cell belonging to each row, and belongs to each column. A column selection line for supplying a column selection signal for selecting the evaluation cell;
Each of the evaluation cells includes its own SRAM cell, the main power supply line, the main gate power supply line, the first main input / output line, and the second response line in response to the row selection signal and the column selection signal. 2. The semiconductor device according to claim 1, wherein a main input / output line, the first bit main power supply line, and the second bit main power supply line are connected or disconnected. A sub power supply line provided for each row or each column, for supplying the power supply voltage of the SRAM cell of the evaluation cell belonging to each said row or each column;
Connection / non-connection between the sub power supply line and the main power supply line according to a row selection signal belonging to the same row as the sub power supply line or a column selection signal belonging to the column. A power line switching circuit for switching between,
To supply a power supply voltage for supplying an input voltage to the gate of the first data transfer transistor and the second data transfer transistor of the SRAM cell of the evaluation cell belonging to each row or each column provided for each row or each column Sub-gate power supply line,
In response to a row selection signal belonging to the same row as the sub-gate power supply line or a column selection signal belonging to the column, the sub-gate power supply line and the main gate power supply line A gate power line switching circuit for switching connection / disconnection;
A first sub input / output line provided for each row or column and supplying an input voltage to the first latch node of the SRAM cell of the evaluation cell belonging to each row or column or detecting the output voltage; ,
The first sub input / output line is provided corresponding to the first sub input / output line, and the first sub input / output line corresponds to a row selection signal belonging to the same row as the first sub input / output line or a column selection signal belonging to the column. A first input / output line switching circuit for switching connection / disconnection between a line and the first main input / output line;
A second sub-input / output line that is provided for each row or each column and supplies an input voltage to the second latch node of the SRAM cell of the evaluation cell belonging to each row or each column or detects its output voltage; ,
The second sub input / output line is provided corresponding to the second sub input / output line, and the second sub input / output line corresponds to a row selection signal belonging to the same row as the second sub input / output line or a column selection signal belonging to the column. A second input / output line switching circuit for switching connection / disconnection between the line and the second main input / output line;
A first bit line voltage is supplied to the first latch node via the first data transfer transistor of the SRAM cell of the evaluation cell that is provided for each row or each column and belongs to each row or each column. A first bit sub-power supply line;
In response to a row selection signal belonging to the same row as the first bit sub-power supply line or a column selection signal belonging to a column, the first bit sub-power supply line and the first bit sub-power supply line A first bit power supply line switching circuit for switching connection / disconnection with the first bit main power supply line;
A second bit line voltage is supplied to the second latch node via the second data transfer transistor of the SRAM cell of the evaluation cell that is provided for each row or each column and belongs to each row or each column. A second bit sub-power supply line;
In response to a row selection signal belonging to the same row as the second bit sub-power supply line or a column selection signal belonging to a column, the second bit sub-power supply line and the second bit sub-power supply line The semiconductor device according to claim 2, further comprising: a second bit power supply line switching circuit that switches connection / disconnection with the second bit main power supply line. Each of the evaluation cells is
One input terminal is connected to the row selection line belonging to its own row, and the other input terminal is connected to the column selection line belonging to its own column and supplied to the connected row selection line. A selection circuit that outputs a selection signal indicating selection / non-selection of its own SRAM cell in accordance with a row selection signal and a column selection signal supplied to a column selection line;
A first switch for switching connection / disconnection between the second sub input / output line belonging to the same row or column as the self and the second latch node of the self SRAM cell according to the selection signal;
A second switch for switching connection / disconnection between the first sub input / output line belonging to the same row or column as the self and the first latch node of the self SRAM cell according to the selection signal;
A third switch for switching connection / disconnection between the sub power supply line belonging to the same row or column as the self and a power supply terminal of the self SRAM cell according to the selection signal;
A fourth switch for switching connection / disconnection between the second bit sub-power supply line belonging to the same row or column as the self and the second bit line of the self SRAM cell according to the selection signal;
A fifth switch for switching connection / disconnection between the first bit sub-power supply line belonging to the same row or column as the self and the first bit line of the self SRAM cell according to the selection signal;
And a sixth switch for switching connection / disconnection between the sub-gate power supply line belonging to the same row or column as the self and the data transfer transistor of the own SRAM cell according to the selection signal. The semiconductor device according to claim 3. In each of the plurality of evaluation cells,
A total resistance comprising a wiring resistance of the first main input / output line, a switch resistance of the first input / output line switching circuit, a wiring resistance of the first sub input / output line, and a switch resistance of the second switch;
A total resistance composed of a wiring resistance of the second main input / output line, a switch resistance of the second input / output line switching circuit, a wiring resistance of the second sub input / output line, and a switch resistance of the first switch;
And the wiring resistance of the cell ground wiring for supplying the ground voltage to the SRAM cell, respectively,
Wiring resistance of the main power supply line, switch resistance of the power supply line switching circuit, wiring resistance of the sub power supply line, and total resistance consisting of switch resistance of the third switch,
A total resistance comprising a wiring resistance of the first bit main power supply line, a switch resistance of the first bit power supply line switching circuit, a wiring resistance of the first bit sub power supply line, and a switch resistance of the fifth switch;
A total resistance comprising a wiring resistance of the second bit main power supply line, a switch resistance of the second bit power supply line switching circuit, a wiring resistance of the second bit sub power supply line, and a switch resistance of the fourth switch;
The wiring resistance of the main gate line, the switch resistance of the gate power supply line switching circuit, the wiring resistance of the sub-gate power supply line, and the total resistance composed of the switch resistance of the sixth switch are set to be smaller than any of the above. 5. The semiconductor device according to claim 4, wherein: A selection signal supply circuit for supplying a column selection signal to each column selection line and supplying a row selection signal to each row selection line;
The selection signal supply circuit has a selection control signal, a clock signal, a column address signal, a row address signal, and two test signals as inputs,
Depending on the state of the two test signals, the mode shifts to a normal evaluation mode, a first test mode, or a second test mode,
In the normal evaluation mode, a first address mode that generates the column selection signal and the row selection signal based on the column address signal and the row address signal according to the state of the selection control signal, and the clock signal Performing a count operation in synchronization, and switching between the second address mode for generating the column selection signal and the row selection signal based on the count result;
In the first test mode, the column selection signal and the row selection signal for selecting all the evaluation cells are generated, and in the second test mode, the column for deselecting all the evaluation cells. 6. The semiconductor device according to claim 2, wherein a selection signal and the row selection signal are generated. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated, using the semiconductor device according to claim 1;
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power line;
The second bit main power supply line is opened,
Supplying a first variable input voltage to the second main input / output line;
Detecting a change in the first output voltage of the first main input / output line;
A third step of obtaining a first input / output characteristic;
Supplying the bit line voltage to the second bit main power line;
The first bit main power supply line is opened;
Supplying a second variable input voltage to the first main input / output line;
Detecting a change in the second output voltage of the second main input / output line;
A fourth step of acquiring a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the SRAM cell as a static noise margin of the evaluation cell. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated, using the semiconductor device according to claim 1;
A second step of supplying a ground voltage to the first main input / output line and the second main input / output line to open the main power supply line;
Either one of the first bit main power supply line and the second bit main power supply line is opened, and a desired voltage is supplied to the other.
Supplying a variable gate voltage to the main gate power line;
A third step of evaluating characteristics of the first data transfer transistor or the second data transfer transistor by measuring a current flowing through the other of the first bit main power supply line and the second bit main power supply line; A method for evaluating a semiconductor device, comprising: A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated, using the semiconductor device according to claim 1;
A second step of supplying a desired voltage to the main power supply line and a ground voltage to the main gate power supply line to open the first bit main power supply line and the second bit main power supply line;
Supplying a desired voltage to one of the first main input / output line and the second main input / output line, and supplying a variable voltage to the other;
And a third step of evaluating a characteristic of the driver transistor by measuring a current flowing through one of the first main input / output line and the second main input / output line. Evaluation method. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell having a load transistor,
A first step of supplying a selection signal for selecting an evaluation cell to be evaluated, using the semiconductor device according to claim 1;
A second step of supplying a desired voltage to the main power supply line and a ground voltage to the main gate power supply line to open the first bit main power supply line and the second bit main power supply line;
Supplying a desired voltage to one of the first main input / output line and the second main input / output line, and supplying a variable voltage to the other;
And a third step of evaluating the characteristics of the load transistor by measuring a current flowing through one of the first main input / output line and the second main input / output line. Device evaluation method. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
When performing the characteristic evaluation using the first address mode of the normal evaluation mode using the semiconductor device according to claim 6,
The state of the two test signals input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit corresponds to the first address mode A first step of inputting a column address signal and a row address signal representing the position of the evaluation cell to be evaluated to the selection signal supply circuit;
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power line;
The second bit main power supply line is opened,
Supplying a first variable input voltage to the second main input / output line;
Detecting a change in the first output voltage of the first main input / output line;
A third step of obtaining a first input / output characteristic;
Supplying the bit line voltage to the second bit main power line;
The first bit main power supply line is opened;
Supplying a second variable input voltage to the first main input / output line;
Detecting a change in the second output voltage of the second main input / output line;
A fourth step of acquiring a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the SRAM cell as a static noise margin of the evaluation cell. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
When performing the characteristic evaluation using the second address mode of the normal evaluation mode using the semiconductor device according to claim 6,
The state of the two test signals input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit corresponds to the second address mode A first step set to
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power line;
The second bit main power supply line is opened,
Supplying a first variable input voltage to the second main input / output line;
Detecting a change in the first output voltage of the first main input / output line;
A third step of obtaining a first input / output characteristic;
Supplying the bit line voltage to the second bit main power line;
The first bit main power supply line is opened;
Supplying a second variable input voltage to the first main input / output line;
Detecting a change in the second output voltage of the second main input / output line;
A fourth step of acquiring a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the SRAM cell as a static noise margin of the evaluation cell. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
When using the semiconductor evaluation circuit according to claim 6 and performing the characteristic evaluation using the first test mode,
A first step of setting a state of two test signals input to the selection signal supply circuit to a state corresponding to a first test mode;
A second step of supplying an SRAM cell power supply voltage to the main power supply line and a desired gate voltage to the main gate power supply line;
Supplying a desired bit line voltage to the first bit main power line;
The second bit main power supply line is opened,
Supplying a first variable input voltage to the second main input / output line;
Detecting a change in the first output voltage of the first main input / output line;
A third step of obtaining a first input / output characteristic;
Supplying the bit line voltage to the second bit main power line;
The first bit main power supply line is opened;
Supplying a second variable input voltage to the first main input / output line;
Detecting a change in the second output voltage of the second main input / output line;
A fourth step of acquiring a second input / output characteristic;
The first input / output characteristic is plotted on the first variable input voltage on the X axis, the first output voltage is plotted on the Y axis, and the second input / output characteristic is plotted on the second variable input voltage. Is plotted on the Y-axis, the second output voltage is plotted on the X-axis, and the smaller square of the two squares inscribed in the plotted first and second input / output characteristics And a fifth step of setting one side of the static noise margin of the entire SRAM cell included in all the evaluation cells, to the semiconductor device evaluation method. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell having a load transistor,
When using the semiconductor evaluation circuit according to claim 6 and performing the characteristic evaluation using the first test mode,
A first step of setting a state of two test signals input to the selection signal supply circuit to a state corresponding to a first test mode;
SRAM cell power supply voltage to the main power supply line, the power supply voltage to the main gate power supply line, the power supply voltage to one of the first bit main power supply line and the second bit main power supply line, Supply ground voltage to the other,
Opening the first main input / output line and the second main input / output line;
And a second step of performing a stress test on load transistors of SRAM cells included in all evaluation cells. A method for evaluating a semiconductor device for evaluating characteristics of an SRAM cell, comprising:
When using the semiconductor evaluation circuit according to claim 6 and performing the characteristic evaluation using the first test mode,
A first step of setting a state of two test signals input to the selection signal supply circuit to a state corresponding to a first test mode;
SRAM cell power supply voltage to the main power supply line, the power supply voltage to the main gate power supply line, the power supply voltage to one of the first bit main power supply line and the second bit main power supply line, Supply ground voltage to the other,
A second step of opening the first main input / output line and the second main input / output line;
Supplying the power supply voltage to the other of the first bit main power supply line and the second bit main power supply line, then supplying a ground voltage to the main gate power supply line, and measuring a current flowing through the main power supply line; And a third step of measuring the leakage current of the SRAM cells included in all the evaluation cells.

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