JP2013246858A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses current flowing when the device is not operated and is operated to reduce battery power consumption of a product such as a mobile product, and that eliminates malfunction and stopping of a system due to thermal runaway.SOLUTION: The semiconductor device comprises an SRAM including second conductivity-type driver transistors M3, M4, second conductivity-type access transistors M5, M6, first conductivity-type load transistors M1, M2 and a leakage suppression transistor M10. The leakage suppression transistor M10 is a second conductivity type, and has: a gate connected to a source of the access transistor M6; a drain connected to a common source of the driver transistors M3, M4; and a source connected to a power supply VSS. The access transistor M5 has a drain connected to a bit line RBL, and a gate connected to a word line RWL. The access transistor M6 has a drain connected to a bit line WBL, and a gate connected to a word line WWL.

Description

  The present invention relates to a semiconductor device, and can be suitably used for, for example, a semiconductor device incorporating an SRAM (Static Random Access Memory).

  In recent years, in LSI (Large Scale Integration), measures have been taken to reduce the power supply voltage with respect to an increase in power consumption and a breakdown voltage deterioration of a transistor. However, while this measure to reduce the power supply voltage solves the above-described problem, it causes a problem that the current that can be obtained from the transistor is reduced and the operation speed of the mounted circuit is delayed. Therefore, in general, a method of increasing the current that can be obtained from the transistor by taking a means for lowering the threshold voltage of the transistor has been taken. However, there is a problem that the leakage current (subthreshold current) that flows when the transistor is turned off increases due to the lowered threshold voltage.

  For example, in the SRAM macro, the readout current of the SRAM macro can be improved and the access speed can be increased by taking a large read current flowing through the memory cell together with a sufficient bias voltage applied to the gate of the driver transistor. However, contrary to the increase in reading speed, there arises a problem that the leakage current flowing through the memory cell increases with the bias voltage in the memory cell during standby.

  Thus, performance improvement (increase in read current) and problem occurrence (increase in leakage current) are in a trade-off relationship with each other in the memory cell, and it is difficult to improve both simultaneously. In addition, various LSIs equipped with SRAMs have advanced transistor miniaturization, and a technique for solving both of these simultaneously is desired.

  As a technique related to the above problem, a semiconductor memory device is disclosed in Japanese Patent Application Laid-Open No. 2004-206745 (Japanese Patent No. 4388274: US Publication US20040125681 (A1)). The method of reducing the leakage current of the SRAM memory cell disclosed in Japanese Patent Application Laid-Open No. 2004-206745 is as follows. The source nodes (eg, ground nodes of driver MOS transistors in the memory cells) of the memory cells arranged in the memory array are made common. The common node is connected to the ground potential via a resistor, a diode, and a switch MOS transistor. When the memory array is in the standby state, the switch MOS transistor is turned off, and the common source node of each memory cell becomes higher than the ground potential, so that the leakage current of the memory cell and the memory array can be reduced.

  Japanese Unexamined Patent Application Publication No. 2003-249078 discloses a semiconductor device. In the method disclosed in Japanese Patent Laid-Open No. 2003-249078, an NMOS transistor Q7 is provided between a common source of driver transistors of an SRAM memory cell and a ground power supply VSS. During standby, the NMOS transistor Q7 is turned off, the common source potential VSSMC rises, and the leakage current is reduced. On the other hand, at the time of reading and writing, by turning on the NMOS transistor Q7, the potential VSSMC of the common source is substantially set to the ground potential VSS, thereby suppressing a decrease in operating speed.

  Japanese Patent Laid-Open No. 2005-293629 discloses an SRAM device. In the method disclosed in Japanese Patent Laid-Open No. 2005-293629, an NMOS transistor MN3 is provided between a common source of driver transistors of an SRAM memory cell and a ground power supply. The gate of the NMOS transistor MN3 inputs a signal synchronized with the word line signal. In the data holding state (standby mode), the NMOS transistor MN3 is turned off, and the potential of the common source is raised to reduce the leakage current in the memory cell. On the other hand, when the word line is activated (during reading and writing), the NMOS transistor MN3 is turned on in synchronization with the word line signal. For this reason, the potential of the common source is almost the ground potential, and a decrease in operation speed during data reading is suppressed. As another method, a PMOS transistor MP3 is provided between the common source of the load transistors of the SRAM memory cell and the power supply VDD, and a signal synchronized with the word line signal is input to the gate. In the data holding state (during standby), the PMOS transistor MP3 is turned off. Therefore, the potential of the common source is lower than the power supply voltage on the high potential side, and leakage current flowing in the memory cell is reduced. On the other hand, when the word line is activated (during reading and writing), the PMOS transistor MP3 is turned on, and the common source potential is set to the power supply potential VDD, thereby reducing the operation speed during data reading. Suppress.

  Japanese Unexamined Patent Application Publication No. 2009-026461 (US Pat. No. 5,668,770 (A)) discloses a semiconductor device. The method disclosed in Japanese Patent Application Laid-Open No. 2009-026461 is a method for reducing a leak current flowing in a memory cell by increasing a threshold voltage of a transistor constituting the SRAM memory cell. In this method, in order to operate the latch circuit in the memory cell, the stored data is held by making the power supply voltage (VCH) connected to the memory cell higher than the voltage (VCC) of the data line. However, in this method, since the voltage (VCC) of data written from the data line is lower than the power supply voltage (VCH) of the memory cell, the data held in the memory cell cannot be rewritten. As a countermeasure, a PMOS transistor Qp is provided between the common source of the load transistor of the memory cell and the power supply VCH. When writing data, the PMOS transistor Qp is turned off, and the power supply (VCH) is supplied from the latch circuit in the memory cell. Once disconnected, data can be rewritten.

  A. Teman, et al. , “A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)”. IEEE Journal of Solid-State Circuits, Vol. Nos. 46 and 2011 disclose an SRAM configuration and a memory cell in which one transistor is added to a memory cell constituted by eight transistors. The PMOS transistor M9 has a source connected to the power supply VDD, a drain connected to the power feeding node of the memory cell, and a gate connected to the source of the access NMOS transistor M2. With this configuration, the supply potential of the memory cell is lowered to improve the write characteristics. Further, it is stated that the PMOS transistor M9 has an effect of reducing the leakage current in the memory cell as compared with the conventional eight transistors.

JP 2004-206745 A JP 2003-249078 A JP 2005-293629 A JP 2009-026461 A

A. Teman, et al. "A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)", IEEE Journal of Solid-State Circuits, Vol. 46, 2011.

  In the system LSI, it is an important issue to suppress the current flowing during operation as much as possible to eliminate the malfunction and stop of the system due to thermal runaway. For example, an SRAM macro mounted on a large-scale system LSI has a large-capacity memory array of several tens of megabytes, so that leakage current flowing through unselected memory cells can be suppressed not only during standby but also during access. It is becoming an important technical issue. In addition, since the charge / discharge current flowing through the bit line becomes the dominant power in the memory array during the read operation, reducing the charge / discharge current of the bit line is also a technical problem to be overcome. In view of these technical problems, the above-described literature methods cannot sufficiently cope with this problem for the following reasons.

  In the method disclosed in Japanese Patent Application Laid-Open No. 2004-206745 (Japanese Patent No. 4388274), when a memory array is enabled, a switch MOS transistor is turned on, so that a common source is used in all memory cells regardless of selection or non-selection. Make the node grounded. Therefore, the leak current flowing in the memory cell cannot be reduced in the memory array when enabled or the memory array being accessed.

  The method disclosed in Japanese Patent Laid-Open No. 2003-249078 is a method for lowering / increasing the power supply potential VSSMC on the low potential side of the memory cell in response to the activation / inactivation of a word line selection signal (or a signal equivalent thereto). It is. Accordingly, the power supply potential VSSMC changes in synchronization with the word line selection signal. As a result, after the word line signal rises, a grace time is required until the power supply potential VSSMC is stabilized, which causes a delay in access time. In addition, a control circuit for switching the power supply potential VSSMC is required for each word line, which increases the chip area and power.

  The method disclosed in Japanese Patent Laid-Open No. 2005-293629 has the following problems. In this method, the power supply potential on the low potential side of the memory cell is lowered / increased in response to the activation / inactivation of the word line selection signal (or a signal equivalent thereto), or the power supply on the high potential side of the memory cell. In this method, the potential is increased / decreased. Accordingly, when the memory cell is accessed, the power supply potential of the memory cell changes after the word line selection signal is output. As a result, the memory cell requires a grace time until the power supply potential is stabilized, which causes the access time to be delayed. In addition, a control circuit for switching the power supply potential is required for each word line, which increases the chip area and power.

  The method disclosed in JP 2009-026461 has the following problems. In this system, the supply voltage to the memory cell is disconnected when the memory cell is accessed, and the supply voltage is connected to the memory cell during standby. For this reason, a grace time is required until the power supply voltage is stabilized after the supply voltage is switched, and this grace time causes the access time to be delayed. Further, since the switching signal is a word line selection signal or a signal delayed from the word line selection signal, this also causes a delay in access. Furthermore, a control circuit for switching the power supply voltage is required, which increases the chip area and power.

  IEEE Journal of Solid-State Circuits, Vol. The methods disclosed in 46 and 2011 have the following problems. Since this system is configured by using nine MOS transistors in the memory cell, the area of the memory array is increased by 1.5 times or more than the conventional six-transistor memory cell. In addition, since the power supply node on the VDD side of the memory cell does not immediately reach a stable potential after the access, the leakage current is larger than that of the conventional memory cell using eight transistors over several cycles after the write access. Has the disadvantage of increasing.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, in a semiconductor device including an SRAM, an NMOS transistor is connected between a common source of a driver transistor and a power supply, and a gate is connected to a storage node. Alternatively, a PMOS transistor is connected between the common source of the load transistor and the power supply, and the gate is connected to the storage node.

  According to the embodiment, in the semiconductor device, the read operation current and the leak current flowing during standby can be reduced as much as possible, and the malfunction and stop of the system due to thermal runaway can be suppressed.

FIG. 1A is a block diagram showing the configuration of the semiconductor device according to the first embodiment. FIG. 1B is a block diagram of the SRAM macro showing the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a circuit diagram showing the configuration of the memory cell of the semiconductor device according to the first embodiment. FIG. 3A is a circuit diagram showing a memory cell storing data “1” in storage node SNT. FIG. 3B is an equivalent circuit showing a memory cell storing data “1” in the storage node SNT. FIG. 3C is an equivalent circuit showing a memory cell storing data “1” in the storage node SNT. FIG. 4 is a graph showing the retention cycle dependence of the average leakage current of the memory cell storing data “1” in the storage node SNT. FIG. 5 is a graph showing the correlation between the distribution ratio of data “1” and the leakage current of all the memory cells in the memory cell array. FIG. 6 is a graph showing the correlation between the distribution ratio of data “1” and the leakage current of all the memory cells in the memory cell array. FIG. 7 is a graph showing the correlation between the distribution ratio of data “1” and the leakage current of all the memory cells in the memory cell array. FIG. 8 is a graph showing the correlation between the distribution ratio of data “1” and the leakage current of all the memory cells in the memory cell array. FIG. 9 is a graph showing the correlation between the distribution ratio of data “1” and the leakage current of all the memory cells in the memory cell array. FIG. 10 is a graph showing the retention cycle dependency of the total leakage current of the memory cell array. FIG. 11A is a diagram for explaining a method of reducing the leakage current of the memory cell in the holding period. FIG. 11B is a diagram illustrating a method for reducing the leakage current of the memory cell in the holding period. FIG. 11C is a diagram illustrating a method for reducing the leakage current of the memory cell in the holding period. FIG. 12 is a diagram for explaining another method for reducing the leakage current of the memory cell during the holding period. FIG. 13 is a schematic plan view showing an example of the layout of the memory cell according to the first embodiment. FIG. 14 is a circuit diagram showing a configuration of a memory cell of the semiconductor device according to the second embodiment. FIG. 15 is a diagram for explaining the effect of suppressing the bit line current flowing from the bit line into the memory cell during the read operation. FIG. 16 is a table showing an example of the effect of suppressing the bit line current under each device condition. FIG. 17 is a circuit diagram showing the configuration of the memory cell of the semiconductor device according to the third embodiment. FIG. 18A is a circuit diagram showing a memory cell storing data “1” in storage node SNT. FIG. 18B is an equivalent circuit showing a memory cell storing data “1” in the storage node SNT. FIG. 18C is an equivalent circuit showing a memory cell storing data “1” in the storage node SNT. FIG. 19 is a graph showing the retention cycle dependence of the average leakage current of the memory cell storing data “1” in the storage node SNT. FIG. 20 is a circuit diagram showing the configuration of the memory cell of the semiconductor device according to the fourth embodiment. FIG. 21A is a circuit diagram showing a memory cell storing data “1” in storage node SNT. FIG. 21B is an equivalent circuit showing a memory cell storing data “1” in the storage node SNT. FIG. 21C is an equivalent circuit showing a memory cell storing data “1” in the storage node SNT. FIG. 22 is a graph showing the dependency of the average leakage current flowing in the memory cell storing data “1” in the storage node SNT on the retention cycle. FIG. 23 is a circuit diagram showing the configuration of the memory cell of the semiconductor device according to the fifth embodiment. FIG. 24 shows an example of the effect of suppressing the bit line current under the corner conditions of the device and the power supply voltage. FIG. 25 is a graph showing the retention cycle dependency of the leakage current in each control method. FIG. 26 is a graph showing the retention cycle dependency of the leakage current in each control method. FIG. 27 is a graph showing the retention cycle dependency of the leakage current in each control method. FIG. 28 is a graph showing the retention cycle dependency of the leakage current in each control method. FIG. 29 is a graph showing the temperature dependence of the suppression effect of the bit line current under each device condition. FIG. 30 is a graph showing the temperature dependence of the bit line current suppression effect under each device condition. FIG. 31 is a graph showing the temperature dependence of the bit line current suppression effect under each device condition. FIG. 32 is a graph showing the temperature dependence of the reduction rate of the WBL line discharge current based on the conventional cell with respect to the bit line current under each corner condition of the device and the power supply voltage. FIG. 33 is a table showing the delay time of the read signal from the rise of the word line until the read signal is output. FIG. 34 is a graph showing the increase rate of the delay time in each control method based on the delay time of the conventional cell with respect to the result of FIG. FIG. 35 is a graph showing the increase rate of the delay time in each control method based on the delay time of the conventional cell with respect to the result of FIG.

  Hereinafter, embodiments of a semiconductor device will be described with reference to the accompanying drawings.

(First embodiment)
A configuration of the semiconductor device according to the first embodiment will be described.
1A and 1B are block diagrams showing the configuration of the semiconductor device according to the first embodiment. FIG. 1A shows an example of an LSI (semiconductor chip) mixed with a memory as the semiconductor device 1. FIG. 1B shows an example of the SRAM macro 2 mounted on the semiconductor device 1. As illustrated in FIG. 1A, the semiconductor device 1 includes an arithmetic processing circuit 3 including an SRAM macro 2, a peripheral circuit 4 including the SRAM macro 2, and other SRAM macros 2. As shown in FIG. 1B, the SRAM macro 2 has a memory cell MC in which a bit line is configured as a single end during a read operation.

  The SRAM macro 2 includes a memory cell array MCA, an address buffer AB, a row decoder RD, a word driver (not shown), a column decoder CD, a column selector CS, a sense amplifier / data output buffer SABF, and an input buffer. It has DIB. The memory cell array MCA includes a plurality of memory cells MC, a plurality of word lines WWL and RWL, and a plurality of bit lines RBL and WBL. The plurality of word lines WWL and RWL extend in the X direction. The plurality of bit lines RBL and WBL extend in the Y direction. The plurality of memory cells MC are arranged in a matrix corresponding to a plurality of intersections between the plurality of word lines WWL, RWL and the plurality of bit lines RBL, WBL. Details of the memory cell MC will be described later. The address buffer AB takes in an external address signal Address and converts it into predecode signals RA and CA. Predecode signals RA and CA are output to row decoder RD and column decoder CD.

  A data read operation of the memory cell MC will be described. The row decoder RD selects a desired word line RWL based on the predecode signal RA and fixes a non-selected word line RWL to a low potential. The column decoder CD selects a desired bit line RBL based on the predecode signal CA. The memory cell MC connected to the intersection of the selected word line RWL and bit line RBL outputs a read signal to the bit line RBL. The bit line RBL transmits a read signal to the sense amplifier / data output buffer SABF via a switch of the column selector CS. The sense amplifier amplifies the read signal of the memory cell MC and outputs data Dout to the outside of the chip via the data output buffer. Here, the sense amplifier / data output buffer SABF in FIG. 2 is a circuit block provided with a sense amplifier and an output buffer.

  A data write operation to the memory cell MC will be described. The row decoder RD selects a desired word line RWL based on the predecode signal RA and fixes a non-selected word line RWL to a low potential. The input buffer DIB receives the data signal Din input from the outside and outputs it to the column selector CS. Further, the column decoder CD selects desired bit lines RBL and WBL based on the predecode signal CA via the column selector CS. A write data signal based on the input data is transmitted to the selected bit lines RBL and WBL, and the input data is written to the memory cell MC. The external signal chip enable Chip-Enable is a signal that activates the SRAM macro 2 so that it can be accessed. During standby, each block is deactivated so that unnecessary current does not flow. In the present embodiment, there is shown a method for reducing leakage current with respect to the memory cells MC constituting the memory cell array MCA in the SRAM macro 2 illustrated in FIG. 1B.

  FIG. 2 is a circuit diagram showing a configuration of the memory cell MC of the semiconductor device according to the first embodiment. The memory cell MC includes second conductivity type (N) driver transistors M3 and M4, second conductivity type (N) access transistors M5 and M6, first conductivity type (P) load transistors M1 and M2, The second conductivity type (N) leak suppression transistor M10 is used. The leak suppression transistor M10 has a gate connected to the source of the access transistor M6 (storage node SNB), a drain connected to the common source of the driver transistors M3 and M4, and a source connected to the power supply Vss. The access transistor M5 has a drain connected to the read bit line RBL and a gate connected to the read word line RWL. Access transistor M6 has a drain connected to write bit line WBL and a gate connected to write word line WWL.

  In the present embodiment, when the data of the storage node SNT is “1”, the potential on the low potential side (potential of the node NS) applied to the memory cell MC by the leak suppression transistor M10 is increased, and the memory cell MC is Reduce the flowing leakage current. This potential on the low potential side (the potential of the node NS) is autonomously performed in the memory cell MC in response to the write data of the memory cell MC without passing through the control signal. Therefore, the control of the leak suppression transistor M10 as shown in the prior art is unnecessary, the access time is not limited by the control signal, and the control circuit for generating the control signal is also unnecessary. The effect of reducing the leakage current can be obtained not only in non-selected memory cells MC but also in selected memory cells MC. Further, since the word lines for reading and writing are used as the word lines, at the time of the reading operation, one of the paired access transistors M6 maintains the OFF state, and the current discharged from the bit line WBL via the memory cell MC. Does not flow, and the read operation current of the entire memory cell array is reduced.

  Specifically, the memory cell MC is a conventional SRAM memory cell constituted by 6 transistors, which is replaced with an example in which the bit line RBL at the time of reading is constituted by a single end, and further a leakage suppression transistor M10 is added. The load transistors M1 and M2 are PMOS transistors. The other driver transistors M3 and M4, access transistors M5 and M6, and leak suppression transistor M10 are NMOS transistors. The load transistor M1 and the driver transistor M3 constitute an inverter IVt connected with a common drain. The load transistor M2 and the driver transistor M4 also constitute an inverter IVb connected with a common drain. The inputs and outputs of the inverters IVt and IVb form a latch circuit that is cross-coupled to each other, and each output has a complementary relationship. The source of the access transistor M5 is connected to the storage node SNT of the inverter IVt. A read and write word line RWL is connected to the gate of the access transistor M5, and a read and write bit line RBL is connected to the drain. Similarly, the source of access transistor M6 is connected to storage node SNB of inverter IVb. A write word line WWL is connected to the gate of the access transistor M6, and a write bit line WBL is connected to the drain. A power source Vdd is connected to a common source of the load transistors M1 and M2. The drain of the leak suppression transistor M10 is connected to the common source (node NS) of the driver transistors M3 and M4. The power source Vss is connected to the source of the leak suppression transistor M10, and the storage node SNB (source of the access transistor M6) is connected to the gate. The above configuration is preferable as a specific configuration for obtaining the effects of the present embodiment described above.

  Next, the operation of the semiconductor device according to the first embodiment will be described. Here, a writing operation, a holding state, and a reading operation of the memory cell MC will be described with reference to FIG. In the following description, when the storage node SNT stores data “1”, the circuit that suppresses the leakage current flowing through the memory cell MC functions. Therefore, this mode is called “suppression-mode”. To do. In addition, when the storage node SNT stores data “0”, a read current flows from the bit line through the memory cell MC at the time of read access. Therefore, the mode in this state is referred to as Read-Mode.

  First, the case where data “1” is rewritten from the state of data “0” in the storage node SNT in the memory cell MC (when the state is changed to Suppression-Mode) will be described. A precharge circuit (not shown) connected to the bit lines RBL and WBL precharges the bit lines RBL and WBL to the power supply voltage Vdd before the access operation starts. Next, the row decoder RD raises the selected word lines RWL and WWL via a word driver (not shown), and turns on the access transistors M5 and M6. The write buffer outputs write data to the bit lines RBL and WBL according to the input data. The column decoder CD activates the switch of the selected bit line of the column selector CS, and transmits the data sent from the write buffer to the selected bit lines RBL and WBL. When the write data is “1”, the potential of the bit line RBL is set high and the potential of the bit line WBL is set low. As a result, the potential of the storage node SNT in the memory cell MC changes from Low to High, and the potential of the storage node SNB changes from High to Low. That is, the potentials of the storage node SNT and the storage node SNB are rewritten to the potential according to the input data via the bit lines RBL and WBL.

  Thereafter, the rewriting of data stored in the memory cell is completed by setting the selected word line potential to the low potential (Vss potential). In the memory cell MC, when the data of the storage node SNT is kept at “1”, the storage state of the storage node SNB is held at “0”. The gate of leak suppression transistor M10 is a common node with storage node SNB, and leak suppression transistor M10 is turned off. An equivalent circuit of the memory cell is shown in FIGS. 3B and 3C in consideration of a leakage current flowing through the memory cell in this state. If the common source of the driver transistors M3 and M4 is the node NS, the potential of the node NS (and the storage node SNB) can be expressed as Vdd · R10 / (Rmc + R10) using the equivalent element shown in FIG. 3C ( Details will be described later). Here, the equivalent resistance R10 is an equivalent element when the leak suppression transistor M10 is turned off, and the equivalent resistance Rmc is a combined resistance of the equivalent resistance of the inverter IVt and the equivalent resistance of the inverter IVb. That is, the potential Vdd · R10 / (Rmc + R10) of the node NS can be expressed by the equivalent resistance division ratio with respect to the leakage current flowing in the memory cell MC. In this memory cell MC, when data “1” is held in the storage node SNT, the potential on the low potential side (the potential of the node NS) is higher than Vss, and the power supply voltage difference (Vdd−) supplied to the memory cell is increased. Since the potential of the node NS becomes lower than Vdd−Vss, the leakage current flowing in the memory cell MC can be reduced.

  Note that the potential of the node NS (and the storage node SNB) immediately after the data writing operation is lower than Vss. This is because coupling noise is applied to the storage node SNB in response to a drop in the word line potential at the end of writing. Accordingly, since the equivalent resistance R10 (impedance between the node NS and Vss) when the leakage suppression transistor M10 is turned off temporarily increases, the leakage current in the memory cell is further reduced during that period. When the holding period (holding period) becomes longer, the potential of the node NS rises and becomes the value of the above formula. Since the potential change of the node NS affects the leakage current flowing through the memory cell, the dependency of the leakage current on the holding period will be described later.

  Next, a read operation of data “1” will be described. A precharge circuit (not shown) connected to the bit lines RBL and WBL precharges the bit lines RBL and WBL to the power supply voltage Vdd before the access operation starts. The row decoder RD raises only the selected word line RWL (increases to Vdd) via a word driver (arranged in the coder in a row), and sets the access transistors M5 of all the memory cells MC connected to the word line RWL. turn on. The potential of the bit line RBL is High, and in the memory cell storing data “1” in the storage node SNT, the potential of the bit line RBL and the potential of the storage node SNT are Vdd, so that the potential of the word line RWL is Vdd. Even when it rises, access transistor M5 is inactive. Therefore, the potential of the bit line RBL maintains the precharge potential Vdd. Thereafter, the potential of the bit line RBL is amplified by the sense amplifier SABF via the switch in the column selector CS selected by the column decoder CD, and the data is output outside the SRAM macro by the output buffer.

  A case where data “0” is rewritten from the state of data “1” in the memory cell MC (when the state is changed to Read-Mode) will be described. The above-described write operation is the same until the data sent from the write buffer is transmitted to the selected bit lines RBL and WBL after the word line rises from the precharge of the bit line. Due to the write data of the selected bit lines RBL and WBL, the potential of the storage node SNT changes from High to Low, and the potential of the storage node SNB changes from Low to High. That is, the potentials of the storage node SNT and the storage node SNB are rewritten to the potential according to the input data via the bit lines RBL and WBL. After that, the potential of the word lines RWL and WWL is set to the low potential (Vss potential), so that the rewriting of the storage data in the memory cell is completed.

  In the memory cell MC, when the data of the storage nodes SNT and SNB are “0” and “1”, respectively, the potential of the storage node SNB is the Vdd potential, and the leak suppression transistor M10 and the driver transistor M3 are on. The potentials of the storage node SNT and the node NS become the Vss potential via the driver transistor M3 and the leak suppression transistor M10.

  Next, a read operation of data “0” will be described. The operation from the precharge of the bit line to the rise of the word line is the same as the above read operation. The charge of the bit line RBL is discharged to Vss through the driver transistor M3 and the leak suppression transistor M10 in the memory cell MC when the word line rises. Accordingly, the potential of the bit line RBL drops, and the drop potential at this time becomes a read signal. The subsequent operation is the same as the above read operation, and the description thereof is omitted here.

  The discharge speed of the read signal is slower than that of a conventional memory cell using six transistors. This discharge speed is related to the access time of the read operation. When the discharge speed is slow, it is necessary to delay the timing for starting the sense amplifier, which causes the access time to be delayed. This is because it is necessary to take a large read signal from the memory cell MC in terms of sensitivity of the sense amplifier. As described above, the discharge rate of the bit line as a read signal is an important value as a characteristic of the SRAM macro, and the results of examination by computer simulation using HSPICE will be described later.

The mechanism and effect of the memory cell according to this embodiment will be described.
The read signal appearing on the bit line RBL is such that when the data stored in the storage node SNT is “0” (Low), the charge on the bit line RBL is discharged to Vss via the driver transistor M3 and the leak suppression transistor M10. It occurs in. When the data stored in the storage node SNT is “1” (High), even if the potential of the bit line RBL and the storage node SNT are High and the gate of the access transistor M5 rises to High, the access transistor M5 The off state (inactive state) is maintained. Considering these two operating states, it can be seen that the voltage change occurs only on the bit line when the storage node SNT is “0”. Therefore, when the storage node SNT holds data “0”, a speed for discharging the charged charge of the bit line RBL is required, so that a sufficient bias voltage is applied between the gate and the source of the driver transistor M3. There is a need. In other words, it can be said that the potential of the node NS needs to be set to a potential sufficiently close to the ground potential Vss. When the storage node SNT is “1”, if the gate and the source of the driver transistor M3 are at the same potential, the potential of the storage node SNT can be maintained at the high potential. This means that the potential of the storage node SNT can be maintained at a high potential regardless of the potential of the node NS. On the other hand, it is known that increasing the discharge speed of the bit line at the time of reading (increasing the read current) and suppressing the leakage current in the memory cell MC are in a trade-off relationship. Specifically, it is known that when the gate widths of the driver transistors M3 and M4 are increased in order to increase the readout discharge current, the leakage current increases on the other hand. This is because the method of simply increasing or decreasing the sizes of the driver transistors M3 and M4 cannot solve both the increase (or maintenance) of the read current and the suppression of the leakage current at the same time.

  Assume that data “0” is stored in storage node SNT and data “1” is stored in storage node SNB (Read-Mode) in memory cell MC shown in FIG. A bias potential Vdd is applied to the storage node SNB, and a potential difference of (Vdd−Vss) is applied between the gate and the source of the leak suppression transistor M10. The leak suppression transistor M10 is in an on state, and the potential of the node NS is Vss. A potential difference of (Vdd−Vss) is applied between the gate and source of the driver transistor M3. The potential of the storage node SNT is held at Vss through the driver transistor M3 and the leak suppression transistor M10.

  It is assumed that data “1” is stored in storage node SNT and data “0” is stored in storage node SNB (suppression mode). The bias potential applied to storage node SNT is Vdd. Further, the bias potential applied to the storage node SNB is represented by a division ratio in which the leak current flowing in the memory cell MC is represented by an equivalent resistance because the leak suppression transistor M10 is in the off state. 3A to 3C are diagrams for explaining the potential state at this time. 3A is a circuit showing the memory cell MC, and FIGS. 3B and 3C show the memory cell MC in the suppression mode by an equivalent circuit.

  As shown in FIG. 3A, the storage node SNT holds High (Vdd potential), and the driver transistor M4 is in an on state (active state). Therefore, since the node NS and the storage node SNB are common, the leak suppression transistor M10 forms a diode connection. The driver transistor M3 and the load transistor M2 are in an off state. In the inverters IVt and IVb, a leakage current flows from Vdd to Vss through the transistors M3 and M2. In the memory cell MC, the state of the leakage current can be represented by an equivalent circuit replaced with a resistance element. As shown in FIG. 3B, resistors Rivt and Rivb are obtained by replacing inverters IVt and IVb with equivalent resistors, respectively. The resistor R10 is obtained by replacing the leak suppression transistor M10 with an equivalent resistor. The diode D10 indicates that the leak suppression transistor M10 forms a diode connection, and is replaced with an equivalent element. FIG. 3C is obtained by replacing the equivalent resistances Rivt and Rivb of FIG. 3B with a combined resistance Rmc. Based on FIG. 3C, the potential Vns of the node NS in the suppression mode can be expressed by Vdd · R10 / (Rmc + R10). The potential Vns of the node NS is higher than Vss by ΔVns = Vdd · R10 / (Rmc + R10). However, the potential Vns of the node NS at this time is established when it is lower than the threshold voltage Vth10 of the leak suppression transistor M10. When the potential Vns of the node NS is higher than the threshold voltage Vth10 of the leak suppression transistor M10, the potential Vns of the node NS is clamped by the diode D10 and becomes the threshold voltage Vth10 of the leak suppression transistor M10.

  As described above, when the potential of the storage node SNT is High (Vdd) and the potential of the storage node SNB is Low (potential of the node NS) (in the suppression mode), the potential Vns of the node NS is higher than the Vss by the above ΔVns. Biased. As a result, the leakage current imc flowing through the memory cell MC is imc = Vdd / (Rmc + R10). Here, in the conventional memory cell that does not use the leakage suppression transistor M10, the leakage current icon is icon = Vdd / Rmc. Therefore, the leak current (imc) flowing through the memory cell MC is reduced as compared with the conventional leak current (icon).

  Here, it is more preferable that the absolute value of the threshold voltage of the leak suppression transistor M10 is lower than the absolute value of the threshold voltage of the load transistors M1 and M2. As described above, considering the case where the potential Vns of the node NS is clamped by the diode D10 and becomes the threshold voltage Vth10 of the leak suppression transistor M10, the bias voltage applied between the gate and the source of the load transistor M1 is sufficiently set. This is because the ON resistance of the load transistor M1 is reduced by increasing the resistance. Thereby, the tolerance with respect to the noise in the storage node SNT can be made high.

  However, the potential of the node NS is shown as a negligible value with almost no leakage current flowing from the bit line WBL via the access transistor M6. A method for reducing the leakage current through the access transistor M6 will be described later. Note that the leakage current through the access transistor such as the access transistor M6 is also ignored in the other embodiments.

  FIG. 4 shows the retention cycle of the average leakage current Iddmc flowing in the memory cell when data “1” (Vdd) is written to the storage node SNT of the memory cell and the storage state (the potentials of the word lines RWL and WWL is Vss). It is a graph which shows dependence. This figure uses values calculated by computer simulation using HSPICE. The horizontal axis indicates the number of cycles in the holding state after data writing, and the vertical axis indicates the average leakage current Iddmc (nA) in logarithm. In this figure, white triangles indicate that the device characteristic conditions of the transistors constituting the memory cell MC of the present embodiment are NMOS transistor: Fast / PMOS transistor: Fast (hereinafter referred to as “FF condition”), and Vdd = The result is 1.2 V (hereinafter referred to as “1.2 V condition”). The black triangle is the result when a conventional 6-transistor memory cell (hereinafter referred to as a “conventional cell”) has an FF condition and a 1.2 V condition. Open circles indicate that the device characteristic conditions of the transistors constituting the memory cell MC are NMOS transistor: Center / PMOS transistor: Center (hereinafter referred to as “CC condition”), and Vdd = 1.1 V (hereinafter referred to as “1. 1V condition ”). A black circle is a result in the case where the CC condition is set to 1.1 V in the conventional cell. In the white squares, the conditions of the device characteristics of the transistors constituting the memory cell MC are NMOS transistor: Slow / PMOS transistor: Slow (hereinafter referred to as “SS condition”), and Vdd = 1.0 V (hereinafter referred to as “1.0 V”). It is a result when it is referred to as “condition”. The black squares are the results when the SS condition is used and the 1.0 V condition is used in the conventional cell.

  As shown in FIG. 4, in the suppression-mode, the leak current (Idddmc) increases in the order of the SS condition, the CC condition, and the FF condition. In addition, the memory cell MC (FIG. 2) of the present embodiment has a 29.7% reduction under the FF condition and a 38.9% reduction under the CC condition, compared with the leakage current of the conventional cell (6 transistors). A reduction of 31.5% can be achieved under SS conditions. However, these values are maintained in the retained state after the data write operation, and the leak current values at the 50th cycle are compared. As described above, the memory cell MC of the present embodiment has an effect of reducing the leakage current in the suppression-mode compared to the conventional cell.

  As described above, in the suppression-mode, the leakage current of the memory cell MC is reduced as compared with the leakage current of the conventional cell. However, during read-mode, the leak current of the memory cell MC is almost the same as the leak current of the conventional cell, and there is no effect of reducing the leak current. In other words, in the present embodiment, the leakage current flowing through the memory cell MC depends on the data stored in the memory cell. In the case where there are a large number of memory cells MC storing data “1” among the plurality of memory cells MC configuring the memory cell array MCA, the effect of reducing the leakage current is increased. On the other hand, when there are a large number of memory cells storing data “0”, the effect of reducing the leakage current is reduced.

  5 to 9 are graphs showing the correlation between the leakage current of all the memory cells in the memory cell array and the distribution ratio of data “1”. These figures are calculated by computer simulation using HSPICE. Each graph shows the ratio of the number of memory cells that store data “1” (the remaining memory cells MC that store data “0”) and the memory cell array MCA having 100-bit memory cells MC. The correlation with the leakage current is shown. Here, the vertical axis indicates the total leakage current (nA) of all memory cells, and the horizontal axis indicates the distribution ratio (%) of data “1” in the memory cell array MCA (memory cells storing data “1”). Number ratio). FIG. 5 shows a case of 1.2V condition and FF condition. FIG. 6 shows a case of 1.1V condition and CC condition. FIG. 7 shows the case of the SS condition under the 1.0V condition. FIG. 8 shows a case of 1.2V condition and FS condition. FIG. 9 shows the case of the SF condition under the 1.2V condition. In each figure, a white circle indicates the memory cell MC of the present embodiment at a temperature of 125 ° C. (hereinafter referred to as “125 ° C. condition”), and a dotted line indicates a conventional cell under the condition of 125 ° C. A white triangle indicates the memory cell MC of the present embodiment at a temperature of 75 ° C. (hereinafter referred to as “75 ° C. condition”), and a broken line (short) indicates a conventional cell under the 75 ° C. condition. A white square indicates the memory cell MC of the present embodiment at a temperature of 40 ° C. (hereinafter referred to as “40 ° C. condition”), and a broken line (long) indicates a conventional cell under the 40 ° C. condition. A white diamond indicates the memory cell MC of the present embodiment at a temperature of 25 ° C. (hereinafter referred to as “25 ° C. condition”), and practice indicates a conventional cell under a 25 ° C. condition.

When the memory cell MC of the present embodiment and the conventional cell are compared under the same conditions, the following can be understood.
As shown in FIG. 5, under the FF condition, the memory cells MC storing data “1” are 6% or more, 16% or more, and 32% under the 125 ° C. condition, 75 ° C. condition, 40 ° C. condition, or 25 ° C. condition, respectively. As described above, if it is 40% or more, the leakage current can be reduced as compared with the conventional cell. Further, as shown in FIG. 6, in the CC condition, the memory cells MC storing the data “1” in the 125 ° C., 75 ° C., 40 ° C., and 25 ° C. conditions are 23% or more and 45% or more, respectively. If it is 61% or more and 61% or more, the leakage current can be reduced as compared with the conventional cell. Further, as shown in FIG. 7, under the SS condition, the memory cells MC storing data “1” are 45% or more, 70% or more under the 125 ° C., 75 ° C., 40 ° C. or 25 ° C. condition, respectively. If it is 77% or more and 77% or more, the leakage current can be reduced as compared with the conventional cell. Further, as shown in FIG. 8, in the FS condition, the memory cells MC storing data “1” are 13% or more, 33% or more, respectively, in the 125 ° C., 75 ° C., 40 ° C., or 25 ° C. conditions. If it is 52% or more and 52% or more, the leakage current can be reduced as compared with the conventional cell. Further, as shown in FIG. 9, in the SF condition, the memory cells MC storing data “1” are 4% or more, 10% or more in the 125 ° C. condition, 75 ° C. condition, 40 ° C. condition, or 25 ° C. condition, respectively. If it is 19% or more and 19% or more, the leakage current can be reduced as compared with the conventional cell.

Here, when the temperature dependence of the leakage current is examined, the following can be understood.
As shown in FIG. 5 to FIG. 9, the leakage current is dependent on temperature. As shown in FIG. 5, in the case of 1.2 V condition and FF condition, the temperature is 125 ° C. (125 ° C. condition). Overall leakage current is maximized. It can be seen that as the temperature decreases to 75 ° C., 40 ° C., and 25 ° C. (75 ° C., 40 ° C., and 25 ° C., respectively), the overall leakage current also decreases.

  Further, in the correlation between the distribution ratio of the data “1” in the memory cell array MCA and the leakage current, it can be seen that the dependency of the distribution ratio of the data “1” decreases as the temperature decreases. As shown in FIG. 5, in the case of 1.2V condition and FF condition, if the memory cell MC of data “1” (suppression-mode) is 6% or more in the 125 ° C. condition, it is compared with the conventional cell. Leakage current can be suppressed. In order to reduce the leakage current as compared with the conventional cell, the ratio of the memory cell MC of the storage data “1” is reduced as the temperature decreases to 125 ° C., 75 ° C., 40 ° C., 25 ° C. 16% or more, 32% or more, or 40% or more. Considering the variation in device models, it is necessary to refer to device conditions other than the FF condition, but when compared with the FF condition (FIG. 5) where the leakage current is maximum, the CC condition (FIG. 6) and the FS condition ( 8) and SF condition (FIG. 9), the leakage current is one order lower, and SS condition (FIG. 7) is two orders of magnitude lower (both compared under 125 ° C. condition). For devices other than these FF conditions, it is clear that the leakage current is sufficiently low without considering the distribution ratio of data “1”. Among them, the conditions under which a large leakage current flows are about 720 nA of the SF condition at 125 ° C. and about 460 nA of the FS condition at 125 ° C. However, if the distribution ratio of the storage data “1” is 4% or more under the SF condition, the leakage current can be reduced as compared with the conventional cell. Further, even if the distribution ratio of the stored data “1” is 13% or more even under the FS condition, the leakage current can be reduced as compared with the conventional cell.

  If the data “0” and “1” stored in the memory cell array are assumed to be random data, the probability that “1” will be written to the memory cell in the storage data in which 1-bit data is expressed in binary is Expected to be 50%. The memory capacity of an SRAM macro mounted on a semiconductor chip of SoC (System On Chip) is a memory macro of several kilos to several tens of megabits, and the number of SRAM macros mounted on one chip is several hundred to several thousand. . Therefore, even if the data stored for each memory macro is biased, the bias of the stored data is leveled over the entire chip, and the probability of the memory cell written to the stored data “1” is close to 50%. Therefore, in most cases in FIGS. 5 to 9, the effect of reducing the leakage current can be obtained. In any case, the FF condition that maximizes the leakage current has an effect of reducing the leakage current as compared with the conventional cell.

  FIG. 10 is a graph showing the retention cycle dependency of the total leakage current Idd flowing through the memory cell array. This figure is calculated by computer simulation using HSPICE. The horizontal axis indicates the number of cycles in the holding state after data writing, and the vertical axis indicates the total average leakage current Idd (nA). In this figure, the memory cells MC of the present embodiment are indicated by triangles, circles, and square marks, the triangles are 1.2V conditions and FF conditions, and circles are 1.1V conditions and CC conditions. The squares show the results in the case of the 1.0 V condition and the SS condition, respectively. Region A is a range in which the leakage current is larger than the leakage current of the conventional cell under the FF condition. Specifically, the range is about 33 nA or more. Region B is a range where the leakage current is larger than the leakage current of the conventional cell under CC conditions. Specifically, the range is about 2 nA or more.

  Since the value of the leakage current differs depending on the distribution rate of the data “1” in the memory cell array MCA, it is assumed here that the distribution rate of the data “1” is 50% (the distribution rate of the data “1” is also 50%). doing. Specifically, average leakage current Iddmc and average leakage current Iddrd were measured. However, the average leakage current Iddmc is an average leakage current that flows through the Vdd power supply when “1” (Vdd) is written to the storage node SNT of the memory cell MC and the holding state (the potential of the word line is Vss). The average leakage current Iddrd is an average leakage current that flows through the Vdd power supply when “0” (Vss) is written to the storage node SNT and the storage node SNT is brought into the holding state. In the graph of FIG. 10, the total value (Idd) of the average leakage current Iddmc and the average leakage current Iddrd is plotted by the number of holding cycles.

  As shown in FIG. 10, the leakage current (Idd) increases in the order of SS condition, CC condition, and FF condition. Further, as remarkable in the FF condition, the leak current up to about 14 cycles after data writing is lower than that after 15 cycles when the leak current is saturated. As described in the explanation of the operation of the present embodiment, this is due to the following reason. The potential of the storage node SNB after data writing is temporarily lower than Vss due to coupling noise due to the falling potential of the word lines RWL and WWL at the end of the write operation. For this reason, a negative potential is applied as the gate potential of the leakage suppression transistor M10, the resistance value when the leakage suppression transistor M10 is turned off is increased, and the potential of the node NS is also increased. Therefore, the bias voltage (Vdd-NS potential) applied to the memory cell MC is reduced, and the leakage current flowing through the memory cell MC is suppressed. After data writing, the potentials of the node NS and the storage node SNB gradually increase, become constant at Vdd · R10 / (Rmc + R10), and the leakage current (Idd) is also saturated.

  As shown in FIG. 10, when the leakage current is viewed based on the FF condition, the value is two orders of magnitude lower in the CC condition and three orders of magnitude lower in the SS condition (not shown in FIG. 10, but the FS condition (1. 2V condition) and SF condition (1.2V condition) are also one order of magnitude lower). For this reason, the condition for the maximum leakage current is the FF condition (1.2 V condition). Further, from the comparison with the region A, under the FF condition (1.2 V condition) of the present embodiment, the leakage current is reduced by 14% compared to the conventional cell. Further, from the comparison with the region B, under the CC condition (1.1V condition) of the present embodiment, the leakage current is reduced by 10% compared to the conventional cell.

  FIG. 25 to FIG. 28 are graphs showing cycle dependency of leakage current in each control method (including third and fourth embodiments described later) (however, FIG. 27 and FIG. 28 are partially shown in FIG. 27 and FIG. 28). Expanding). This figure is a plot of values calculated by computer simulation using HSPICE. The horizontal axis represents the number of cycles in which the retained state is maintained after data writing, and the vertical axis represents the total average leakage current Idd (nA). As in FIG. 10, assuming that the distribution ratio of data “1” in the memory cell array MCA is 50% (the distribution ratio of data “0” is also 50%), the average leakage current Idd (average leakage current Iddmc and The total value of the average leakage current Iddrd) is plotted by the number of holding cycles. In this figure, the black squares indicate the case of the 1.2V condition and the FF condition in the first embodiment (hereinafter also referred to as “Vss control” or “Vss-Cntrl”). The black circle is the case of the FF condition under the 1.2 V condition in the third embodiment (hereinafter also referred to as “Vdd control” or “Vdd-Cntrl”). The black triangle is the case of the FF condition under the 1.2 V condition in the fourth embodiment (hereinafter also referred to as “Vss + Vdd control” or “Vss + Vdd−Cntrl”). A white square is a case of 1.1V condition and CC condition in the first embodiment. A white circle is a case of 1.1V condition and CC condition in the third embodiment. A white triangle is a case of 1.1V condition and CC condition in the fourth embodiment. The white diamond is the case in the SS condition under the 1.0 V condition in the first embodiment. The cross mark is the case in the SS condition under the 1.0V condition in the third embodiment. The white inverted triangle is the case in the SS condition under the 1.0V condition in the fourth embodiment. Region C is a range in which the leakage current is larger than the leakage current of the conventional cell under the FF condition. 25 to 28 show the cases of 125 ° C. condition, 75 ° C. condition, 40 ° C. condition, and 25 ° C. condition, respectively.

  As shown by the black squares in FIG. 25, the leakage current is reduced by 14% in the 1.2V condition, the FF condition, and the 125 ° C. condition as compared with the conventional cell. Further, as shown by the black square in FIG. 26, the leakage current is reduced by 13.6% under the 1.2V condition, the FF condition and the 75 ° C. condition as compared with the conventional cell. In addition, as shown by the black squares in FIG. 27, the leakage current is reduced by 14.1% under the 1.2V condition, the FF condition, and the 40 ° C. condition as compared with the conventional cell. Further, as shown by the black squares in FIG. 28, the leakage current is reduced by 9.0% under the 1.2V condition, the FF condition, and the 25 ° C. condition as compared with the conventional cell.

  As described above, in the present embodiment, the leakage current value of the memory cell array MCA depends on the distribution ratio of data stored in the memory cell array. However, the correlation between the distribution ratio of the stored data “1” and the leakage current, the variation and temperature dependence of the devices exhibiting the above characteristics, the probability that the data “1” is stored in the memory cell, and the SoC semiconductor chip. Although the leak current depends on the number of memory cells MC to be used, the memory cell MC of this embodiment has an effect of reducing the leak current more than the conventional cell under the same conditions.

  Next, the delay time of the read signal from the rise of the word line to the output of the read signal will be described. FIG. 33 is a table showing the delay time of the read signal from the rise of the word line to the output of the read signal (including second to fifth embodiments described later). This figure is based on the result calculated by computer simulation using HSPICE. Here, the definition of the delay time of the read signal is required from the time when the potential of the word line RWL rises to 50% of the amplitude (Vdd-Vss potential difference) to the time when the potential of the bit line RBL falls to 50%. It's time. “Temperature” indicates a temperature condition. “CC, 1.1V” indicates a CC condition with a 1.1V condition. “FF, 1.2V” indicates the FF condition under the 1.2V condition. “SS, 1.0V” indicates the SS condition under the 1.0V condition. “Conventional cell” refers to a conventional memory cell. “Vss control” indicates “Vss-Cntrl”, that is, the first and second embodiments. “Vss + Vdd control” indicates “Vss + Vdd−Cntrl”, that is, the fourth and fifth embodiments. “Vdd control” indicates “Vdd-Cntrl”, that is, the third embodiment. The unit of the numerical value is psec. It is. In each control method, the delay time was calculated in steps of 10 ° C. from 25 ° C. to 125 ° C. using the operating temperature as a parameter.

  Under CC conditions, 74.0 to 75.9 psec. The delay is 88.4 to 91.5 psec. In the first embodiment (Vss control). Is the delay. Under the FF condition, 47.1-48.2 psec. In the first embodiment, the delay is 54.0 to 55.8 psec. Is the delay. In the SS condition, the delay is 142.7 to 143.1 psec in the conventional cell, and 183.9 to 185.2 psec. In the first embodiment. Is the delay.

  FIG. 34 is a graph showing the increase rate of the delay time in each control method based on the delay time of the conventional cell with respect to the result of FIG. 33 (second, fourth, and fifth embodiments described later). including). However, eleven bar graphs of each control method indicate eleven operating temperature conditions in steps of 10 ° C. from the 125 ° C. condition to the 25 ° C. condition from the left side to the right side. Under CC conditions for Vss control (Vss control “CC”), a delay increase of about 17% is recognized as compared with the conventional cell. Further, in the FF condition for Vss control (Vss control “FF”), a delay increase of about 14% is recognized as compared with the conventional cell. Further, in the SS condition of Vss control (Vss control “SS”), a delay increase of about 23% is recognized as compared with the conventional cell. Further, in the FS condition and SF condition (Vss control “FS”, “SF”) of Vss control, the same tendency as the FF condition and CC condition of Vss control is recognized.

Next, a method for reducing leakage current flowing from the bit line WBL into the memory cell during the holding period will be described.
11A to 11C are diagrams illustrating a method for reducing a leak current flowing into a memory cell during a holding period. Among these, FIG. 11A is a circuit diagram when the potential of the bit line WBL is fixed to Vss. FIG. 11B is a circuit diagram in the case where the potential of the bit line WBL is fixed to Vdd. FIG. 11C is a graph showing a potential state when the storage node SNB is set to a low potential. A method for reducing the leak current flowing into the memory cell during the holding period by setting the potential of the bit line WBL in the holding period to an appropriate state will be discussed below.

  First, consider the case where the potential of the bit line WBL is set to Vss as shown in FIG. 11A. During the holding period, the potential of the word line WWL is maintained at Low (Vss). When a potential of High (Vdd) is stored in storage node SNB of memory cell MC, a leak current (subthreshold current) flows from access transistor M6 to bit line WBL. On the other hand, when data having a low (Vns = Vdd · R10 / (Rmc + R10)) potential is stored in the storage node SNB, almost no leakage current flows. This is because the leak suppression transistor M10 and the access transistor M6 are composed of the same device.

  Next, consider the case where the potential of the bit line WBL is set to Vdd as shown in FIG. 11B. When data having a High (Vdd) potential is stored in the storage node SNB of the memory cell MC during the holding period, the source and drain potentials of the access transistor M6 are the same. Therefore, the access transistor M6 is in an off state, and no leak current (subthreshold current) flows between the memory cell MC and the bit line WBL. On the other hand, when data having a Low (Vns = Vdd · R10 / (Rmc + R10)) potential is stored in the storage node SNB, as shown in FIG. 11C, the Low (Vss) potential of the word line WWL is equal to the storage node SNB. And the potential of the bit line WBL, the leakage current hardly flows between the memory cell MC and the bit line WBL through the access transistor M6. From the above results, the leakage current flowing between the bit line WBL and the memory cell MC can be suppressed by holding the potential of the bit line WBL at a potential of Vdd or higher during the holding period.

  Further, since the potential state of the bit line WBL does not change even during the readout period, the leakage current between the Mori cell MC and the bit line WBL is reduced by holding the potential of the bit line WBL during the readout operation at a potential of Vdd or higher. Reduced.

  FIG. 12 is a diagram for explaining a method of reducing a leak current flowing from the bit line RBL into the memory cell MC during the holding period. In the drawing, two memory cells MHigh and MClow connected on the bit lines RBL and WBL are shown. The memory cells MHigh and MClow are connected to the same bit line RBL via access transistors M05 and M15, respectively. Here, a method for reducing the leakage current flowing between a plurality of memory cells in the holding period by setting the potential of the bit line RBL to an appropriate state will be discussed below.

  First, it is assumed that data “1” (High) is stored in the storage node SN0T of the memory cell MHigh and data “0” (Low) is stored in the storage node SN1T of the memory cell MClow. When the potential of the bit line RBL is set to Vss, a leak current flows to the Vss potential of the bit line RBL via the storage node SN0T via the access transistor M05 of the memory cell MHigh. On the other hand, when the potential of the bit line RBL is set to Vdd, a leakage current flows from the bit line RBL to Vss through the storage node SN1T. Thus, it can be seen that leakage current flows under the above two assumptions. Under these assumptions, when the number of holding cycles increases, the leakage current continues to flow for the number of cycles during the holding period.

Here, consider that the bit line RBL is in a floating state.
When floating, a path of a leak current that flows from Vdd of the memory cell MHigh to Vss of the memory cell MClow through the access transistor M05 and the bit line RBL is formed. This leak current is equivalent to a value calculated from the equivalent resistance of the load transistor M01, access and transistor M05, access transistor M15, driver transistor M13, and leak suppression transistor M110, and the wiring resistance of the bit line. It can also be said that an intermediate potential is generated between Vdd and Vss in the bit line RBL. For example, in the SRAM macro 2 shown in FIG. 1B, it is assumed that 16 memory cells MC are arranged in the Y direction, and data “1” and data “0” are stored repeatedly. Under the FF condition and 125 ° C. condition, a potential of about 92 mV is generated in the floating bit line RBL. For this reason, the gate potential (Vss) of the access transistor M05 of the memory cell MHigh is lower than the source potential (the potential 92 mV of the bit line RBL), and the leakage current to the bit line RBL is reduced. As described above, by setting the bit line RBL in the floating state in the holding period, leakage current flowing between a plurality of memory cells connected to the same bit line can be reduced. This technique can be applied not only to the memory cell of the present embodiment but also to a memory cell to which a leak suppression transistor M11 (third embodiment: described later) is connected.

  As described above, the leakage current flowing between the bit line WBL and the memory cell MC can be suppressed by setting the potential of the bit line WBL to Vdd in the reading period and the holding period. In addition, the leakage current flowing between the plurality of memory cells MC connected on the same bit line RBL can be suppressed by setting the potential of the bit line RBL to the floating state in the holding period. Further, during the holding period, the leakage current can be further suppressed by performing the above-described state simultaneously.

Next, the layout of the memory cell MC in FIG. 2 will be described.
FIG. 13 is a schematic plan view showing an example of the layout of the memory cell according to the present embodiment. Each of the MOS transistors M1 to M6 and M10 in the figure corresponds to each transistor constituting the memory cell shown in FIG. The layout of the conventional cell is a region obtained by removing the NMOS transistor of M10 from the layout of FIG. In other words, in the present embodiment, M10 is added in the vertical direction (upward direction) in the drawing. For this reason, the layout area is longer by one NMOS transistor in the vertical direction than the conventional cell.

  As described above, by using the memory cell MC of the present embodiment, the leakage current in the memory cell array during the data holding period can be reduced as compared with the conventional cell. In addition, in this embodiment, since leakage current reduction can be controlled without using a special control signal, a leakage current control circuit is not added, and there is no need to design the timing of the control signal. Further, even in the memory cell array MCA at the time of access, in the non-selected memory cell, the leakage current is reduced depending on the data to be stored, so that the leakage current of the entire memory cell array MCA can be reduced. Furthermore, since the read bit line is single-ended, there is no discharge current from one of the paired bit lines WBL during the read operation, and the current consumption during the read operation can be reduced.

  In the present embodiment, the leakage current and read operation current flowing through the memory cell MC can be reduced as compared with the conventional cell. Therefore, the power consumption of the system LSI mounting this memory cell is suppressed. In particular, in a mobile product having a battery, the operating time of the system can be extended due to the effect of suppressing power consumption. Further, it is possible to suppress an increase in the temperature of the LSI accompanying an increase in current consumption, and there is an effect of suppressing malfunction and stop of the system LSI due to thermal runaway. Furthermore, in the system using the LSI in which the present embodiment is mounted, the malfunction and stop can be suppressed, so that the reliability of the entire system is improved.

(Second Embodiment)
A configuration of the semiconductor device according to the second embodiment will be described. The SRAM macro 2 of the first embodiment described above is different from the SRAM macro 2 of the present embodiment in the following points. The SRAM macro 2 of the first embodiment described above has separate word lines (word line RWL and word line WWL) for read operation and write operation. On the other hand, the SRAM macro 2 of the present embodiment has only a common word line WL. Accordingly, the SRAM macro 2 of the present embodiment is different from the SRAM macro 2 of the first embodiment in that the access transistors M5 and M6 are controlled by the common word line WL. Hereinafter, the above-described differences will be mainly described.

  FIG. 14 is a circuit diagram showing a configuration of the memory cell MC of the semiconductor device according to the second embodiment. The memory cell MC of the present embodiment is the same as that of the first embodiment except that the gates of the access transistors M5 and M6 are connected to a common word line WL. Accordingly, on / off of the access transistors M5 and M6 is controlled corresponding to the selection / non-selection signal of the word line WL.

  Similarly to the first embodiment, in this embodiment, when the data of the storage node SNT is “1”, the potential of the node NS is increased, thereby reducing the leakage current flowing in the memory cell MC. Similarly to the first embodiment, the leakage suppression transistor M10 is autonomously performed in response to the stored data of the memory cell MC without passing through a control signal. Therefore, the access time is not delayed without being limited by a special control signal. Further, since a circuit for generating a control signal is unnecessary, power consumption is not increased. Further, the effect of reducing the leakage current can be similarly obtained in the accessed memory cell array MCA. In this embodiment, since the read and write word lines are shared, it can be configured by arranging one set of word decoders and word drivers for each word line, compared with the first embodiment. There is no additional word driver, and the chip area and power consumption are not increased. However, the read current when the storage node SNB is “0” is the current consumption compared to the first embodiment because the charge of one of the paired bit lines WBL is discharged through the storage node SNB. Has the disadvantage of increasing By the way, it has been found that the present memory cell has a characteristic to suppress the discharge current in the circuit configuration. This point will be mainly described below.

  Since the writing operation and the holding state in this embodiment are the same as those in the first embodiment, description thereof is omitted.

  A read operation in which the data of the storage node SNT is “1” and the data of the storage node SNB is “0” (suppression-mode) will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. However, the word lines RWL and WWL operate as the common word line WL. The selected common word line WL is raised (increased to Vdd), and the access transistors M5 and M6 of all the memory cells connected to the word line are turned on. As a result, since the potential of the bit line RBL and the potential of the storage node SNT are High (Vdd) potential, the access transistor M5 is turned off (inactive state), and the potential of the bit line RBL does not change. This is the same as in the first embodiment. On the other hand, the access transistor M6 is in the on state, and the storage node SNB of the memory cell MC is Low, so that the charge of the bit line WBL is discharged, and the potential of the bit line WBL decreases. A current flows from the bit line WBL toward Vss in the memory cell MC, and the potentials of the storage node SNB and the node NS rise. Since the leak suppression transistor M10 at this time has a diode-connected configuration, the potential of the node NS is clamped by the threshold voltage Vth10 of the leak suppression transistor M10. For this reason, since the potential of the node NS does not fall below the threshold voltage Vth10, the bit line current is not completely discharged to the Vss potential, and the read operation current in the bit line WBL is reduced.

  Next, a read operation of data “0” (Read-Mode) will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. However, the word lines RWL and WWL operate as the common word line WL. By raising the selected common word line WL (raising it to Vdd), the access transistors M5 and M6 of all the memory cells connected to the word line are turned on. As a result, the charge on the bit line RBL is discharged to Vss via the storage node SNT in the memory cell MC. On the other hand, the storage node SNB of the memory cell MC is at a High (Vdd) potential, and the access transistor M6 is in an off state (inactive state) even when the potential of the word line WL rises to Vdd. Therefore, the potential of the bit line WBL does not change.

The mechanism and effect of the memory cell according to this embodiment will be described.
The mechanism for suppressing the leakage current of this embodiment is the same as that of the first embodiment, and a description thereof will be omitted. Also in this embodiment, the leakage current in the holding period can be reduced as in the first embodiment. In the holding period, in both cases of the present embodiment and the first embodiment, when the storage node SNT is High (Vdd potential), the potential of the common node NS is made higher than Vss due to the effect of the leak suppression transistor M10. This is to make it higher.

In addition, the mechanism and effects of the memory cell according to the present embodiment are as follows.
As described above, the charge of the bit line WBL is discharged to Vss through the memory cell MC with the rise of the word line WL in the read operation period during the suppression-mode. The discharge current of the bit line WBL wastes unnecessary current for reading the storage data of the memory cell MC, and increases the power of the access operation. However, in the present embodiment, the leak suppression transistor M10 in the memory cell MC has a diode connection configuration during the suppression-mode. Therefore, the charge of the bit line WBL during the read operation is not completely discharged, and there is an effect of suppressing current consumption compared to the conventional cell. The specific mechanism is as follows.

  FIG. 15 is a diagram for explaining the effect of suppressing the bit line current flowing from the bit line WBL to the memory cell during the read operation. The storage node SNT at the time of the suppression-mode stores data whose potential is High (Vdd). As a result, the driver transistor M4 is in the on state, and the gate and drain of the leak suppression transistor M10 become a common node. That is, the leak suppression transistor M10 is an element equivalent to a diode that clamps the node NS with the threshold voltage. In the holding period in which the potential of the word line WL is Low, the potential of the node NS can be represented by a ratio potential (Vdd · R10 / (Rmc + R10) in which the leakage current is replaced with an equivalent resistance. Is turned on, the electric charge charged in the bit line WBL flows toward Vss, the potential of the node NS rises, and the leak suppression transistor M10 functions as a diode. On the other hand, the node NS rises to the clamp potential due to the effect of the diode that the leak suppression transistor M10 functions, so that the fall potential of the bit line WBL never falls below the clamp potential. The storage node SNB also rises in the potential of the node NS. In both cases, the potential rises and the access transistor M6 is subjected to the substrate effect and the threshold voltage rises to the off state (inactive state), causing the discharge current of the bit line WBL not to be completely discharged, and the memory cell array. In the entire MCA, the operating current during the read operation is reduced as compared with the conventional cell.

  FIG. 16 is a table showing an example of the effect of suppressing the read current of the bit line WBL under each device condition. This figure describes values calculated by computer simulation using HSPICE. Here, the conditions of the memory cell MC are 1.1V condition and CC condition, 1.2V condition and FF condition, 1.0V condition and SS condition. However, the temperature conditions are all 125 ° C. The discharge current flowing from the bit line WBL is an average current flowing into Vss of the memory cell in the period from the start of rising of the word line WL to the completion of falling. As shown in the table of FIG. 16, in the 1.1V condition and the CC condition, the conventional cell has about 7.9 μA, and the present embodiment (second embodiment) has 1.6 μA, and the reduction rate is about 80%. It is. In the 1.2V condition and the FF condition, the conventional cell has a value of about 8.2 μA and the present embodiment has a value of 5.0 μA, and the reduction rate is about 38%. Further, in the 1.0V condition and the SS condition, the conventional cell has about 6.6 μA and the present embodiment has 0.6 μA, and the reduction rate is about 90%.

  29 to 31 are graphs showing the temperature dependence of the bit line current suppression effect under each device condition (including a fifth embodiment to be described later). In each figure, the vertical axis indicates the discharge current (bit line current) Iss (nA) of the bit line WBL, and the horizontal axis indicates the temperature (° C.). The temperature is changed from 125 ° C. to 25 ° C. in 10 ° C. steps. The squares in FIG. 29 to FIG. 30 indicate conventional cells. In the conventional cells, the discharge current of the bit line has almost no temperature dependence, and the maximum change is 0.16 μA. Specifically, it is as follows.

  FIG. 29 shows 1.1V conditions and CC conditions. In the graph, squares indicate conventional cells, circles indicate memory cells MC of the present embodiment, and triangles indicate memory cells MC of the fifth embodiment. As a result of comparing the graph of the present embodiment with the conventional cell, the reduction rate of the discharge current Iss of the bit line in the memory cell MC is about 80% to 86%.

  In FIG. 30, a white square indicates the 1.2V condition and the FF condition of the conventional cell, a black square indicates the 1.2V condition and the FS condition of the conventional cell, and a white circle indicates the memory cell MC of the present embodiment. The 1.2V condition and the FF condition are shown, and the black circles indicate the 1.2V condition and the FS condition of the memory cell MC of the present embodiment. The white triangle indicates the 1.2V condition and FF condition of the memory cell MC of the fourth embodiment, and the black triangle indicates the 1.2V condition and FS condition of the memory cell MC of the fourth embodiment. Show. Referring to the white circle and black circle graphs of the present embodiment, the reduction rate of the discharge current Iss of the bit line WBL is about 38% to 46% and about 43% to 51%, respectively, as compared with the conventional cell. is there.

  In FIG. 31, the white square indicates the 1.0V condition and SS condition of the conventional cell, the black square indicates the 1.2V condition and SF condition of the conventional cell, and the white circle indicates the memory cell of the present embodiment. The 1.0V condition and SS condition of MC are shown, and the black circles indicate the 1.2V condition and SF condition of the memory cell MC of the present embodiment. A white triangle indicates a 1.0 V condition and an SS condition of the memory cell MC of the fourth embodiment, and a black triangle indicates a 1.2 V condition and an SF condition of the memory cell MC of the fourth embodiment. Referring to the white circle and black circle graphs of the present embodiment, the reduction rate of the discharge current Iss of the bit line WBL is about 90% to 92% and about 87% to 90%, respectively, as compared with the conventional cell. It is.

  FIG. 32 is a graph summarizing the results of FIGS. 29 to 31 (including a fifth embodiment described later). The bit line current under each device condition is shown as a reduction rate based on the conventional cell. Moreover, the temperature dependence from 25 degreeC to 125 degreeC is also shown. The vertical axis represents the reduction rate (%) of the bit line current relative to the conventional cell, and the horizontal axis represents each device condition. However, the left side of this graph shows the result of Vss control (second embodiment), and the right side shows the result of Vss + Vdd control (fifth embodiment). Of the device conditions, “CC, 1.1V” indicates the 1.1V condition and the CC condition, and “FF, 1.2V” indicates the 1.2V condition and the FF condition. Similarly, “SS, 1.0 V” indicates a 1.0 V condition and SS condition, “FS, 1.2 V” indicates a 1.2 V condition and FS condition, and “SF, 1.2 V” indicates 1.2V condition and SF condition are shown. Under each device condition, the delay time is calculated in steps of 10 ° C. from 25 ° C. to 125 ° C. using temperature as a parameter. Accordingly, the eleven bar graphs indicate eleven operating temperature conditions in a 10 ° C. step from the 125 ° C. condition to the 25 ° C. condition in order from the left side to the right side.

  From the above results, if the memory cell MC of the present embodiment is used, the discharge current Iss of the bit line WBL can be reduced by about 38% to 92% as compared with the conventional cell. In terms of current value, the discharge current of 6.6 μA to 8.7 μA in the conventional cell can be reduced to 0.56 μA to 5.0 μA in the present embodiment.

  Note that the leakage current and the delay time (FIG. 33, FIG. 34) from the rise of the word line (50%) to the output of the read signal (50%) in this embodiment are the first embodiment. The description is omitted here.

  In this embodiment, the word driver and its control circuit are configured in the same circuit system as that of the conventional cell by using a common word line WL without using separate word lines (RWL, WWL) for reading and writing. can do. This eliminates the need for a write word driver and control circuit required in the first embodiment, reduces the chip area compared to the first embodiment, and consumes current and leakage current flowing in the circuit. Can also be reduced. In this embodiment, the diode-connected configuration in the memory cell MC can reduce the discharge current of the charge that flows from the bit line WBL during the read operation. Therefore, the operating current during the read operation can be reduced as compared with the conventional cell. Furthermore, the present embodiment can reduce the leakage current during the holding period as in the first embodiment. As described above, since the operating current and the leakage current can be reduced, the current consumption of the semiconductor chip (LSI) on which the memory cell MC of the present embodiment is mounted is reduced. In addition, in a semiconductor chip on which this memory cell is mounted, the malfunction and stop of the system are reduced to suppress thermal runaway induced by an increase in current consumption, and the reliability of the system configured with this semiconductor chip is improved.

(Third embodiment)
A configuration of the semiconductor device according to the third embodiment will be described. The memory cell MC of the first embodiment described above is different from the memory cell MC of the present embodiment in the following points. The memory cell MC according to the first embodiment described above includes the leak suppression transistor M10 between the common source of the driver transistors M3 and M4 and Vss. On the other hand, the memory cell MC of the present embodiment has a leak suppression transistor M11 between the common source of the load transistors M1 and M2 and Vdd. That is, the memory cell MC of the present embodiment is different from the memory cell MC of the first embodiment in that a leak suppression transistor (M11) is provided on the Vdd side. Below, the difference is mainly demonstrated.

  FIG. 17 is a circuit diagram showing a configuration of the memory cell MC of the semiconductor device according to the third embodiment. The memory cell MC includes second conductivity type (N) driver transistors M3 and M4, second conductivity type (N) access transistors M5 and M6, first conductivity type (P) load transistors M1 and M2, A leak suppression transistor M11 of the first conductivity type (P) is provided. The leak suppression transistor M11 has a gate connected to the source of the access transistor M5 (storage node SNT), a drain connected to the common source of the load transistors M1 and M2, and a source connected to the power supply Vdd. The access transistor M5 has a drain connected to the read bit line RBL and a gate connected to the read word line RWL. Access transistor M6 has a drain connected to write bit line WBL and a gate connected to write word line WWL. At this time, the common source of the driver transistors M3 and M4 is connected to the power supply Vss.

  In the present embodiment, due to the effect of the leak suppression transistor M11, when the data in the storage node SNT is “1”, the potential on the high potential side (Vdd side) applied to the memory cell MC may be made lower than Vdd. it can. For this reason, the leakage current flowing in the memory cell MC is reduced as compared with the conventional cell. The leak suppression transistor M11 is autonomously performed in response to the write data to the memory cell MC without using a special control signal. Accordingly, the leak suppression transistor does not need to be controlled by the control signal, and the access time is not limited by the control signal, so that it does not become slow. Further, since a control circuit for generating a special control signal is not required, the layout area does not increase and the current consumption does not increase. The effect of reducing the leakage current can be obtained not only in non-selected memory cells MC but also in selected memory cells MC. Further, in the memory cell MC of the present embodiment, since read and write word lines are used, a discharge current flows from one of the paired bit lines WBL to Vss in the memory cell MC during the read operation. Therefore, the operating current during the read operation is reduced as compared with the conventional cell.

  The operation of the semiconductor device according to the third embodiment will be described. Specifically, a writing operation, a holding state, and a reading operation of the memory cell MC will be described with reference to FIG.

  A case where data “1” is written from the state of data “0” in the storage node SNT (when data is rewritten to Suppression-Mode) will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. Next, the write buffer outputs write data to the bit lines RBL and WBL according to the input data. The column decoder CD activates the selection switch in the column selector CS, and transmits the data sent from the write buffer to the selected bit lines RBL and WBL. When the write data is “1”, the potential of the bit line RBL is set high and the potential of the bit line WBL is set low. As a result, the potential of the storage node SNT in the memory cell MC changes from Low to High, and the potential of the storage node SNB changes from High to Low. That is, the potentials of the storage node SNT and the storage node SNB are rewritten to the potential according to the input data via the bit lines RBL and WBL.

  Thereafter, the rewriting of data stored in the memory cell is completed by setting the selected word line potential to the low potential (Vss potential). The storage node SNT is at a High (Vdd) potential, and the leak suppression transistor M11 is in an off state (inactive state). The leakage current flowing through the memory cell in this state can be represented by an equivalent circuit of the memory cell shown in FIGS. 18B and 18C. (Detailed description of FIGS. 18B and 18C will be described later.) Referring to FIG. 18C, the potential of the common node PS (and storage node SNT) of the load transistors M1 and M2 is represented by Vdd · Rmc / (Rmc + R11). Become. Here, R11 is an equivalent resistance when the leakage suppression transistor M11 is OFF, and Rmc is an equivalent resistance of the inverter IVt and the inverter IVb as a combined resistance. The potential Vdd · Rmc / (Rmc + R11) of the node NS is an equivalent resistance division ratio obtained by replacing the leak current flowing in the memory cell MC with an equivalent circuit. Therefore, in the state where the storage node SNT of the memory cell MC holds data “1”, the potential on the high potential side (Vdd potential side) applied to the memory cell MC can be lowered, The applied power supply voltage is lower than that of the conventional cell. For this reason, the leakage current flowing in the memory cell MC can be reduced.

  However, the potential of the node PS during the data write operation is once lower than the potential Vdd · Rmc / (Rmc + R11) as the potential of the storage node SNB falls. During the data holding period, the potential of the node PS gradually increases toward the potential represented by the above-described division ratio. Further, the potential of the storage node SNB immediately falls to Vss along with the write operation, and the load transistor M1 is turned on, so that the node PS and the storage node SNT become a common node. From these factors, immediately after writing, the leakage suppression transistor M11 is not immediately turned off (inactive) but is turned on, and gradually shifts to the off state. Since this transition occurs over several cycles immediately after the write operation, the leakage current of the memory cell flows more than that in the conventional cell within this period.

  A read operation of data “1” will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. The selected word line RWL turns on the access transistors M5 of all the memory cells connected to the word line RWL. As a result, a High (Vdd) potential that is the potential of the storage node SNT is output as the potential of the bit line RBL. Here, the storage node SNT has a potential equal to or higher than (Vdd−Vth11 (threshold voltage of M11)) with respect to Vss. This is because when the potential is lower than the potential of (Vdd−Vth11), the leak suppression transistor M11 has a diode connection configuration and is clamped to the potential of (Vdd−Vth11). Since the access transistor M5 is composed of the same device as the leak suppression transistor M11, the threshold voltage has almost the same value. Therefore, even when the word line RWL rises during the read operation, the access transistor M5 is in an off state (inactive state), and the charged charge of the bit line RBL is not discharged to Vss in the memory cell, and the potential of the bit line RBL is It does not fall. Further, even if the potential of the storage node SNT decreases as the access transistor M5 is turned on due to the variation in threshold voltage, the potential of the bit line RBL does not fall below the potential of (Vdd−Vth11). Can be read.

  A case where data “0” is written from the state of data “1” will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. The row decoder RD raises the selected word lines RWL and WWL and turns on the access transistors M5 and M6 of all the memory cells connected to the word lines RWL and WWL. Next, the write buffer outputs write data to the bit lines RBL and WBL according to the input data. The column decoder CD activates the switch of the selected bit line of the column selector CS, and transmits the data sent from the write buffer to the selected bit lines RBL and WBL. When the write data is “0”, the potential of the bit line RBL is set to Low, and the potential of the bit line WBL is set to High. As a result, the potential of the storage node SNT changes from High to Low, and the potential of the storage node SNB changes from Low to High. That is, the potentials of the storage node SNT and the storage node SNB are rewritten to the potential according to the input data via the bit lines RBL and WBL. Thereafter, the rewriting of data stored in the memory cell is completed by setting the selected word line potential to the low potential (Vss potential).

  Next, in the data “0” holding state, the storage node SNT is at the Low (Vss) potential, and the leakage suppression transistor M11 and the load transistor M2 are in the on state. The high potential of the storage node SNB is held at the Vdd potential via the load transistor M2 and the leak suppression transistor M11, and the potential of the node PS is also held at the Vdd potential via the leak suppression transistor M11.

  A read operation of data “0” will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. The word driver in the row decoder RD raises only the selected word line RWL (rises to Vdd) and turns on the access transistors M5 of all memory cells connected to the word line RWL. As a result, the charge on the bit line RBL is discharged to Vss via the storage node SNT in the memory cell MC. At this time, storage node SNT temporarily increases the potential together with the discharge current flowing from bit line RBL. However, as the potential of the bit line RBL drops, the potential of the storage node SNT gradually becomes Vss. At this time, the discharge current of the bit line RBL is also referred to as a read current. In addition, when data “0” (Vss) is stored in the storage node SNT and data “1” (Vdd) is stored in the storage node SNB, Vdd is applied to the gate of the driver transistor M3, and reading is performed with sufficient driving force. Current flows.

The mechanism and effect of the memory cell according to this embodiment will be described.
It is assumed that data “1” (High) is stored in storage node SNT and data “0” (Low) is stored in storage node SNB (suppression mode). The potential of the storage node SNT is such that the leak suppression transistor M11 is in an off state and the memory cell MC is in a data holding state and a leak current flows. The potential of the storage node SNB is Vss. 18A to 18C are diagrams for explaining the data holding state at this time. 18A is a circuit diagram showing the memory cell MC, and FIGS. 18B and 18C show the memory cell MC in an equivalent circuit.

  As shown in FIG. 18A, the storage node SNB holds the Vss potential, and the load transistor M1 is in the on state. Therefore, the node PS and the storage node SNT become a common node, and the leak suppression transistor M11 has a diode connection configuration. The driver transistor M3 and the load transistor M2 are in an off state. In this state, a leak current flows from Vdd to Vss in inverters IVt and IVb. FIG. 18B is an equivalent circuit in which the transistor in the memory cell MC is replaced with an equivalent resistance. Here, resistors Rivt and Rivb are obtained by replacing inverters IVt and IVb with equivalent resistors. The resistor R11 is obtained by replacing the leak current flowing through the leak suppression transistor M11 with an equivalent resistor. The diode D11 indicates that the leak suppression transistor M11 has a diode connection configuration, and is replaced with an equivalent element. FIG. 18C is obtained by replacing the equivalent resistances Rivt and Rivb of FIG. 18B with a combined resistance Rmc. Assuming that Vss = 0V, the potential Vps of the node PS is obtained based on FIG. 18C and can be expressed by Vdd · Rmc / (Rmc + R11). The potential Vps of the node PS is lower than Vdd by ΔVps = Vdd · R11 / (Rmc + R11). However, the potential Vps of the node PS at this time is established when it is lower than the absolute value Vth11 of the threshold voltage of the leak suppression transistor M11. When the potential Vps of the node PS is higher than the absolute value Vth11 of the threshold voltage of the leak suppression transistor M11, the potential Vps of the node PS is clamped by the diode D11 and becomes Vdd−Vth11.

  In this way, when the potential of the storage node SNT is High (the potential of the node PS) and the potential of the storage node SNB is Low (Vss) (in the suppression mode), the potential on the high potential side of the memory cell MC (the potential of the node PS). The potential Vps) is lower than the Vdd by the above ΔVps, and the leakage current imc flowing through the memory cell MC is imc = Vdd / (Rmc + R11). Here, if the leakage current in the conventional cell not using the leakage suppression transistor M11 is icon, icon = Vdd / Rmc. Therefore, the leakage current (imc) flowing through the memory cell MC is reduced compared to the leakage current (icon) of the conventional cell.

  In the present embodiment, the absolute value of the threshold voltage of leak suppression transistor M11 is preferably lower than the absolute value of the threshold voltage of access transistors M3 and M4. As described above, considering the case where the potential Vps of the node PS is clamped by the diode D11 and becomes the threshold voltage Vth11 of the leak suppression transistor M11, the bias voltage applied between the gate and the source of the driver transistor M4 is sufficiently set. This is because the ON resistance of the driver transistor M4 is reduced. Thereby, the tolerance with respect to the noise in the storage node SNB can be made high.

  FIG. 19 is a graph in which the average leakage current Iddmc after the data “1” (Vdd) is written to the storage node SNT is plotted in the holding cycle. The average leakage current Iddmc in the figure is calculated by computer simulation using HSPICE, and indicates a value at 50 cycles in the holding state after the data writing operation. The horizontal axis represents the number of cycles in the holding state after data writing, and the vertical axis represents the average leakage current Iddmc (nA) in logarithm. In this figure, the white triangle is when the FF condition and the 1.2V condition are used in the memory cell MC of the present embodiment. The black triangle is the result when the FF condition and the 1.2 V condition are used in a conventional 6-transistor memory cell (conventional cell). The white circle is the result when the CC condition and the 1.1 V condition are set in the memory cell MC of the present embodiment. A black circle is a result in the case of CC condition and 1.1V condition in a conventional cell. The white squares are the results when the SS condition and the 1.0 V condition are used in the memory cell MC of the present embodiment. The black squares are the results when SS conditions and 1.0 V conditions are used in a conventional cell.

  As shown in FIG. 19, the leakage current (Idddmc) increases in the order of the SS condition, CC condition, and FF condition. Based on the FF condition, the leak current value is low by two digits under the CC condition and three digits under the SS condition. It can be seen that the leakage current under the FF condition is larger than the other conditions and maximum. This tendency is the same in the conventional cell. Therefore, since the leakage current value under various conditions is lower than the leakage current value under the FF condition of the conventional cell, it can be confirmed that this embodiment has an effect of reducing the leakage current as compared with the conventional cell.

  Further, the leakage current of the memory cell MC (FIG. 17) of the present embodiment can be reduced by 30.1% under the FF condition as compared with the leakage current of the conventional cell (6 transistors). By the way, in the present embodiment, the potential of the node PS decreases during the write operation of the data “1”, and the rise time at the storage node SNT becomes gradual. This is because the current flowing through the leakage suppression transistor M11 decreases as the potential of the storage node SNT increases. For this reason, the potential of the storage node SNT gradually rises from the potential between Vdd and Vss. Therefore, a minute through current flows in the inverter IVb in several cycles after the write operation, and the leak current in the memory cell MC temporarily becomes larger than that in the conventional cell. This leakage current decreases as the gate potential (SNT potential) of the leakage suppression transistor M11 increases toward Vdd · Rmc / (Rmc + R11). This phenomenon can also be observed from FIG. In this figure, it is understood that the leakage current is smaller than that of the conventional cell under the FF condition when the retention cycle after the write operation is 3 cycles or more under the SS condition and the CC condition, and after 4 cycles under the FF condition.

  A phenomenon in which the above-described leakage current becomes larger than that of a conventional cell will be examined on a memory cell array scale. In this embodiment, the size of the memory cell array for simulation is composed of 16 bits of memory cells. Assuming that data “1” is repeatedly written in order of 1 bit at a time under the FF condition in this array scale, the write cycle is once every 16 cycles. In addition, 3 bits out of 15 bits have a larger leakage current than the conventional cell (where 1 bit is a cycle during a write operation, and the 3 bits correspond to the above-described 3 cycles). When the sum of the leakage current of 3 bits and the remaining leakage current of 12 bits is larger than the leakage current of 15 bits of the conventional cell, there is no effect of reducing the leakage current. Actually, the memory size of the SRAM macro has a storage capacity of at least several kilobits, and the remaining number of bits is overwhelmingly larger than 3 bits. The 3-bit leakage current flows 32.3 nA, 6.7 nA, and 0.9 nA more than the conventional cell, but other bits reduce the leakage of about 5 nA compared to the conventional cell. That is, even if the leakage current increased by 3 bits is about 40 nA, the leakage current of 5 nA × 1 kb = 5 μA can be reduced if the remaining bits are 1 kilobit. From this, even if there are several to tens of bits of memory cells in which the leakage current temporarily increases as in the present embodiment, it can be seen that the effect of reducing the leakage current is great when viewed from the entire memory cell array. .

  25 to 28 are graphs showing cycle dependency of leakage current in each control method (including first and fourth (described later) embodiments) (however, FIGS. 27 and 28 are partial graphs). Has expanded to). The preconditions and symbols of these graphs are as already described in the first embodiment. However, as described above, in the third embodiment (“Vdd-Cntrl”), the black circle, the white circle, and the cross mark are the Vdd1.2V condition, the FF condition, the Vdd1.1V condition, and the CC, respectively. Condition, Vdd 1.0 V condition and SS condition.

  As shown by the black circles in FIG. 25, the leakage current is reduced by 15% in the Vdd 1.2V condition, the FF condition, and the 125 ° C. condition as compared with the conventional cell. Also, as shown by the black circles in FIG. 26, the leakage current is reduced by 19.6% under the Vdd 1.2 V condition, the FF condition, and the 75 ° C. condition as compared with the conventional cell. Further, as shown by the black circles in FIG. 27, under the Vdd 1.2V condition, the FF condition and the 40 ° C. condition, the leakage current is reduced by 15.0% compared to the conventional cell. Further, as shown by the black circles in FIG. 28, the leakage current is reduced by 11.2% in the Vdd 1.2V condition, the FF condition, and the 25 ° C. condition as compared with the conventional cell.

  As described above, in the present embodiment, the value of the leakage current is determined depending on the stored data. However, the correlation between the distribution ratio of the stored data “1” and the leakage current, the variation and temperature dependence of the devices exhibiting the above characteristics, the probability of storing the data “1”, the memory cell mounted on the SoC semiconductor chip From the number of MCs and the like, the memory cell MC of the present embodiment has an effect of reducing the leakage current as compared with the conventional cell.

  As shown in FIGS. 25 to 28, when the leakage current Idd of 125 ° C. to 25 ° C. is observed, it can be seen that the leakage current increases as the temperature increases. The leakage current becomes the maximum condition at 1.2 V at 125 ° C. and FF conditions. As described above, the retention period after the write operation is four cycles or more, and the leakage current is smaller than that of the conventional cell. When the cycle condition in which the leakage current decreases with respect to the conventional cell is observed from 125 ° C. to 25 ° C., the number of cycles in which the leakage current decreases compared to the conventional cell increases as the temperature decreases. For example, it can be seen that the leakage current decreases after 30 cycles at 25 ° C. (FIG. 28). In other words, it can be said that the leakage current is larger than that of the conventional cell up to 29 cycles.

  Here, it is assumed that the write operation is repeated bit by bit for a memory cell array having a memory capacity of 1 kilobit. Specifically, the 29-bit (29 cycles) leakage current increases by the following amount compared to the conventional cell. The first to tenth bits are 34.1 nA, 12.4 nA, 7.4 nA, 5.1 nA, 3.8 nA, 3.0 nA, 2.4 nA, 2.0 nA, 1.7 nA, and 1.4 nA, respectively. . The 11th to 20th bits are 1.2 nA, 1.1 nA, 0.9 nA, 0.8 nA, 0.7 nA, 0.6 nA, 0.52 nA, 0.45 nA, 0.39 nA, and 0.33 nA, respectively. . The 21st to 29th bits are 0.29 nA, 0.24 nA, 0.2 nA, 0.17 nA, 0.13 nA, 0.1 nA, 0.07 nA, 0.05 nA, and 0.02 nA, respectively. The total of these 29-bit leakage currents is 81.7 nA. After 30 bits, it decreases by about 0.24 nA. Here, since the number of memory cells MC corresponding to the 30th bit and after is about 1 kilobit, the reduction in leakage current is about 240 nA in total. From the above, this memory macro can reduce the leakage current of about 160 nA. In addition, a SoC (System On Chip) semiconductor chip has a large number (hundreds to thousands) of SRAM macros having a built-in memory capacity of several kilobits to several tens of megabits. Therefore, it can be seen that the reduction amount is overwhelmingly larger than the reduction amount of the leakage current.

  The delay time of the read signal from the rise of the word line to the output of the read signal in this embodiment will be described. FIG. 33 is a table showing the delay time of the read signal from the rise of the word line until the read signal is output (including the first and second and fourth to fifth embodiments). The preconditions and symbols of these graphs are as already described in the first embodiment.

  Under CC conditions, 74.0 to 75.9 psec. In the third embodiment (Vdd control) 73.8.4 to 75.7 psec. Is the delay. Under the FF condition, 47.1-48.2 psec. Of 47.0 to 47.7 psec. In the third embodiment. Is the delay. Under the SS condition, the delay is 142.7 to 143.1 psec in the conventional cell, and 142.2 to 142.6 psec. In the third embodiment. Is the delay. From this table, there is a feature that the delay time becomes longer as the temperature becomes higher under the CC condition and the FF condition, and the delay time becomes shorter as the temperature becomes higher under the SS condition. However, these changes are 2 psec. It can be seen that there is almost no temperature dependence under each condition.

  FIG. 35 is a graph showing the increase rate of the delay time in each control method based on the delay time of the conventional cell with respect to the result of FIG. The eleven bar graphs in each control method become temperature conditions of a 10 ° C. step from the 125 ° C. condition to the 25 ° C. condition in order from the left side to the right side. Under the CC condition of Vdd control (Vdd control “CC”), a delay increase of about 0.2% is recognized as compared with the conventional cell. The Vdd control FF condition (Vdd control “FF”) has a delay increase of about 0.2 to 1% compared to the conventional cell, and the Vdd control SS condition (Vdd control “SS”) is greater than that of the conventional cell. About 0.3% increase in delay is observed. The Vdd control FS condition (Vdd control “FS”) has a delay increase of about 0.2 to 0.7% compared to the conventional cell, and the Vdd control SF condition (Vdd control “SF”) has the conventional cell. There is a delay increase of about 0.2%. This embodiment is about 1% faster than the conventional cell. From these facts, it can be said that this embodiment has no superiority or inferiority in the temperature dependence of the reading speed as compared with the conventional cell.

  As described above, this embodiment also has an effect of reducing the leakage current as compared with the conventional cell. In this embodiment, since the read and write word lines are used, the discharge current (read current) does not flow from the write bit line WBL during the read operation, and the operation current is suppressed during the read period. There is. Further, in this embodiment, the reading speed of the memory cell is equal to that of the conventional cell, and reading can be performed at a higher speed than the first embodiment and the second embodiment. For these reasons, the present embodiment has an effect of reducing the leakage current and the read operation current while maintaining the read speed equivalent to that of the conventional cell. Therefore, the semiconductor chip on which the semiconductor device of this embodiment is mounted can reduce current consumption. In addition, the effect of reducing current consumption can suppress a temperature rise caused by a semiconductor chip (LSI), and reduce malfunction and stoppage of the system due to thermal runaway. Furthermore, the reliability of the system using this semiconductor chip is improved by reducing the malfunction and stoppage.

(Fourth embodiment)
A configuration of the semiconductor device according to the fourth embodiment will be described. The memory cell MC of the first embodiment described above is different from the memory cell MC of the present embodiment in the following points. The memory cell MC according to the first embodiment described above includes the leak suppression transistor M10 between the common source of the driver transistors M3 and M4 and Vss. On the other hand, in addition to the memory cell MC of the first embodiment, the memory cell MC of the present embodiment has a leak suppression transistor M11 between the common source of the load transistors M1 and M2 and Vdd. That is, the memory cell MC of the present embodiment is different from the memory cell MC of the first embodiment in that a leak suppression transistor (M11) is also added on the Vdd side. In other words, the memory cell MC of the present embodiment has a configuration in which the first embodiment and the third embodiment are combined. Below, the difference is mainly demonstrated.

  FIG. 20 is a circuit diagram showing a configuration of the memory cell MC of the semiconductor device according to the fourth embodiment. The memory cell MC includes second conductivity type (N) driver transistors M3 and M4, second conductivity type (N) access transistors M5 and M6, first conductivity type (P) load transistors M1 and M2, A second conductivity type (N) leakage suppression transistor M10 and a first conductivity type (P) leakage suppression transistor M11 are provided. The leak suppression transistor M10 has a gate connected to the source of the access transistor M6 (storage node SNB), a drain connected to the common source of the driver transistors M3 and M4, and a source connected to the power supply Vss. The leak suppression transistor M11 has a gate connected to the source of the access transistor M5 (storage node SNT), a drain connected to the common source of the load transistors M1 and M2, and a source connected to the power supply Vdd. The access transistor M5 has a drain connected to the read bit line RBL and a gate connected to the read word line RWL. Access transistor M6 has a drain connected to write bit line WBL and a gate connected to write word line WWL.

  Also in the present embodiment, as in the first and third embodiments, when the data of the storage node SNT is “1”, the potential on the low potential side (Vss potential side) applied to the memory cell MC is increased. The potential on the high potential side (Vdd potential side) can be lowered. Thereby, the leak current flowing in the memory cell MC is reduced. The control of these leak suppression transistors M10 and M11 is autonomously performed in the memory cell MC corresponding to the data to be written in the memory cell MC without using a special control signal. Therefore, in this embodiment, a control signal for suppressing leakage is unnecessary, the access time is not limited by the control signal, and a control signal generation circuit is not required. For this reason, an increase in chip area and an increase in current consumption due to the control circuit do not occur. The effect of reducing the leakage current can be obtained not only in the non-selected memory cell MC but also in the selected memory cell MC. Furthermore, in the present embodiment, since read and write word lines are used, a discharge current does not flow from one of the paired bit lines WBL to Vss in the memory cell MC during a read operation. Current consumption during the read operation is reduced.

  In the present embodiment, when data “0” (Vss) is stored in storage node SNT and data “1” (Vdd) is stored in storage node SNB, leakage suppression transistor M11 and leakage suppression transistor M10 are turned on. . Therefore, the Vdd potential is applied to the gate of the driver transistor M3, the Vss potential is applied to the source, the Vss potential is applied to the gate of the load transistor M2, and the Vdd potential is applied to the source. These applied voltages are sufficient bias voltages for the driver transistor M3 and the load transistor M2, and suppress the decrease in the reading speed as much as possible. On the other hand, when data “1” (Vdd) is stored in storage node SNT and data “0” (Vss) is stored in storage node SNB, leak suppression transistors M11 and M10 are turned off. The potentials of the node PS and the node NS can be expressed by a division ratio of an equivalent resistance indicated by a leak current flowing in the memory cell MC, and the leak current flowing in the memory cell MC can be reduced.

  The operation of the semiconductor device according to the fourth embodiment will be described. Specifically, a writing operation, a holding state, and a reading operation of the memory cell MC will be described with reference to FIG.

  A case where data “1” is written from the state of data “0” in the memory cell MC (when rewritten to Suppression-Mode) will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. The word driver in the row decoder RD raises the selected word lines RWL and WWL and turns on the access transistors M5 and M6 of all the memory cells connected to the word lines RWL and WWL. Next, the write buffer outputs write data to the bit lines RBL and WBL according to the input data. The column decoder CD activates the selection switch in the column selector CS, and transmits the data sent from the write buffer to the selected bit lines RBL and WBL. When the write data is “1”, the potential of the bit line RBL is set high and the potential of the bit line WBL is set low. As a result, the potential of the storage node SNT changes from low to high, and the potential of the storage node SNB changes from high to low. That is, the potentials of the storage node SNT and the storage node SNB are rewritten to the potential according to the input data via the bit lines RBL and WBL. Thereafter, the rewriting of data stored in the memory cell is completed by setting the selected word line potential to the low potential (Vss potential). At this time, the potentials of the node PS and the node SNT become a potential between Vdd and Vss in the process in which the leak suppression transistor M11 and the leak suppression transistor M10 are turned off, as in the third embodiment. As shown in the third embodiment, the rising speed of storage node SNT is slower than the falling speed of storage node SNB. This is because the current of the leakage suppression transistor M11 decreases as the potential of the storage node SNT increases. Therefore, the potential of the node PS during the write cycle is lowered to a value lower than the value represented by the division ratio of the equivalent resistance, so that both the load transistor M2 and the driver transistor M4 in the inverter IVb are turned on, and the potential is small. Pass through current. After the write cycle, the lowered potential of the node PS becomes a value represented by the division ratio of the equivalent resistance over several cycles.

  In memory cell MC, the retention state of data “1” after data writing is represented by a division ratio from a state in which the potential of node PS and node NS is lower than the value represented by the division ratio of the equivalent resistance. This is the period of transition to the value. In the first cycle after the write operation, the potentials of the nodes NT and PS are lower than the value of the division ratio, so that more leakage current flows than in the conventional cell.

  After several cycles after the write operation, in the memory cell MC, in the data “1” holding state, the potential on the low potential side (Vss potential side) applied to the memory cell MC is high and the high potential side (Vdd potential side). ) Can be lowered and the power supply voltage applied to the memory cell is lowered, so that the leakage current flowing in the memory cell can be reduced.

  A read operation of data “1” in the memory cell MC will be described. The operations from the precharge of the bit line to the rise of the word line are the same as in the first embodiment. The word driver in the row decoder RD raises only the selected word line RWL and turns on all the access transistors M5 connected to the word line RWL. As a result, High (Vdd) that is the potential of the storage node SNT is reflected in the potential of the bit line RBL, and the potential of the storage node SNT is read. Here, the potential of the storage node SNT is higher than (Vdd−Vth11 (threshold voltage of M11)) with respect to Vss. This is because when it is lower than the potential of (Vdd−Vth11), it is clamped to the potential of (Vdd−Vth11) by the diode connection configuration of the leak suppression transistor M11. Therefore, the potential of the source of the access transistor M5 is also higher than the potential of (Vdd−Vth11). Further, since the access transistor M5 and the leak suppression transistor M11 are composed of the same device, the threshold voltages are almost the same value. For these reasons, even if the word line RWL rises during the read operation, the access transistor M5 is in an off state, the charge of the bit line RBL is not discharged, and the potential of the bit line RBL does not drop. Even when the potential of the storage node SNT decreases as the access transistor M5 is turned on due to variations in threshold voltage, the potential of the bit line RBL does not fall below the potential of (Vdd−Vth11). The appearing data “High” can be read.

  In the memory cell MC, the write operation for storing the data “0” from the data “1” state is almost the same as in the third embodiment, except that the potential of the node NS is slightly higher than Vss. It is a point written from. The operation after rewriting, the holding period, and the reading operation are the same as those in the first embodiment, and a description thereof will be omitted.

Next, the mechanism and effect of the memory cell according to the present embodiment will be described.
It is assumed that data “1” (High) is stored in storage node SNT and data “0” (Low) is stored in storage node SNB (suppression mode). Due to the bias potential applied to the storage node SNT, the leakage suppression transistor M11 is in the off state, and the leakage current flowing through the memory cell MC is represented by a resistance value division ratio represented by an equivalent resistance. Similarly, due to the bias potential applied to storage node SNB, leak suppression transistor M10 is in an off state, and the leak current flowing through memory cell MC is represented by a resistance value division ratio represented by an equivalent resistance. FIG. 21A to FIG. 21C are diagrams for explaining a potential state in the suppression mode. Among these, FIG. 21A is a circuit diagram showing the memory cell MC, and FIGS. 21B and 21C are shown by an equivalent circuit of a leakage current flowing in the memory cell MC.

  As shown in FIG. 21A, since data “High” (Vdd) is stored in storage node SNT, driver transistor M4 is in an on state. Further, since the data “Low” (Vss) is stored in the storage node SNB, the load transistor M1 is also in the on state. Therefore, each of the leak suppression transistor M11 and the leak suppression transistor M10 is a circuit that forms a diode connection. In this case, a leak current flows from Vdd to Vss through inverters IVt and IVb. As shown in FIG. 21B, the memory cell MC in this state can be represented by an equivalent circuit in which a transistor is replaced with a resistor. Here, the resistors Rivt and Rivb are obtained by replacing the inverters IVt and INb with equivalent resistors. Resistors R11 and R10 are obtained by replacing leak currents flowing through the leak suppression transistors M11 and M10 with equivalent resistors. Since the leak suppression transistors M11 and M10 have a diode connection configuration, they are replaced with equivalent elements of the diodes D11 and D10. FIG. 21C represents the resistances Rivt and Rivb of FIG. 21B as a combined resistance Rmc. Based on FIG. 21C, the potential Vps of the node PS can be expressed by Vdd (Rmc + R10) / (Rmc + R11 + R10), and the potential Vps of the node PS is lower than Vdd by ΔV1 = Vdd · R11 / (Rmc + R11 + R10). However, this is established when the potential Vps of the node PS is lower than the threshold voltage Vth11 of the leak suppression transistor M11. When the potential Vps of the node PS is higher than the threshold voltage Vth11 of the leak suppression transistor M11, the potential Vps of the node PS is clamped by the diode D11 and becomes Vdd−Vth11. Further, the potential Vns of the node NS can be expressed by Vdd · R10 / (Rmc + R11 + R10), and the potential Vns of the node NS is higher than Vss by ΔV2 = Vdd · R10 / (Rmc + R11 + R10). However, the potential Vns of the node NS at this time is established when it is lower than the threshold voltage Vth10 of the leak suppression transistor M10. When the potential Vns of the node NS is higher than the threshold voltage Vth10 of the leak suppression transistor M10, the potential Vns of the node NS is clamped by the diode D10 and becomes Vss + Vth10.

  As described above, the potential on the high potential side of the memory cell MC (the potential Vps of the node PS) is biased lower than the Vdd by the above ΔV1. The potential on the low potential side of the memory cell MC (the potential Vns of the node NS) is biased higher than Vss by the above ΔV2. For this reason, the leakage current Iddmc flowing in the memory cell MC is Iddmc = Vdd / (Rmc + R11 + r10). Here, in a conventional memory cell composed of 6 transistors, the leakage current icon is icon = Vdd / Rmc. Therefore, the leakage current (Idddmc) flowing in the memory cell MC is reduced as compared with the conventional leakage current (icon).

  FIG. 22 shows the retention cycle of the average leakage current Iddmc flowing in the memory cell when data “1” (Vdd) is written to the storage node SNT of the memory cell and the memory cell SNT is in the retention state (the potentials of the word lines RWL and WWL are Vss). It is a graph which shows dependence. In this figure, values calculated by computer simulation using HSPICE are plotted. The horizontal axis indicates the number of holding cycles after data writing, and the vertical axis indicates the average leakage current Iddmc (nA) in logarithm. In this figure, white triangles are the results when the FF condition and the 1.2 V condition are used in the memory cell MC of the present embodiment. The black triangle is the result when the FF condition and the 1.2 V condition are used in a conventional 6-transistor memory cell (conventional cell). The white circle is the result when the CC condition and the 1.1 V condition are set in the memory cell MC of the present embodiment. The black circle is the result when the CC condition and 1.1V condition in the conventional cell are used. The white squares are the results when the SS condition and the 1.0 V condition are used in the memory cell MC of the present embodiment. A black square is a result at the time of setting SS conditions and 1.0V conditions in a conventional cell.

  Further, in this figure, comparison is made in 50 cycles after the data write operation. As shown in this figure, the leakage current (Idddmc) increases in the order of SS condition, CC condition, and FF condition. Further, it can be seen that the leak current value is low by an order of magnitude in both the CC condition and the SS condition with reference to the FF condition of the present embodiment. That is, it can be seen that the leakage current under the FF condition is larger than the other conditions and is the maximum. This tendency is the same in the conventional cell. Therefore, when the leakage current of the conventional cell under the FF condition is used as a reference, the leakage current value under the various conditions in the present embodiment is low, and this embodiment also has the effect of reducing the leakage current compared to the conventional cell. It can be said that there is.

  As shown in FIG. 22, the memory cell MC (FIG. 20) of the present embodiment under the FF condition can reduce the leakage current by 25.9% compared to the conventional cell (6 transistors).

  25 to 28 are graphs showing the retention cycle dependency of the leakage current in each control method (including the first and third embodiments) (however, FIGS. 27 and 28 are partially enlarged). doing). The preconditions and symbols of these graphs are as already described in the first embodiment. However, as described above, the black triangle, the white triangle, and the white inverted triangle are the 1.2 V condition, the FF condition, and the 1.1 V condition in the fourth embodiment (“Vss + Vdd−Cntrl”), respectively. And CC conditions, 1.0 V conditions and SS conditions.

  Under the Vdd = 1.2V condition and the FF condition, as shown by the black triangle in FIG. 25, the leakage current is reduced by 23.4% compared to the conventional cell. Under the 1.2V condition, the FF condition, and the 75 ° C. condition, as shown by the black triangle in FIG. 26, the leakage current is reduced by 23.6% compared to the conventional cell. Under the 1.2V condition, the FF condition, and the 40 ° C. condition, as shown by the black triangle in FIG. 27, the leakage current is reduced by 18.5% compared to the conventional cell. Under the 1.2V condition, the FF condition, and the 25 ° C. condition, the leak current is reduced by 10.5% as compared with the conventional cell, as shown by the black triangle in FIG.

  As shown in FIG. 28, in the comparison of the leakage current between the present embodiment and the third embodiment, there is no difference in cycle dependency between the present embodiment and the third embodiment at 25 ° C. As shown in FIG. 27, under a high temperature condition of 40 ° C. or higher, the present embodiment reduces the leakage current with a smaller number of holding cycles than the third embodiment. From the above results, the same conclusion as in the third embodiment can be obtained in this embodiment. In other words, assuming a 1-kbit SRAM macro, even if it is assumed that several bits of memory cells have a larger leakage current than conventional cells within several cycles to several tens of cycles after data writing, the remaining 1 kbit or more Since the leak current is reduced in the memory cell as compared with the conventional cell, it can be said that this embodiment has an effect of reducing the leak current as compared with the conventional cell. Here, the assumed 1 kilobit SRAM macro has the minimum memory capacity mounted on the SoC chip.

  Note that the leakage current and the delay time from the rise of the word line (50%) to the output of the read signal (50%) in this embodiment are the same as in the first embodiment. Then, the explanation is omitted.

  Next, the delay time of the read signal from the rise of the word line to the output of the read signal will be described. FIG. 33 is a table showing the delay time of the read signal from the rise of the word line until the read signal is output (including the first to third and fifth embodiments). The preconditions and symbols of these graphs are as already described in the first embodiment.

  Under CC conditions, 74.0 to 75.9 psec. The delay is 87.7 to 90.7 psec in the fourth embodiment (Vss + Vdd control). Is the delay. Under the FF condition, 47.1-48.2 psec. Of 43.7 to 55.5 psec. In the fourth embodiment. Is the delay. In the SS condition, the delay is 142.7 to 143.1 psec in the conventional cell, and in the fourth embodiment is 181.9 to 183.1 psec. Is the delay. As shown in FIG. 33, in this embodiment, the delay time becomes longer as the temperature becomes higher under the CC condition and the FF condition, and there is almost no temperature dependence under the SS condition. However, even in the case of the CC condition and the FF condition, the change in the delay time is 3 psec. Therefore, there is almost no dependence on temperature.

  FIG. 34 is a graph showing the increase rate of the delay time in each control method with respect to the result of FIG. 33 on the basis of the delay time of the conventional cell (the first, second, and fifth described later). Including the embodiment). The preconditions and symbols of these graphs are as already described in the first embodiment. Under the CC condition of Vss + Vdd control (Vss + Vdd control “CC”), a delay increase of 16.3 to 15.6% is recognized as compared with the conventional cell. Further, in the FF condition of Vss + Vdd control (Vss + Vdd control “FF”), a delay increase of 13.2 to 12.3% is recognized as compared with the conventional cell. In addition, in the SS condition of Vss + Vdd control (Vss + Vdd control “SS”), a delay increase of 21.6 to 22.0% is recognized as compared with the conventional cell. Further, in the FS condition and SF condition (Vss + Vdd control “FS”, “SF”) of Vss + Vdd control, the same tendency as the FF condition and CC condition of Vss + Vdd control is recognized.

  In this embodiment, since the discharge current (read current) does not flow from the write bit line WBL during the read operation using the read and write word lines, the effect of suppressing the operation current during the read period is obtained. is there. As described above, since the present embodiment has an effect of reducing the leakage current and the operating current, the current consumption of the semiconductor chip on which the present embodiment is mounted is reduced. Further, in the semiconductor chip (LSI) on which the memory cell shown in this embodiment is mounted, the current consumption is reduced and the temperature rise of the semiconductor chip is suppressed. As a result, the malfunction and stop of the system caused by the thermal runaway are suppressed, and the reliability of the system using this semiconductor chip (LSI) is improved.

(Fifth embodiment)
A configuration of the semiconductor device according to the fifth embodiment will be described. The SRAM macro 2 of the fourth embodiment described above and the SRAM macro 2 of the present embodiment are different in the following points. The word line of the SRAM macro 2 of the fourth embodiment described above has a word line (RWL) for read operation and a word line (WWL) for write operation. On the other hand, the SRAM macro 2 of the present embodiment has only a common word line WL. That is, the SRAM macro 2 of the present embodiment is different from the SRAM macro 2 of the fourth embodiment in that the gates of the access transistors M5 and M6 are connected to the common word line WL. Below, the difference is mainly demonstrated.

  FIG. 23 is a circuit diagram showing a configuration of the memory cell MC of the semiconductor device according to the fifth embodiment. The configuration of the memory cell MC is almost the same as the MC of the fourth embodiment. The difference is that the gates of the access transistors M5 and M6 are connected to the common word line WL. Accordingly, the access transistors M5 and M6 are controlled to be in an on / off state in response to the selection / non-selection signal of the word line WL.

  Also in the present embodiment, as in the fourth embodiment, when the data in the storage node SNT is “1”, the potential on the low potential side (node NS) applied to the memory cell MC is set higher than the Vss potential. can do. In addition, the potential on the high potential side (node PS) can be made lower than the Vdd potential. Therefore, the leakage current flowing in the memory cell can be reduced by reducing the power supply voltage in the memory cell MC. The potential on the low potential side (node NS) and the potential on the high potential side (node PS) are controlled by controlling the leak suppression transistors M10 and M11, but without using a special control signal, Autonomous in response to the write data. In the present embodiment, control by the control signal is unnecessary, and the access time is not rate-limited by the control signal. Further, since a circuit for generating a control signal is unnecessary, there is no increase in chip area or current consumption due to the control circuit. Further, since the effect of reducing the leakage current can be obtained not only in the non-selected memory cell MC but also in the selected memory cell MC, the current consumption of the memory cell array being accessed can be reduced. . In the present embodiment, as in the second embodiment, the word lines are made common word lines without being separated for reading and writing. For this reason, during the read operation, the charge on one of the paired bit lines WBL is discharged toward Vss in the memory cell MC. This discharge current is a consumption current unrelated to the read operation. However, there is a feature that the discharge current of the present embodiment is reduced rather than the discharge of the charge on the bit line WBL of the conventional cell. In the present embodiment, the leakage suppression transistor M10 has a diode-connected configuration via the storage node SNB during the read operation, so that the potential of the storage node SNB is clamped. As a result, the charge of the bit line WBL is not completely discharged, and the operating current during the read operation is reduced as compared with the conventional cell.

  The operation of the semiconductor device according to the fifth embodiment will be described. Specifically, a writing operation, a holding state, and a reading operation of the memory cell MC will be described with reference to FIG.

  The writing operation and the holding state in the present embodiment are the same as those in the fourth embodiment, and a description thereof will be omitted.

  A read operation when data “1” (suppression-mode) is stored in storage node SNT will be described. The operation from the precharge of the bit line to the rise of the word line is the same as in the second embodiment. The word driver in the row decoder raises the selected common word line WL (rises to Vdd) and turns on the access transistors M5 and M6. As a result, since the potential of the storage node SNT is a High (Vdd) potential, the access transistor M5 is in an off state (inactive state), and the potential of the bit line RBL does not change. On the other hand, the access transistor M6 is in the on state, and the storage node SNB of the memory cell MC is Low, so that the charge of the bit line WBL is discharged, and the potential of the bit line WBL decreases. When a current flows from the bit line WBL toward Vss in the memory cell MC, the potentials of the storage node SNB and the node NS rise. Since the leak suppression transistor M10 at this time has a diode-connected configuration, the potential of the node NS is clamped by the threshold voltage Vth10 of the leak suppression transistor M10. The storage node SNB also raises the potential at the same time, and turns off the access transistor M6 as the potential of the bit line WBL drops. As a result of these operations, the charge of the bit line WBL is not completely discharged, so that the current consumption in the read operation is more effective than that of the conventional cell.

  The read operation of data “0” (Read-Mode) is the same as that in the fourth embodiment, and a description thereof will be omitted.

Next, the mechanism and effect of the memory cell according to the present embodiment will be described.
As described above, the access transistor M6 is turned on in response to the rise of the word line WL in the read operation period during the suppression-mode, so that the charge of the bit line WBL is discharged through the memory cell MC. The diode connection configuration and the equivalent element of the diode at this time are the same as those in the second embodiment, and a description thereof will be omitted. Further, the mechanism for reducing the leakage current and the equivalent circuit in the data holding period during the suppression-mode are the same as those in the fourth embodiment, and a description thereof will be omitted.

  As described above, also in this embodiment, the operating current during the read operation can be reduced. In addition, this embodiment has an effect of reducing the leakage current flowing in the memory cell MC during the data holding period.

  The delay time of the bit line read signal from the rise of the word line is the same as in the fourth embodiment, and the description thereof is omitted here.

    FIG. 24 is an example showing current discharged from the bit line WBL to Vss in the memory cell for each device condition during the read operation. This figure shows values calculated by computer simulation using HSPICE. Here, the conditions of the memory cell MC are 1.1V condition and CC condition, 1.2V condition and FF condition, 1.0V condition and SS condition. In either case, the temperature is constant at 125 ° C. The discharge current flowing from the bit line WBL is an average current flowing into Vss in the memory cell in the period from the start of rising of the word line WL to the completion of falling. As shown in the table of FIG. 24, the 1.1V condition and the CC condition are about 7.9 μA in the conventional cell and 1.6 μA in the present embodiment (fifth embodiment), and the reduction rate is about 80%. It is. Further, in the 1.2V condition and the FF condition, the conventional cell is about 8.2 μA, and in the present embodiment, the current is 5.2 μA, and the reduction rate is about 37%. Further, in the 1.0V condition and the SS condition, the conventional cell has about 6.6 μA and the present embodiment has 0.6 μA, and the reduction rate is about 90%.

  29 to 31 are graphs showing the relationship between the temperature and the discharge current of the bit line WBL (including the second embodiment). The preconditions and symbols of these graphs are as described in the second embodiment. As shown in FIGS. 29 to 30, in the conventional cell, the discharge current of the bit line has almost no temperature dependence, and the change is 0.16 μA at the maximum. FIG. 29 shows 1.1V conditions and CC conditions. As a result of comparison with the conventional cell (square), the reduction rate of the discharge current Iss of the bit line in the memory cell MC of the present embodiment (triangle) is about 80% to 86%. FIG. 30 shows the 1.2V condition and FF condition, and the 1.2V condition and FS condition. As a result of comparison with conventional cells (white squares, black squares), the reduction rate of the discharge current Iss of the bit line in the memory cell MC of this embodiment (white triangles, black triangles) is about 38% to 46%, about 43% to 51%. FIG. 31 shows the 1.0V condition and SS condition, and the 1.2V condition and SF condition. As a result of comparison with the conventional cells (white squares, black squares), the reduction rate of the discharge current Iss of the bit line in the memory cell MC of this embodiment (white triangles, black triangles) is about 90% to 92%, about 87% to 90%.

  FIG. 32 is a graph summarizing the results of FIGS. 29 to 31 (including the second embodiment). This figure shows the bit line current under each device condition as a reduction rate based on the conventional cell. Further, the dependency is shown by setting the temperature as a parameter of 10 ° C. steps from 25 ° C. to 125 ° C. The preconditions and symbols of these graphs are as described in the second embodiment. From the above results, if the memory cell MC of the present embodiment is used, the discharge current Iss of the bit line WBL can be reduced by about 38% to 92% as compared with the conventional cell. In terms of current value, the discharge current of 6.6 μA to 8.7 μA in the conventional cell can be reduced to 0.56 μA to 5.0 μA in the present embodiment.

  As described above, since the read and write word lines are shared in this embodiment, two word drivers are not required for one memory cell, and one word is used unlike a conventional cell. Can be configured with a driver. As a result, the layout area can be reduced as compared with the fourth embodiment, and the leakage current and the operating current flowing in the unnecessary word driver can be reduced, so that the power consumption can be reduced. Also, the memory cell MC of the present embodiment has an effect of reducing the leakage current as compared with the conventional cell. Further, since the read current discharged from the bit line WBL to the memory cell MC during the read operation period can be reduced, there is an effect of reducing power consumption compared to the conventional cell. For these reasons, the current consumption of the semiconductor chip on which this embodiment is mounted is reduced. Thereby, the thermal runaway of the semiconductor chip (LSI) accompanying the increase in current consumption is suppressed, and the malfunction and stop of the system induced by the thermal runaway can be suppressed. In addition, the reliability of a system configured using this semiconductor chip (LSI) is improved.

  Each of the plurality of techniques described in the above embodiments can be applied to other embodiments as long as no technical contradiction occurs.

  Hereinafter, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 SRAM macro 3 Arithmetic processing circuit 4 Peripheral circuit MC, MHigh, MClow Memory cell M1, M2, M01, M02, M11, M12 Load transistor M3, M4, M03, M04, M13, M14 Driver transistor M5, M6, M05, M06, M15, M16 Access transistor M10, M11, M010, M011 Leakage suppression transistor RWL, WWL, WL Word line RBL, WBL Bit line

Claims (14)

A semiconductor device including an SRAM (Static Random Access Memory),
The SRAM is
First and second driver transistors of the second conductivity type;
First and second access transistors of the second conductivity type;
First and second load transistors of the first conductivity type;
First leakage suppression, wherein the second conductivity type transistor has a gate connected to a source of the second access transistor, a drain connected to a common source of the first and second driver transistors, and a source connected to a second power source. A transistor, and
The first access transistor has a drain connected to a read bit line and a gate connected to a read word line,
The second access transistor has a drain connected to a write bit line and a gate connected to a write word line. The semiconductor device according to claim 1,
A common drain of the first load transistor and the first driver transistor is connected to a common gate of the second load transistor and the second driver transistor;
A common drain of the second load transistor and the second driver transistor is connected to a common gate of the first load transistor and the first driver transistor;
A common source of the first and second load transistors is connected to a first power source;
A source of the first access transistor is connected to a common drain of the first load transistor and the first driver transistor;
A semiconductor device, wherein a source of the second access transistor is connected to a common drain of the second load transistor and the second driver transistor. The semiconductor device according to claim 1,
The absolute value of the threshold voltage of the first leak suppression transistor is lower than the absolute value of the threshold voltage of the first and second load transistors. The semiconductor device according to claim 1,
The write bit line is set to be equal to or higher than a potential of a first power supply connected to the common source of the first and second load transistors during a data read period or a data hold period. The semiconductor device according to claim 1,
The read bit line is set in a floating state during a data retention period. The semiconductor device according to claim 1,
The read word line and the write word line are the same semiconductor device. The semiconductor device according to claim 1,
A second leakage current transistor having a gate connected to the source of the first access transistor, a drain connected to the common source of the first and second load transistors, and a source connected to the first power supply; A semiconductor device further comprising a suppression transistor. The semiconductor device according to claim 7,
The read word line and the write word line are the same semiconductor device. A semiconductor device including an SRAM (Static Random Access Memory),
The SRAM is
First and second driver transistors of the second conductivity type;
First and second access transistors of the second conductivity type;
First and second load transistors of the first conductivity type;
A second leakage suppressing transistor, the first conductivity type transistor having a gate connected to a source of the first access transistor, a drain connected to a common source of the load transistor, and a source connected to a first power source; And
The first access transistor has a drain connected to a read bit line and a gate connected to a read word line,
The second access transistor has a drain connected to a write bit line and a gate connected to a write word line. The semiconductor device according to claim 9.
A common drain of the first load transistor and the first driver transistor is connected to a common gate of the second load transistor and the second driver transistor;
A common drain of the second load transistor and the second driver transistor is connected to a common gate of the first load transistor and the first driver transistor;
A common source of the first and second driver transistors is connected to a second power source;
A source of the first access transistor is connected to a common drain of the first load transistor and the first driver transistor;
A semiconductor device, wherein a source of the second access transistor is connected to a common drain of the second load transistor and the second driver transistor. The semiconductor device according to claim 9.
The read bit line is set in a floating state during a data retention period. The semiconductor device according to claim 9.
The absolute value of the threshold voltage of the second leak suppression transistor is lower than the absolute value of the threshold voltage of the first and second driver transistors. An operation method of a semiconductor device including an SRAM (Static Random Access Memory),
Here, the SRAM is
First and second driver transistors of the second conductivity type;
First and second access transistors of the second conductivity type;
First and second load transistors of the first conductivity type;
First leakage suppression, wherein the second conductivity type transistor has a gate connected to a source of the second access transistor, a drain connected to a common source of the first and second driver transistors, and a source connected to a second power source. A transistor, and
A common drain of the first load transistor and the first driver transistor is connected to a common gate of the second load transistor and the second driver transistor;
A common drain of the second load transistor and the second driver transistor is connected to a common gate of the first load transistor and the first driver transistor;
A common source of the first and second load transistors is connected to a first power source;
The first access transistor has a drain connected to a read bit line, a gate connected to a read word line, a source connected to the common drain of the first load transistor and the first driver transistor,
The second access transistor has a drain connected to a write bit line, a gate connected to a write word line, a source connected to a common drain of the second load transistor and the second driver transistor,
The operation method of the semiconductor device is as follows:
Setting the write bit line to be equal to or higher than the potential of the first power supply during a data read period or a data hold period;
A method for operating a semiconductor device, comprising: precharging the read bit line and the write bit line to a predetermined potential after the end of the data read period or the data hold period. The operation method of the semiconductor device according to claim 13,
A method of operating a semiconductor device, further comprising: setting the read bit line in a floating state during the data retention period.

Images