JP5343851B2 - Semiconductor evaluation circuit - Google Patents

Abstract

A semiconductor evaluation circuit is provided with a drain power supply line for supplying drain power supply to a drain terminal of one or a plurality of transistors to be measured, and a source power supply line for supplying source power supply to a source terminal. At least the drain terminal or the source terminal is connected to the corresponding drain power supply line or the source power supply line through a switching element which is turned on when the transistor to be measured is selected. The semiconductor evaluation circuit is provided with a reference voltage applying circuit for applying a prescribed reference voltage to at least the drain terminal or the source terminal of the unselected transistor to be measured.

Description

The present invention relates to a semiconductor evaluation circuit, and more particularly to a semiconductor evaluation circuit for evaluating the characteristics of a transistor under measurement which is a DUT (Device Under Test).
The present application claims priority based on Japanese Patent Application No. 2007-201922 filed in Japan on August 02, 2007 and Japanese Patent Application No. 2007-201923 filed on August 02, 2007 in Japan. The contents are incorporated herein.

  When developing micro processes for semiconductors, TEG (Test Element Group) consisting of elements of various dimensions is fabricated on a semiconductor wafer to evaluate and analyze the characteristics of micro elements (transistors, resistor elements, etc.) We are developing devices that can withstand mass production by setting process conditions based on the results. In the process development so far, the optimum process conditions and transistor structure could be set by evaluating and analyzing the characteristics of individual transistors fabricated in the TEG. Can no longer be ignored. In addition, the phenomenon that the stress applied to the transistor changes depending on the state of the transistor and the characteristics of the transistor change cannot be ignored.

  From such a situation, for example, in a fine process with a processing level of 45 nm, the characteristics of both transistors vary even if they are adjacent transistors. Therefore, a small signal such as SRAM (Static Random Access Memory) is transferred to a pair transistor (adjacent It is predicted that the detection circuit and the amplification circuit that detect with two transistors) have a reduced operating margin or become inoperable. In this case, sufficient data cannot be obtained only by evaluating individual transistors. Therefore, the characteristics of a large number of transistors are evaluated, analyzed by statistical processing, and systematic characteristic differences and characteristic differences due to variations are separated. A large-scale TEG that can be analyzed is required.

  Conventionally, as a TEG for performing large-scale element evaluation, for example, as shown in FIG. 9A, there is a DMA (Device Matrix Array) -TEG in which a plurality of transistors to be measured can be arranged and evaluated in a matrix of n rows and m columns ( Non-patent document 1).

The configuration of the DMA-TEG according to the prior art will be described below with reference to FIG. DUT11 to DUTnm are transistors to be measured. The drains of the transistors under measurement DUT11 to DUT1m are connected to the common drain line D1, and the sources are connected to the common source line S1.
The common drain line D1 is connected via a switch SW2 to a common drain force line (Drain Force) to which a drain voltage is supplied. In order to monitor the voltage of the common drain line D1, the drain voltage sense line DS1 is connected to the drain sense line (Drain Sense) via the switch SW1.

  The common source line S1 is connected to a common source power source (Source Force). Further, in order to monitor the voltage of the common source line S1, the common source line S1 is connected to the source sense line (Source Sense) via the switch SW3. The switches SW1 to SW3 are controlled by an output signal of a decoder (not shown).

  With these sets as one set, the transistors to be measured DUTn1 to DUTnm which are the n-th set are provided with the same connection as described above. The gates of the transistors under test DUT11 to DUTn1 are connected to the common gate line G1, and the gates of the transistors under test DUT1m to DUTnm are connected to the common gate line Gm.

Further, either the gate voltage VG1 or the gate non-selection voltage VGX is supplied to the common gate line G1 through the gate selection circuit 500. When the selection signal EN1 becomes high level (selected), the gate voltage VG1 is supplied to the gate line G1, and when the selection signal EN1 becomes low level (non-selected), the gate non-selection voltage VGX is supplied to the gate line G1. The gate non-selection voltage VGX is normally zero volts, but a negative voltage can be set as required.
With the DMA-TEG having such a configuration, the characteristics of m × n transistors DUT11 to DUTnm can be evaluated.

Here, since the m measured transistors DUT11 to DUT1m are connected in parallel to the common drain line D1, if each of the measured transistors has an off-leak current (current that flows without the transistor being completely turned off), Since a leak current flows through the non-selected transistor under measurement, the characteristics of the transistor under measurement to be measured cannot be accurately evaluated. In this case, for example, the gate non-selection voltage VGX is set to about −0.2 V so as to suppress the off-leak current. FIG. 9B is a circuit diagram of the switches SW1 to SW3.
Yoshiyuki Shimizu, MitsuoNakamura, Toshimasa Matsuoka, and Kenji Taniguchi, “Test structure for precise statistical characteristics measurement of MOSFETs”, IEEE 2002 Int. Conference on Microelectronic Test Structure (ICMTS 2002), pp. 49-54, April 2002

  In the above prior art, when a large-scale DMA-TEG, for example, m = n = 2048, that is, a TEG capable of evaluating 4M transistors, 2048 switches SW2 are connected to the drain force line. For example, when the measurement current of the transistor under measurement is set to about 1 mA, the transistor size of the switch SW2 requires W / L = 20 μm / 0.6 μm, and the total size of the 2048 switches SW2 is W = 20 μm × 2048 = 40960 μm. It becomes. When the off-leakage current flows about 0.1 pA per W = 1 μm, the leakage current flowing to the transistor of the non-selected switch SW2 is about 4 nA, and considering the variation, the measurement current of the transistor under measurement can be measured with high accuracy. There is a problem that you can not.

  In addition, for example, when the switches SW1, SW2, and SW3 are not selected, the common drain line D1 and the common source line S1 are in a floating state. Therefore, even if the off-leakage current of the switches SW1, SW2, and SW3 flows, it is constant. After a time, the common drain line D1 and the common source line S1 in a floating state are charged by the leakage current, and the off-leakage current does not flow automatically. However, since the transient current still flows, the measurement can be performed until it is stabilized. There is a problem that the characteristic evaluation time of the total transistor under measurement becomes long, or the quality determination of the transistor under measurement cannot be accurately performed.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a semiconductor evaluation circuit capable of shortening the characteristic evaluation time of a transistor under measurement and improving the characteristic evaluation accuracy.

  To achieve the above object, according to a first aspect of the present invention, a drain power supply line for supplying drain power to the drain terminal of one or a plurality of transistors under measurement and a source power supply to the source terminal are provided. And at least one of the drain terminal and the source terminal corresponding to the drain power line or the source power line corresponding to each via a switching element that is turned on when the transistor under measurement is selected. And a reference voltage application circuit that applies a predetermined reference voltage to at least one of the drain terminal and the source terminal of the non-selected transistor under measurement.

  According to a second aspect of the present invention, in the first aspect, the measured transistors are arranged in a matrix of n rows and m columns, provided for each row, and the measured transistors of each row N common drain lines connected to the drain terminals, provided for each row, n common source lines connected to the source terminals of the transistors under measurement in each row, provided for each column, M common gate lines, drain voltage detection lines, source voltage detection lines, gate power supply lines, and gate voltage detection lines connected to the gate terminals of the transistors under measurement are provided for each row, and are common to each row. N drain power source switching elements for switching connection / disconnection between the drain line and the drain power supply line, and connection / connection between the common drain line of each row and the drain voltage detection line provided for each row. N drain voltage detecting switching elements for switching connection, n source power switching elements provided for each row, for switching connection / disconnection between the common source line of each row and the source power supply line, and for each row N source voltage detection switching elements for switching connection / disconnection between the common source line of each row and the source voltage detection line, and the common gate line and the gate of each column provided for each column. M number of switching elements for gate power supply for switching connection / disconnection with the power supply line, and m number of switching elements provided for each column, for switching connection / disconnection between the common gate line in each column and the gate voltage detection line. Based on the address signal input from the host controller to select the gate voltage detection switching element and the transistor under measurement for characteristic evaluation, A drain selection switching circuit for outputting a row selection signal for turning on the drain power source switching element, the drain voltage detection switching element, the source power source switching element, and the source voltage detection switching element, and the address signal A column selection control circuit that outputs a column selection signal for turning on the gate power supply switching element and the gate voltage detection switching element of the column to be selected, and the reference voltage application circuit includes the A predetermined reference voltage is applied to the common drain line and the common source line in a non-selected row based on a logical inversion signal of a row selection signal.

  According to a third aspect of the present invention, in the second aspect, the reference voltage application circuit is provided for each row, a reference voltage supply line for supplying a predetermined reference voltage, and a common drain line for each row. And n drain reference voltage applying switching elements for switching connection / disconnection between the reference voltage supply line and the reference voltage supply line, provided for each row, and connecting / disconnecting the common source line of each row and the reference voltage supply line. N switching elements for applying a source reference voltage to be switched, and a logical inversion signal of a row selection signal output from the row selection control circuit provided for each row, and the drain reference voltage applying switching element and the source reference for each row A logic inversion circuit for outputting to the voltage applying switching element.

  According to a fourth aspect of the present invention, in any one of the second and third aspects, the drain power switching element is disposed at one end of the common drain line, and the drain voltage detection switching element is the common. The source power switching element is disposed at one end of the common source line, and the source voltage detection switching element is disposed at the other end of the common source line.

  According to a fifth aspect of the present invention, in any one of the second and third aspects, a gate reference voltage supply line for supplying a predetermined gate reference voltage and each column are provided. A gate reference voltage application switching element that switches connection / disconnection between a common gate line and the gate reference voltage supply line, and the column selection control circuit outputs a logical inversion signal of the column selection signal. Output to the gate reference voltage applying switching element.

  According to a sixth aspect of the present invention, in the fifth aspect, the transistor under measurement is a 1V-type low voltage MOS (Metal Oxide Semiconductor) transistor element, the drain power supply switching element, and the drain voltage detection. Switching element, source power source switching element, source voltage detection switching element, gate power source switching element, gate voltage detection switching element, drain reference voltage application switching element, source reference voltage application switching element The switching element for applying a gate reference voltage is a 3V high voltage MOS transistor element, and the row selection control circuit and the column selection control circuit are composed of 3V high voltage MOS transistor elements.

  According to a seventh aspect of the present invention, in the first aspect, the drain voltage detection line, the source voltage detection line, the gate power supply line, the gate voltage detection line, the first address line, An address line, a drain power source switching element for switching connection / disconnection between the drain terminal of the transistor to be measured and the drain power source line, and the one transistor to be measured A drain voltage detection switching element that switches connection / disconnection between the drain terminal of the transistor under measurement and the drain voltage detection line, and the one transistor under measurement. A source power switching element for switching connection / disconnection between a source terminal and the source power line, and the one A source voltage detection switching element for switching connection / disconnection between a source terminal of the transistor to be measured and the source voltage detection line, and the one transistor to be measured; A switching element for gate power supply for switching connection / disconnection between the gate terminal of the transistor under measurement and the gate power supply line, and the gate terminal of the transistor under measurement and the gate voltage provided for the one transistor under measurement. A switching element for detecting a gate voltage for switching connection / disconnection with a detection line and the one measured transistor, and the first address line and the second address for selecting the measured transistor Based on the address signal input via the line, the drain power switch A selection signal for turning on the switching element for detecting the switching element for the drain voltage detection, the switching element for the source power supply, the switching element for the source voltage detection, the switching element for the gate power supply, and the switching element for the gate voltage detection; A selection circuit, and the reference voltage application circuit applies a predetermined reference voltage to the drain terminal and the source terminal of the non-selected transistor under measurement based on a logic inversion signal of the selection signal.

  According to an eighth aspect of the present invention, in the seventh aspect, the reference voltage application circuit is provided for a reference voltage supply line for supplying a predetermined reference voltage and the one transistor under measurement. A drain reference voltage applying switching element for switching connection / disconnection between the drain terminal of the transistor under measurement and the reference voltage supply line, and a source terminal of the transistor under measurement provided for the one transistor under measurement. And a source reference voltage application switching element that switches connection / disconnection between the reference voltage supply line and the selection circuit, wherein the selection circuit outputs a logically inverted signal of the selection signal to the drain reference voltage application switching element and the source reference. Output to voltage application switching element.

  According to a ninth aspect of the present invention, in the eighth aspect, the transistor to be measured is a 1V system low voltage MOS (Metal Oxide Semiconductor) transistor element, the drain power supply switching element, and the drain voltage detection. Switching element, source power source switching element, source voltage detection switching element, gate power source switching element, gate voltage detection switching element, drain reference voltage application switching element, and source reference voltage application switching The element is a 3V high voltage MOS transistor element, and the selection circuit is composed of a 3V high voltage MOS transistor element.

  According to a tenth aspect of the present invention, in the eighth or ninth aspect, the drain power source switching element, the drain voltage detection switching element, the source power source switching element, the source voltage detection switching element, A combination of the switching element for gate power supply, the switching element for gate voltage detection, the switching element for application of drain reference voltage, the switching element for application of source reference voltage, and the selection circuit is used as an evaluation unit corresponding to one transistor to be measured. The plurality of evaluation units are arranged in a matrix.

  According to an eleventh aspect of the present invention, in the first aspect, the predetermined reference voltage is a ground level.

  According to a twelfth aspect of the present invention, in the first aspect, the predetermined reference voltage is a positive voltage.

  A thirteenth aspect according to the present invention is a semiconductor evaluation circuit in which one or a plurality of transistors under measurement and a selection circuit system for selecting one of the transistors under measurement are formed on the same semiconductor substrate. The measured transistor and the selection circuit system are formed on the semiconductor substrate by a well structure that is electrically separated, and the reference power supply voltage of the selection circuit system is applied to the well of the measured transistor. A value lower than the applied well voltage is set.

  According to a fourteenth aspect of the present invention, in the thirteenth aspect, the measured transistors are arranged in a matrix of n rows and m columns, provided for each row, and drain terminals of the measured transistors in each row. N common drain lines connected to each other, n common source lines provided for each row and connected to the source terminals of the transistors under measurement in each row, provided for each column, and each column under measurement M common gate lines connected to the gate terminal of the transistor, drain power supply lines, drain voltage detection lines, source power supply lines, source voltage detection lines, gate power supply lines, and gate voltage detection lines. The drain circuit is formed on the semiconductor substrate, and the selection circuit system is provided for each row, and n drain power supply transistors for switching connection / disconnection between the common drain line and the drain power supply line of each row. And n drain voltage detection transistors provided for each row and switching connection / disconnection between the common drain line of each row and the drain voltage detection line, and a common source line of each row provided for each row N source power supply transistors that switch connection / disconnection with the source power supply line, and n sources that are provided for each row and switch connection / disconnection between the common source line of each row and the source voltage detection line Voltage detection transistors, m gate power supply transistors provided for each column and switching connection / disconnection between the common gate line of each column and the gate power supply line, and provided for each column To select m gate voltage detection transistors for switching connection / disconnection between the common gate line and the gate voltage detection line, and a transistor to be measured for characteristic evaluation Row selection for turning on the drain power supply transistor, the drain voltage detection transistor, the source power supply transistor, and the source voltage detection transistor in a row to be selected based on an address signal input from a host controller A row selection control circuit for outputting a signal, and a column selection control circuit for outputting a column selection signal for turning on the gate power supply transistor and the gate voltage detection transistor of a column to be selected based on the address signal; The reference power supply voltage of the row selection control circuit and the column selection control circuit is set to a value lower than the well voltage applied to the well of the transistor under measurement.

  According to a fifteenth aspect of the present invention, in the fourteenth aspect, the drain power supply transistor is disposed at one end of the common drain line, and the drain voltage detection transistor is disposed at the other end of the common drain line. The source power supply transistor is disposed at one end of the common source line, and the source voltage detection transistor is disposed at the other end of the common source line.

  According to a sixteenth aspect of the present invention, in any one of the fourteenth and fifteenth aspects, a gate reference voltage supply line for supplying a predetermined gate reference voltage is provided for each column. A gate reference voltage application transistor that switches connection / disconnection between a common gate line and the gate reference voltage supply line; and the column selection control circuit outputs a logical inversion signal of the column selection signal Output to the gate reference voltage application transistor.

  According to a seventeenth aspect of the present invention, in the sixteenth solution, the transistor under measurement is a 1V low voltage MOS (Metal Oxide Semiconductor) transistor, the drain power supply transistor, the drain voltage detection transistor. The transistor, the source power supply transistor, the source voltage detection transistor, the gate power supply transistor, the gate voltage detection transistor, and the gate reference voltage application transistor are 3V high voltage MOS transistors, and the row selection The control circuit and the column selection control circuit are composed of 3V high voltage MOS transistors.

  According to an eighteenth aspect of the present invention, in the thirteenth aspect, a drain power supply line, a drain voltage detection line, a source power supply line, a source voltage detection line, a gate power supply line, a gate voltage detection line, A first address line and a second address line are formed on the semiconductor substrate, and the selection circuit system is provided for one measured transistor, and a drain terminal of the measured transistor A drain power supply transistor that switches connection / disconnection to / from the drain power supply line and the one transistor under measurement are connected / disconnected between the drain terminal of the transistor under measurement and the drain voltage detection line. A drain voltage detecting transistor to be switched, and a source terminal of the transistor under measurement provided for the one transistor under measurement; A source power supply transistor that switches connection / disconnection to / from the source power supply line and the one transistor under measurement are connected / disconnected between the source terminal of the transistor under measurement and the source voltage detection line. A source voltage detection transistor to be switched, a gate power transistor provided for the one transistor to be measured, for switching connection / disconnection between the gate terminal of the transistor to be measured and the gate power line, and the one transistor to be measured A gate voltage detection transistor for switching connection / disconnection between the gate terminal of the measured transistor and the gate voltage detection line, and the one measured transistor. In order to select a measurement transistor, the first address line and the second address are selected. Based on an address signal input via a loess line, the drain power supply transistor, the drain voltage detection transistor, the source power supply transistor, the source voltage detection transistor, the gate power supply transistor, and the gate voltage detection And a selection control circuit that outputs a selection signal for turning on the transistor for use, and sets the reference power supply voltage of the selection control circuit to a value lower than the well voltage applied to the well of the transistor under measurement. .

  According to a nineteenth aspect of the present invention, in the eighteenth aspect, the drain power transistor, the drain voltage detection transistor, the source power transistor, the source voltage detection transistor, the gate power transistor, A combination of a gate voltage detection transistor and the selection control circuit is used as an evaluation unit corresponding to one transistor to be measured, and a plurality of the evaluation units are arranged in a matrix of n rows and m columns.

  According to a twentieth aspect of the present invention, in the nineteenth aspect, a drain power supply pad for supplying drain power to the drain power line from the outside, and source power to the source power line are supplied from the outside. A source power supply pad for each column, a drain switch transistor for switching connection / disconnection between the drain power supply pad and the drain power supply line of each column, and a drain switch transistor provided for each column, A source switch transistor that switches connection / disconnection between the source power supply pad and the source power supply line of each column, and the gate terminal of the drain switch transistor and the source switch transistor is arranged in each column. It is connected to one of the corresponding first address line or second address line.

  According to a twenty-first aspect of the present invention, in the twentieth aspect, the transistor under measurement is a 1V-system low-voltage MOS transistor, the drain power supply transistor, the drain voltage detection transistor, and the source power supply. The transistor, the source voltage detection transistor, the gate power supply transistor, the gate voltage detection transistor, the drain switch transistor, and the source switch transistor are 3V high voltage MOS transistors, and the selection control circuit is 3V It is composed of a high voltage MOS transistor of the system.

  A drain power supply line for supplying drain power to the drain terminal of the transistor under measurement; and a source power supply line for supplying source power to the source terminal, wherein at least one of the drain terminal and the source terminal is: In the case of a semiconductor evaluation circuit connected to the drain power source line or the source power source line corresponding to each via a switching element that is turned on when the transistor under measurement is selected, the switching element is turned off when not selected. At least one of the drain terminal and the source terminal connected to the power supply line through the floating state becomes a floating state (leakage current is generated in the switching element). On the other hand, in the present invention, a predetermined reference voltage is applied to at least one of the drain terminal and the source terminal in the unselected transistor under measurement, that is, the drain terminal and / or the source terminal that is in a floating state when not selected. A reference voltage application circuit is provided. Thereby, it is possible to prevent the drain terminal or / and the source terminal of the transistor under measurement from being in a floating state at the time of non-selection, and as a result, it is possible to quickly stabilize the leakage current generated in the switching element. It is possible to shorten the characteristic evaluation time compared to the conventional case.

If the leakage current is to be stabilized, the drain terminal and the source terminal at the time of non-selection need only be prevented from being in a floating state, and the reference voltage at this time may be the ground level. Furthermore, by setting the reference voltage to a positive voltage, the switching element is completely turned off, and the occurrence of leakage current can be prevented. That is, the characteristic evaluation of the selected transistor under measurement can be performed with high accuracy, and the quality determination can be performed accurately.
As described above, according to the present invention, it is possible to reduce both the characteristic evaluation time of the transistor under measurement and improve the characteristic evaluation accuracy by setting the reference voltage.

  Furthermore, the present invention is a semiconductor evaluation circuit in which one or a plurality of transistors under measurement and a selection circuit system for selecting one of the transistors under measurement are formed on the same semiconductor substrate, The transistor under measurement and the selection circuit system are formed on the semiconductor substrate by a well structure that is electrically separated, and the reference voltage of the selection circuit system is applied to the well of the transistor under measurement. Set to a lower value. That is, since the drain terminal or the source terminal of the transistor under measurement in the non-selected state substantially matches the well voltage, the transistor under measurement and each power supply line are set by setting the reference power supply voltage of the selection circuit system to a value lower than the well voltage. Since the gate voltage when the switch transistor for connecting (drain force, source force) is not selected is lower than the well voltage, the off-leak current of the switch transistor can be reduced. Therefore, according to the present invention, it is possible to reduce both the characteristic evaluation time of the transistor under measurement and improve the characteristic evaluation accuracy.

It is a figure which shows the structure of the semiconductor evaluation circuit based on 1st Embodiment of this invention. It is a figure which shows the structure of the semiconductor evaluation circuit based on 2nd Embodiment of this invention. It is a schematic diagram which shows the cross-section of the semiconductor substrate in which the semiconductor evaluation circuit based on 2nd Embodiment of this invention was formed. It is a figure which shows the structure of the semiconductor evaluation circuit based on 3rd Embodiment of this invention. It is a figure which shows the structure of the semiconductor evaluation circuit based on 4th Embodiment of this invention. It is a figure which shows the structure of the semiconductor evaluation circuit based on 5th Embodiment of this invention. It is a detailed explanatory view of a semiconductor evaluation circuit according to a fifth embodiment of the present invention. It is an example of a voltage setting of the semiconductor evaluation circuit which concerns on 5th Embodiment of this invention. It is a figure which shows the structure of the conventional semiconductor evaluation circuit. FIG. 9B is a circuit diagram of switches SW1 to SW3 in FIG. 9A. It is a figure which shows the structure of the semiconductor evaluation circuit of the conventional complete separation type | mold Kelvin sense system.

Explanation of symbols

  DUT11 to DUTnm ... transistor under test, D1 to Dn ... common drain line, S1 to Sn ... common source line, SL1 to SLn ... selection signal line, G1 to Gm ... common gate line, DF ... drain force line, DS ... drain sense Line, SF ... Source force line, SS ... Source sense line, DSB ... Drain source bias line, GF ... Gate force line, GS ... Gate sense line, GB ... Gate bias line, 1 ... X address predecoder, XD1-XDn ... X address main decoder, XS1a to XSna ... first X address selection circuit, XS1b to XSnb ... second X address selection circuit, 2 ... Y address predecoder, YD1 to YDm ... Y address main decoder, YS1 to YSm ... Y address selection circuit, T10, T10 '... first transistor, T20, T20' ... first 2 transistors, T30, T30 '... 3rd transistor, T40, T40' ... 4th transistor, T50, T50 '... 5th transistor, T60, T60' ... 6th transistor, 100, 100 '... NAND circuit, 110, 110 '... inverter, XAd ... X address line, YAd ... Y address line, T70 ... seventh transistor, T80 ... eighth transistor, 120 ... drain switch transistor, 130 ... source switch transistor

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a circuit configuration diagram of the semiconductor evaluation circuit according to the first embodiment. The semiconductor evaluation circuit according to the first embodiment is a circuit for evaluating characteristics of measured transistors DUT11 to DUTnm (that is, DMA-TEG) arranged in a matrix of n rows and m columns, and these measured transistors DUT11 to DUTnm Assumes a 1V n-channel MOS (Metal Oxide Semiconductor) transistor fabricated by a 45 nm fine process.

  As shown in FIG. 1, the semiconductor evaluation apparatus according to the first embodiment includes n common drain lines D1 to Dn and common source lines S1 to S1 extending in the row direction (Y-axis direction of the XY coordinate system shown). Sn and selection signal lines SL1 to SLn, m common gate lines G1 to Gm extending in the column direction (X-axis direction orthogonal to the Y-axis direction), drain force lines (drain power supply lines) DF, and drain sense Line (drain voltage detection line) DS, source force line (source power supply line) SF, source sense line (source voltage detection line) SS, drain source bias line (reference voltage supply line) DSB, and gate force line ( (Gate power supply line) GF, gate sense line (gate voltage detection line) GS, gate bias line (gate reference voltage supply line) GB, X address predecoder 1 and n sets of X address memory. Decoders XD1 to XDn, n sets of first X address selection circuits XS1a to XSna, n sets of second X address selection circuits XS1b to XSnb, Y address predecoder 2, m sets of Y address main decoders YD1 to YDm, It is composed of m sets of Y address selection circuits YS1 to YSm.

  The X address predecoder 1 and the n sets of X address main decoders XD1 to XDn constitute a row selection control circuit in the present invention. The Y address predecoder 2 and the m sets of Y address main decoders YD1 to YDm The column selection control circuit in the invention is configured.

  The drain terminals of the transistors under measurement DUT11 to DUT1m arranged in the first row are connected to the common drain line D1, and the source terminals are connected to the common source line S1. The gate terminals of the transistors under test DUT11 to DUT1m are connected to the corresponding common gate lines G1 to Gm, respectively. The same applies to the connections of the transistors under measurement DUT21 to DUTnm from the second row to the nth row. That is, for example, the drain terminals of the transistors under test DUTn1 to DUTnm arranged in the nth row are connected to the common drain line Dn, the source terminals are connected to the common source line Sn, and the gate terminals are respectively corresponding to the common terminals. It is connected to the gate lines G1 to Gm.

  The first X address selection circuit XS1a on the first row includes a first transistor (drain power switching element, drain power transistor) T1-1 and a second transistor (source voltage detection switching element, source voltage detection transistor) T2-. The first transistor T1-1 and the second transistor T2-1 are 3V type n-channel MOS transistors having stable characteristics. The source terminal of the first transistor T1-1 is connected to one end of the common drain line D1, the drain terminal is connected to the drain force line DF, the gate terminal is one end of the selection signal line SL1, and the gate terminal of the second transistor T2-1. And the X address main decoder XD1. The source terminal of the second transistor T2-1 is connected to one end of the common source line S1, the drain terminal is connected to the source sense line SS, the gate terminal is one end of the selection signal line SL1, and the gate terminal of the first transistor T1-1. And the X address main decoder XD1.

  The circuit configurations of the first X address selection circuit XS2a to the first X address selection circuit XSna in the second to nth rows are the same. That is, for example, the first X address selection circuit XSna in the n-th row includes the first transistor T1-n and the second transistor T2-n. The source terminal of the first transistor T1-n is connected to one end of the common drain line Dn, the drain terminal is connected to the drain force line DF, the gate terminal is one end of the selection signal line SLn, and the gate terminal of the second transistor T2-n. And an X address main decoder XDn. The source terminal of the second transistor T2-n is connected to one end of the common source line Sn, the drain terminal is connected to the source sense line SS, the gate terminal is one end of the selection signal line SLn, and the gate terminal of the first transistor T1-n. And an X address main decoder XDn.

  The second X address selection circuit XS1b in the first row includes a third transistor (drain voltage detecting switching element) T3-1, a fourth transistor (source power switching element) T4-1, and a fifth transistor (for applying a drain reference voltage). A switching element T5-1, a sixth transistor (source reference voltage applying switching element) T6-1, and an inverter (logic inversion circuit) IV1-1. The third transistor T3-1, the fourth transistor T4-1, the fifth transistor T5-1, and the sixth transistor T6-1 are 3V-type n-channel MOS transistors with stable characteristics, and the inverter IV1-1 is also included. It is composed of a 3V MOS transistor manufactured by the same process.

  The drain terminal of the third transistor T3-1 is connected to the drain sense line DS, the source terminal is connected to the other end of the common drain line D1 and the source terminal of the fifth transistor T5-1, and the gate terminal is connected to the selection signal line SL1. The other end, the input terminal of the inverter IV1-1, and the gate terminal of the fourth transistor T4-1 are connected. The drain terminal of the fourth transistor T4-1 is connected to the source force line SF, the source terminal is connected to the other end of the common source line S1 and the source terminal of the sixth transistor T6-1, and the gate terminal is connected to the selection signal line SL1. The other end is connected to the input end of the inverter IV1-1 and the gate terminal of the third transistor T3-1.

  The drain terminal of the fifth transistor T5-1 is connected to the drain-source bias line DSB, the source terminal is connected to the other end of the common drain line D1 and the source terminal of the third transistor T3-1, and the gate terminal is connected to the inverter IV1-1. Connected to the output end of the. The drain terminal of the sixth transistor T6-1 is connected to the drain source bias line DSB, the source terminal is connected to the other end of the common source line S1 and the source terminal of the fourth transistor T4-1, and the gate terminal is connected to the inverter IV1-1. Connected to the output end of the. The inverter IV1-1 is a logic inversion circuit, and has an input terminal connected to the other end of the selection signal line SL1, and an output terminal connected to the gate terminals of the fifth transistor T5-1 and the sixth transistor T6-1. Yes.

  The circuit configurations of the second X address selection circuit XS2b to the second X address selection circuit XSnb from the second row to the nth row are the same. That is, for example, the second X address selection circuit XSnb in the n-th row includes a third transistor T3-n, a fourth transistor T4-n, a fifth transistor T5-n, a sixth transistor T6-n, and an inverter IV1-n. Has been.

  The drain terminal of the third transistor T3-n is connected to the drain sense line DS, the source terminal is connected to the other end of the common drain line Dn and the source terminal of the fifth transistor T5-n, and the gate terminal is connected to the selection signal line SLn. The other end, the input end of the inverter IV1-n, and the gate terminal of the fourth transistor T4-n are connected. The drain terminal of the fourth transistor T4-n is connected to the source force line SF, the source terminal is connected to the other end of the common source line Sn and the source terminal of the sixth transistor T6-n, and the gate terminal is connected to the selection signal line SLn. The other end is connected to the input end of the inverter IV1-n and the gate terminal of the third transistor T3-n.

  The drain terminal of the fifth transistor T5-n is connected to the drain-source bias line DSB, the source terminal is connected to the other end of the common drain line Dn and the source terminal of the third transistor T3-n, and the gate terminal is the inverter IV1-n. Connected to the output end of the. The drain terminal of the sixth transistor T6-n is connected to the drain source bias line DSB, the source terminal is connected to the other end of the common source line Sn and the source terminal of the fourth transistor T4-n, and the gate terminal is the inverter IV1-n. Connected to the output end of the. The input end of the inverter IV1-n is connected to the other end of the selection signal line SLn, and the output end is connected to the gate terminals of the fifth transistor T5-n and the sixth transistor T6-n.

  The X address main decoder XD1 in the first row responds to the X selection control signal input from the X address predecoder 1 to the first transistor T1-1, the second transistor T2-1, the third transistor T3-1, and the first transistor T3-1. An X selection signal (row selection signal) for turning ON / OFF the four transistors T4-1 is output to one end of the selection signal line SL1 (the gate terminals of the first transistor T1-1 and the second transistor T2-1). Specifically, the X address main decoder XD1 receives the X selection control signal from the X address predecoder 1 and outputs a NAND signal of the X selection control signal. The inverter IV2-1 outputs a logically inverted signal of the product signal as an X selection signal. The NAND circuit 10-1 and the inverter IV2-1 are composed of 3V MOS transistors having stable characteristics.

  The circuit configurations of the X address main decoders XD2 to XDn main decoder XDn in the second to nth rows are the same. That is, for example, the X address main decoder XDn in the n-th row responds to the X selection control signal input from the X address predecoder 1 to the first transistor T1-n, the second transistor T2-n, and the third transistor T3. -X and an X selection signal for turning ON / OFF the fourth transistor T4-n are output to one end of the selection signal line SLn (the gate terminals of the first transistor T1-n and the second transistor T2-n). Specifically, the X address main decoder XDn receives the X selection control signal from the X address predecoder 1 and outputs a NAND signal of the X selection control signal. The inverter IV2-n outputs a logically inverted signal of the product signal as an X selection signal.

The X address predecoder 1 generates an X selection control signal based on an X address signal input from a host controller (not shown) and outputs it to the X address main decoders XD1 to XDn.
Here, the X address signal is a signal indicating an X coordinate (row direction) address of a transistor under measurement whose characteristics are to be evaluated.

  The Y address selection circuit YS1 in the first column includes a seventh transistor (switching element for gate power supply) T7-1, an eighth transistor (switching element for detecting gate voltage) T8-1, and a ninth transistor (switching for applying a gate reference voltage). Element) T9-1. These are 3V type n-channel MOS transistors having stable characteristics. The source terminal of the seventh transistor T7-1 is connected to one end of the common gate line G1, the drain terminal is connected to the gate force line GF, the gate terminal is the gate terminal of the eighth transistor 8-1, and the Y address main decoder YD1 ( Specifically, it is connected to the output terminal of the inverter IV3-1. The source terminal of the eighth transistor T8-1 is connected to one end of the common gate line G1, the drain terminal is connected to the gate sense line GS, the gate terminal is the gate terminal of the seventh transistor T7-1, and the Y address main decoder YD1 ( Specifically, it is connected to the output terminal of the inverter IV3-1. The ninth transistor T9-1 has a source terminal connected to one end of the common gate line G1, a drain terminal connected to the gate bias line GB, and a gate terminal connected to the Y address main decoder YD1 (specifically, an input terminal of the inverter IV3-1). ).

  The circuit configurations of the Y address selection circuits YS2 to YSm from the second column to the mth column are the same. That is, for example, the Y address selection circuit YSm in the m-th column includes the seventh transistor T7-m, the eighth transistor T8-m, and the ninth transistor 9-m. The source terminal of the seventh transistor T7-m is connected to one end of the common gate line Gm, the drain terminal is connected to the gate force line GF, and the gate terminal is the gate terminal of the eighth transistor T8-m and the Y address main decoder YDm ( Specifically, it is connected to the output terminal of the inverter IV3-m. The source terminal of the eighth transistor T8-m is connected to one end of the common gate line Gm, the drain terminal is connected to the gate sense line GS, the gate terminal is the gate terminal of the seventh transistor 7-m and the Y address main decoder YDm ( Specifically, it is connected to the output terminal of the inverter IV3-m. The ninth transistor T9-m has a source terminal connected to one end of the common gate line Gm, a drain terminal connected to the gate bias line GB, and a gate terminal connected to the Y address main decoder YDm (specifically, an input terminal of the inverter IV3-m). ).

  The Y address main decoder YD1 in the first column selects Y for turning on / off the seventh transistor T7-1 and the eighth transistor T8-1 in accordance with the Y selection control signal input from the Y address predecoder 2. A signal (column selection signal) is output to the gate terminals of the seventh transistor T7-1 and the eighth transistor T8-1, and a Y selection inversion signal (Y selection signal for turning on / off the ninth transistor T9-1) Is output to the gate terminal of the ninth transistor T9-1. Specifically, the Y address main decoder YD1 receives the Y selection control signal from the Y address predecoder 2 and outputs a NAND signal of the Y selection control signal, and the NAND logic. The inverter IV3-1 outputs a logically inverted signal of the product signal as a Y selection signal. Since the input terminal of the inverter IV3-1 is connected to the gate terminal of the ninth transistor T9-1, a Y selection inversion signal that is a logic inversion signal of the Y selection signal is supplied to the gate terminal of the ninth transistor T9-1. Is output.

  The circuit configuration of the Y address main decoders YD2 to YDm from the second column to the mth column is the same. That is, for example, the Y address main decoder YDm in the m-th column turns on / off the seventh transistor T7-m and the eighth transistor T8-m according to the Y selection control signal input from the Y address predecoder 2. A Y selection signal for outputting to the gate terminals of the seventh transistor T7-m and the eighth transistor T8-m and a Y selection inversion signal for turning on / off the ninth transistor T9-m are output to the ninth transistor T9. Output to -m gate terminal. Specifically, the Y address main decoder YDm receives the Y selection control signal from the Y address predecoder 2 and outputs a NAND signal of the Y selection control signal. The inverter IV3-m outputs a logically inverted signal of the product signal as a Y selection signal.

The Y address predecoder 2 generates a Y selection control signal based on a Y address signal input from a host controller (not shown), and outputs it to the Y address main decoders YD1 to YDm.
Here, the Y address signal is a signal indicating the address of the Y coordinate (column direction) of the transistor under measurement whose characteristics are to be evaluated.

  The drain force line DF is a wiring for supplying a drain voltage to the selected transistors under test DUT11 to DUTnm, and one end of the drain force line DF is connected to a drain force pad DFP connected to a drain voltage supply device (not shown). The drain sense line DS is a wiring for detecting the drain voltage of the selected transistors under measurement DUT11 to DUTnm, and a drain sense pad DSP connected to a drain voltage detector (not shown) is connected to one end of the drain sense line DS. .

  The source force line SF is a wiring for supplying a source voltage to the selected transistors under test DUT11 to DUTnm, and one end of the source force line SF is connected to a source force pad SFP connected to a source voltage supply device (not shown). The source sense line SS is a wiring for detecting the source voltage of the selected transistors under measurement DUT11 to DUTnm, and a source sense pad SSP connected to a source voltage detector (not shown) is connected to one end of the source sense line SS. .

  The drain source bias line DSB is a wiring for supplying a predetermined bias voltage (reference voltage) to the non-selected common drain lines D1 to Dn and the common source lines S1 to Sn, and one end thereof is a drain source bias voltage (not shown). A drain source bias pad DSBP connected to the supply device is connected.

  The gate force line GF is a wiring for supplying a gate voltage to the selected transistors under test DUT11 to DUTnm, and one end of the gate force line GF is connected to a gate force pad GFP connected to a gate voltage supply device (not shown). The gate sense line GS is a wiring for detecting the gate voltage of the selected transistors under test DUT11 to DUTnm, and a gate sense pad GSP connected to a gate voltage detector (not shown) is connected to one end of the gate sense line GS. . The gate bias line GB is a wiring for supplying a gate bias voltage to the gate terminals of the non-selected transistors DUT11 to DUTnm that are not selected, and a gate bias pad GBP connected to a gate bias voltage supply device (not shown) at one end thereof. Is connected.

  As shown in FIG. 1, the third transistor T3-1, which is a switch for connecting to the drain sense line DS, has a common drain line D1 with respect to the first transistor T1-1, which is a switch for connecting to the drain force line DF. It is desirable to provide it on the opposite side. By adopting such an arrangement relationship, for example, when DUT 11 is selected, the drain force line DF passes through the first transistor T1-1, the common drain line D1 passes through the DUT 11 and the common source line S1, A current flows through the fourth transistor T4-1 to the source force line SF, and the current flowing from the DUT 11 to the drain sense line DS through the third transistor T3-1 can be eliminated. Since the voltage drop due to the resistance component of the common drain line D1 up to the three transistors T3-1 does not occur, the drain voltage can be detected with high accuracy. Similarly, the second transistor T2-1 that is a switch for connection to the source sense line SS is on the opposite side of the common source line S1 with respect to the fourth transistor T4-1 that is a switch for connection to the source force line SF. It is desirable to provide it.

Next, the operation of the semiconductor evaluation circuit according to the first embodiment configured as described above will be described.
First, the host controller outputs an X address signal for selecting the transistor under test DUT 11 to the X address predecoder 1 and outputs a Y address signal to the Y address predecoder 2. As a result, the X address predecoder 1 outputs an X selection control signal to the X address main decoder XD1 in the first row, and the X address main decoder XD1 responds to the X selection control signal by the first transistor T1- 1. An X selection signal (“1”) for turning on the second transistor T2-1, the third transistor T3-1, and the fourth transistor T4-1 is output to one end of the selection signal line SL1.

  As a result, the first transistor T1-1, the second transistor T2-1, the third transistor T3-1, and the fourth transistor T4-1 in the first row are turned on, and the common drain line D1 in the first row is a drain force line. The common source line S1 is connected to the DF and the drain sense line DS, and the common source line S1 is connected to the source force line SF and the source sense line SS. At this time, since the fifth transistor T5-1 and the sixth transistor T6-1 are turned off, the common drain line D1 and the common source line S1 in the first row are not connected to the drain source bias line DSB (non-conduction).

  On the other hand, the Y address predecoder 2 outputs a Y selection control signal to the Y address main decoder YD1 in the first column, and the Y address main decoder YD1 responds to the Y selection control signal by the seventh transistor T7-1. A Y selection signal (“1”) for turning on the eighth transistor T8-1 is output to the gate terminals of the seventh transistor T7-1 and the eighth transistor T8-1, and the ninth transistor T9-1 is turned on. A Y selective inversion signal (“0”) for turning OFF is output to the gate terminal of the ninth transistor T9-1.

  As a result, the seventh transistor T7-1 and the eighth transistor T8-1 are turned on, and the common gate line G1 in the first column is connected to the gate force line GF and the gate sense line GS. At this time, since the ninth transistor T9-1 is turned off, the common gate line G1 in the first column is not connected to the gate bias line GB.

  At this time, the circuits from the second row to the n-th row are in a non-selected state, and the operation is opposite to that of the first row circuit. In other words, when the circuit in the n-th row is used as a representative example, the first transistor T1-n, the second transistor T2-n, the third transistor T3-n, and the fourth transistor T4-n in the n-th row are turned off. The n-th common drain line Dn is not connected to the drain force line DF and the drain sense line DS, and the common source line Sn is not connected to the source force line SF and the source sense line SS. At this time, since the fifth transistor T5-n and the sixth transistor T6-n are turned on, the n-th common drain line Dn and the common source line Sn are connected to the drain-source bias line DSB.

  Further, the circuits in the second column to the m-th column are also in a non-selected state, and the operation is the opposite of the circuit in the first column. That is, when the circuit in the m-th column is representatively described, the seventh transistor T7-m and the eighth transistor T8-m in the m-th column are turned off, and the common gate line Gm in the m-th column is the gate force line GF. Although not connected to the gate sense line GS, the ninth transistor T9-1 is turned on, so that the common gate line Gm is connected to the gate bias line GB.

  With this operation, only the transistor under test DUT11 is selected, the drain voltage is supplied to the drain force line DF, the source voltage is supplied to the source force line SF, and the gate voltage is supplied to the gate force line GF. As a result, the transistor under test DUT11 is driven to detect the drain voltage generated in the drain sense line DS (drain sense pad DSP) and the source voltage generated in the source sense line SS (source sense pad SSP), the gate sense line GS (gate By detecting the gate voltage generated at the sense pad GSP), the characteristics of the transistor under test DUT11 are evaluated.

  Here, by supplying a gate bias voltage of −0.2 V to the gate bias line GB, a gate bias voltage of −0.2 V is applied to the gate terminals of the transistors DUT12 to DUTnm in the non-selected state, The unselected transistors under measurement DUT12 to DUTnm are completely turned off, and no leakage current flows from the unselected transistors under measurement DUT12 to DUTnm.

  On the other hand, by supplying a bias voltage to the drain source bias line DSB and applying a bias voltage to the common drain lines D2 to Dn and the common source lines S2 to Sn in the second to nth rows in the non-selected state, It is possible to prevent the common drain lines D2 to Dn and the common source lines S2 to Sn in the non-selected state from entering a floating state. Thereby, the first transistors T1-2 to T1-n, the second transistors T2-2 to T2-n, the third transistors T3-2 to T3-n, and the fourth transistor T4-2 in the non-selected state (OFF state). Since the leakage current flowing through .about.T4-n can be stabilized at an early stage, the characteristic evaluation time can be shortened as compared with the conventional case. If the leakage current is to be stabilized, it is only necessary to prevent the common drain line and common source line in the non-selected state from floating, so that the bias voltage supplied to the drain source bias line DSB at this time is the ground level. But it ’s okay.

  Further, for example, by setting the bias voltage supplied to the drain-source bias line DSB to a positive voltage of about +0.2 V, the first transistors T1-2 to T1-n and the second transistors T2-2 to T2 in the non-selected state are set. -N, the source voltages of the third transistors T3-2 to T3-n and the fourth transistors T4-2 to T4-n are +0.2 V and the gate voltage is 0 V, and these transistors are completely turned off, and the leakage current Can be prevented. That is, the characteristic evaluation of the selected transistor under test DUT11 can be performed with high accuracy, and the quality determination can be performed accurately. The bias voltage supplied to the drain-source bias line DSB may be set to a voltage value that does not cause leakage current within a range not exceeding 1V.

  Further, in the above description, the case where the transistor under test DUT11 is selected has been described. However, since the other transistors under test DUT12 to DUTnm are sequentially selected and evaluated for characteristics, according to the first embodiment. According to the semiconductor evaluation circuit, the total characteristic evaluation time can be shortened and the characteristic evaluation accuracy can be improved as compared with the conventional circuit.

[Second Embodiment]
FIG. 2 is a circuit configuration diagram of a semiconductor evaluation circuit according to the second embodiment. In the following, differences from the semiconductor evaluation apparatus according to the first embodiment will be described.

  The second X address selection circuit XS1b in the first row includes a third transistor (drain voltage detection transistor) T3-1 and a fourth transistor (source power transistor) T4-1. The third transistor T3-1 and the fourth transistor T4-1 are 3V type n-channel MOS transistors having stable characteristics. The drain terminal of the third transistor T3-1 is connected to the drain sense line DS, the source terminal is connected to the other end of the common drain line D1, and the gate terminal is connected to the other end of the selection signal line SL1 and the fourth transistor T4-1. Connected to the gate terminal. The drain terminal of the fourth transistor T4-1 is connected to the source force line SF, the source terminal is connected to the other end of the common source line S1, and the gate terminal is connected to the other end of the selection signal line SL1 and the third transistor T3-1. Connected to the gate terminal.

  The circuit configurations of the second X address selection circuit XS2b to the second X address selection circuit XSnb from the second row to the nth row are the same. That is, for example, the second X address selection circuit XSnb in the n-th row includes a third transistor T3-n and a fourth transistor T4-n. The third transistor T3-n has a drain terminal connected to the drain sense line DS, a source terminal connected to the other end of the common drain line Dn, a gate terminal connected to the other end of the selection signal line SLn, and the fourth transistor T4-n. Connected to the gate terminal. The drain terminal of the fourth transistor T4-n is connected to the source force line SF, the source terminal is connected to the other end of the common source line Sn, the gate terminal is connected to the other end of the selection signal line SLn, and the third transistor T3-n. Connected to the gate terminal.

  The Y address selection circuit YS1 in the first column includes a fifth transistor (gate power supply transistor) T5-1, a sixth transistor (gate voltage detection transistor) T6-1, and a seventh transistor (gate reference voltage application transistor) T7. −1, which are 3V type n-channel MOS transistors with stable characteristics. The source terminal of the fifth transistor T5-1 is connected to one end of the common gate line G1, the drain terminal is connected to the gate force line GF, the gate terminal is the gate terminal of the sixth transistor T6-1, and the Y address main decoder YD1 ( Specifically, it is connected to the output terminal of the inverter IV3-1. The sixth transistor T6-1 has a source terminal connected to one end of the common gate line G1, a drain terminal connected to the gate sense line GS, a gate terminal connected to the gate terminal of the fifth transistor T5-1, and a Y address main decoder YD1 ( Specifically, it is connected to the output terminal of the inverter IV3-1. The seventh transistor T7-1 has a source terminal connected to one end of the common gate line G1, a drain terminal connected to the gate bias line GB, and a gate terminal connected to the Y address main decoder YD1 (specifically, an input terminal of the inverter IV3-1). ).

  The circuit configurations of the Y address selection circuits YS2 to YSm from the second column to the mth column are the same. That is, for example, the Y address selection circuit YSm in the m-th column is composed of a fifth transistor T5-m, a sixth transistor T6-m, and a seventh transistor T7-m. The source terminal of the fifth transistor T5-m is connected to one end of the common gate line Gm, the drain terminal is connected to the gate force line GF, the gate terminal is the gate terminal of the sixth transistor T6-m, and the Y address main decoder YDm ( Specifically, it is connected to the output terminal of the inverter IV3-m. The source terminal of the sixth transistor T6-m is connected to one end of the common gate line Gm, the drain terminal is connected to the gate sense line GS, the gate terminal is the gate terminal of the fifth transistor T5-m and the Y address main decoder YDm ( Specifically, it is connected to the output terminal of the inverter IV3-m. The seventh transistor T7-m has a source terminal connected to one end of the common gate line Gm, a drain terminal connected to the gate bias line GB, and a gate terminal connected to the Y address main decoder YDm (specifically, an input terminal of the inverter IV3-m). ).

  The Y address main decoder YD1 in the first column selects Y for turning on / off the fifth transistor T5-1 and the sixth transistor T6-1 in accordance with the Y selection control signal input from the Y address predecoder 2. A signal (column selection signal) is output to the gate terminals of the fifth transistor T5-1 and the sixth transistor T6-1, and a Y selection inversion signal (Y selection signal for turning on / off the seventh transistor T7-1) Is output to the gate terminal of the seventh transistor T7-1. Specifically, the Y address main decoder YD1 receives the Y selection control signal from the Y address predecoder 2 and outputs a NAND signal of the Y selection control signal, and the NAND logic. The inverter IV3-1 outputs a logically inverted signal of the product signal as a Y selection signal. Since the input terminal of the inverter IV3-1 is connected to the gate terminal of the seventh transistor T7-1, a Y selection inversion signal that is a logic inversion signal of the Y selection signal is supplied to the gate terminal of the seventh transistor T7-1. Is output.

  The circuit configuration of the Y address main decoders YD2 to YDm from the second column to the mth column is the same. That is, for example, the Y address main decoder YDm in the m-th column turns on / off the fifth transistor T5-m and the sixth transistor T6-m in accordance with the Y selection control signal input from the Y address predecoder 2. A Y selection signal for outputting to the gate terminals of the fifth transistor T5-m and the sixth transistor T6-m and a Y selection inversion signal for turning on / off the seventh transistor T7-m are output to the seventh transistor T7. Output to -m gate terminal. Specifically, the Y address main decoder YDm receives the Y selection control signal from the Y address predecoder 2 and outputs a NAND signal of the Y selection control signal. The inverter IV3-m outputs a logically inverted signal of the product signal as a Y selection signal.

  X-address predecoder 1, X-address main decoders XD1-XDn, first X-address selection circuit XS1a, which is a selection circuit system composed of measured transistors DUT11-DUTnm, which are 1-V MOS transistors, and 3-V MOS transistors To XSna, second X address selection circuits XS1b to XSnb, Y address predecoder 2, Y address main decoders YD1 to YDm, and Y address selection circuits YS1 to YSm are formed on the same semiconductor substrate.

  FIG. 3 is a diagram schematically showing a cross-sectional structure of a transistor under measurement and a selection circuit system formed on the same semiconductor substrate. As shown in FIG. 3, in this embodiment, on a P-type semiconductor substrate (P-sub) 30, a well structure that constitutes a 1V MOS transistor that is a transistor to be measured, and a 3V system that is a selection circuit system. A well structure constituting a MOS transistor is used.

  In a region where a transistor to be measured is formed, a P-well (PW) 32 and a 1V system for producing a 1V type N-type MOS transistor in a Deep-Nwell (DNW) 31 formed on the P-sub 30. N-well (NW) 33 for manufacturing the P-type MOS transistor is formed. A source region 32S and a drain region 32D are formed in the PW 32. A source terminal PS is connected to the source region 32S, and a drain terminal PD is connected to the drain region 32D. A source region 33S and a drain region 33D are formed in the NW 33. A source terminal PS is connected to the source region 33S, and a drain terminal PD is connected to the drain region 33D.

  In this embodiment, since an N-type MOS transistor is assumed as the transistor under measurement, the source terminal PS of the source region 32S in the PW 32 is connected to the common source line, and the drain terminal PD of the drain region 32D is connected to the common drain line. Connected. Although not shown in FIG. 2, the well voltage VPW is applied to the PW32 of the N-type MOS transistor. When a P-type MOS transistor is used as the transistor under measurement, the source terminal PS of the source region 33S in the NW 33 is connected to the common source line, and the drain terminal PD of the drain region 33D is connected to the common drain line. The well voltage VNW is applied to NW33 of the P-type MOS transistor. The well voltage VNW of the NW 33 and the well voltage VDNW applied to the DNW 31 are set to the same potential.

  On the other hand, in the selection circuit system, on the P-sub 30, a high voltage P-well (HPW) 34 for producing a 3V N-type MOS transistor and a high voltage for producing a 3V P-type MOS transistor are formed. A voltage N-well (HNW) 35 is formed. A source region 34S and a drain region 34D are formed in the HPW 34, and a source region 35S and a drain region 35D are formed in the HNW 35. The HPW 34, the source region 34S, and the P-sub 30 of the N-type MOS transistor are commonly connected to VSS (reference power supply voltage) of the selection circuit system. The HNW 35 of the P-type MOS transistor and the source region 35S are commonly connected to VDD of the selection circuit system.

  By adopting such a structure, the well of the transistor under measurement and the well of the selection circuit system can be electrically separated, so that different voltages can be applied to each well. In this embodiment, VPW = 0V, VNW = VDNW = 1.0V, Vsub (applied voltage of P-sub30) = VHPW (applied voltage of HPW34) = VSS = −0.5V, VHNW (applied voltage of HNW35) = Let VDD = 3.3V. That is, as shown in FIG. 1, the VDD of the X address predecoder 1, the X address main decoders XD1 to XDn, the Y address predecoder 2, and the Y address main decoders YD1 to YDm, which are selection circuit systems, is 3.3V, and VSS is -0.5V.

Next, the operation of the semiconductor evaluation circuit according to the second embodiment configured as described above will be described.
First, the host controller outputs an X address signal for selecting the transistor under test DUT 11 to the X address predecoder 1 and outputs a Y address signal to the Y address predecoder 2. As a result, the X address predecoder 1 outputs an X selection control signal to the X address main decoder XD1 in the first row, and the X address main decoder XD1 responds to the X selection control signal by the first transistor T1- 1. An X selection signal (high level signal) for turning on the second transistor T2-1, the third transistor T3-1, and the fourth transistor T4-1 is output to one end of the selection signal line SL1.

  As a result, the first transistor T1-1, the second transistor T2-1, the third transistor T3-1, and the fourth transistor T4-1 in the first row are turned on, and the common drain line D1 in the first row is a drain force line. The common source line S1 is connected to the DF and the drain sense line DS, and the common source line S1 is connected to the source force line SF and the source sense line SS.

  On the other hand, the Y address predecoder 2 outputs a Y selection control signal to the Y address main decoder YD1 in the first column, and the Y address main decoder YD1 outputs the fifth transistor T5-1 in accordance with the Y selection control signal. A Y selection signal (high level signal) for turning on the sixth transistor T6-1 is output to the gate terminals of the fifth transistor T5-1 and the sixth transistor T6-1, and the seventh transistor T7-1 is turned on. A Y selective inversion signal (low level signal) for turning OFF is output to the gate terminal of the seventh transistor T7-1.

  As a result, the fifth transistor T5-1 and the sixth transistor T6-1 are turned ON, and the common gate line G1 in the first column is connected to the gate force line GF and the gate sense line GS. At this time, since the seventh transistor T7-1 is turned off, the common gate line G1 in the first column is not connected to the gate bias line GB.

  At this time, the circuits from the second row to the n-th row are in a non-selected state, and the operation is opposite to that of the first row circuit. That is, the description will be made using the circuit in the n-th row as a representative. The X-address main decoder XDn in the n-th row outputs the X selection signal (low level signal), so that the first transistor T1-n in the n-th row, The second transistor T2-n, the third transistor T3-n, and the fourth transistor T4-n are turned off, and the common drain line Dn in the n-th row is not connected to the drain force line DF and the drain sense line DS. Sn is not connected to the source force line SF and the source sense line SS.

  Further, the circuits in the second column to the m-th column are also in a non-selected state, and the operation is the opposite of the circuit in the first column. That is, when the circuit in the m-th column is representatively described, the fifth transistor T5-m and the sixth transistor T6-m in the m-th column are turned off, and the common gate line Gm in the m-th column is the gate force line GF. Although not connected to the gate sense line GS, the seventh transistor T7-m is turned on, so that the common gate line Gm is connected to the gate bias line GB. Here, by supplying a gate bias voltage of −0.2 V to the gate bias line GB, a gate bias voltage of −0.2 V is applied to the gate terminals of the transistors DUT12 to DUTnm in the non-selected state, The unselected transistors under measurement DUT12 to DUTnm are completely turned off, and no off-leakage current flows from the unselected transistors under measurement DUT12 to DUTnm.

  By such an operation, only the transistor under test DUT11 is selected, the drain voltage (for example, 1.0V) is supplied to the drain force line DF, the source voltage (for example, 0V) is supplied to the source force line SF, and the gate force line The gate voltage is supplied to GF to drive the transistor DUT 11 to be measured, the drain voltage generated in the drain sense line DS (drain sense pad DSP) is detected, and the source voltage generated in the source sense line SS (source sense pad SSP), By detecting the gate voltage generated in the gate sense line GS (gate sense pad GSP), the characteristics of the measured transistor DUT11 are evaluated.

  Here, as can be seen from FIG. 3, the drain terminals and source terminals of the transistors DUT12 to DUTnm in the non-selected state have the same potential as the voltage (VPW = 0V) applied to the PW32. On the other hand, the low-level X selection signal output from the X address main decoders XD2 to XDn in the non-selected row has the same potential as the VSS level, that is, −0.5V. That is, the first transistors T1-2 to T1-n, the second transistors T2-2 to T2-n, the third transistors T3-2 to T3-n, and the fourth transistors T4-2 to T4-n in the unselected rows. Since −0.5 V, which is sufficiently lower than the voltage (0 V) of the source terminal, is applied to each gate terminal, these transistors are sufficiently turned off, and off-leakage current can be greatly reduced. As a result, it is possible to improve the characteristic evaluation accuracy and shorten the characteristic evaluation time of the measured transistor DUT 11 being selected.

  In the above description, the case where the transistor under test DUT11 is selected has been described. However, since the other transistors under test DUT12 to DUTnm are sequentially selected and evaluated for characteristics, the second embodiment relates to the second embodiment. According to the semiconductor evaluation circuit, the total characteristic evaluation time can be shortened and the characteristic evaluation accuracy can be improved as compared with the conventional circuit.

[Third Embodiment]
Next, a third embodiment of the present invention will be described.
First, as a premise of the third embodiment, a fully-separated Kelvin sense type semiconductor evaluation circuit configured so that Kelvin sense evaluation can be performed for each measured transistor will be described.

  FIG. 10 is a circuit configuration diagram of an improved fully-separated Kelvin sense semiconductor evaluation circuit. As shown in FIG. 10, the improved fully-separated Kelvin sense semiconductor evaluation circuit includes a first transistor (drain power source switching element, drain power source transistor) T10, a second transistor (drain voltage detection switching element). , Drain voltage detection transistor) T20, third transistor (source power source switching element, source power source transistor) T30, fourth transistor (source voltage detection switching element, source voltage detection transistor) T40, fifth transistor (gate) Power switching element, gate power transistor T50, sixth transistor (gate voltage detection switching element, gate voltage detection transistor) T60, NAND circuit 100, inverter 110, X address line (first address) Les line) XAd, Y address line (second address line) YAd, drain force line DF, drain sense line DS, source force line SF, source sense line SS, gate force line GF, and gate sense line GS Yes. The NAND circuit 100 and the inverter 110 constitute a selection circuit in the present invention.

  The first transistor T10, the second transistor T20, the third transistor T30, the fourth transistor T40, the fifth transistor T50, and the sixth transistor T60 are 3V type n-channel MOS transistors with stable characteristics. The inverter 110 is also composed of a 3V MOS transistor manufactured by the same process.

The drain terminal of the first transistor T10 is connected to the drain force line DF, the source terminal is connected to the drain terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the inverter 110. The drain terminal of the second transistor T20 is connected to the drain sense line DS, the source terminal is connected to the drain terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the inverter 110. The drain terminal of the third transistor T30 is connected to the source force line SF, the source terminal is connected to the source terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the inverter 110.
The drain terminal of the fourth transistor T40 is connected to the source sense line SS, the source terminal is connected to the source terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the inverter 110.

  The drain terminal of the fifth transistor T50 is connected to the gate force line GF, the source terminal is connected to the gate terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the inverter 110. The drain terminal of the sixth transistor T60 is connected to the gate sense line GS, the source terminal is connected to the gate terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the inverter 110.

  One input terminal of the NAND circuit 100 is connected to the X address line XAd, and the other input terminal is connected to the Y address line YAd. The X selection signal and the Y address line YAd input via the X address line XAd are connected. Is output to the inverter 110 as a negative logical product signal with the Y selection signal input via. The inverter 110 outputs a logical inversion signal of the negative logical product signal as a selection signal.

As described above, the first transistor T10, the second transistor T20, the third transistor T30, the fourth transistor T40, the fifth transistor T50, the sixth transistor T60, the NAND circuit 100, and the inverter provided for one measured transistor DUT. The DMA can be easily configured by arranging 110 as one evaluation unit 200 and arranging the evaluation units 200 in a matrix of a plurality of n rows and m columns in the row direction and the column direction.
In short, by including an address selection circuit in the evaluation unit 200, the selection of the evaluation unit 200 is facilitated.

Next, the operation of the evaluation unit 200 configured as described above will be described.
When an X selection signal indicating “1” and a Y selection signal are output to the X address line XAd and the Y address line YAd by a decoder (not shown) and the evaluation unit 200 is selected, the output of the NAND circuit 100 is “0” low level. Thus, the output of the inverter 110, that is, the selection signal becomes “1” high level.

  As a result, all of the first transistor T10, the second transistor T20, the third transistor T30, the fourth transistor T40, the fifth transistor T50, and the sixth transistor T60 are turned on, and the drain terminal of the transistor DUT to be measured is the drain force line. The DF and the drain sense line DS are connected, the source terminal is connected to the source force line SF and the source sense line SS, and the gate terminal is connected to the gate force line GF and the gate sense line GS. Then, the drain voltage is supplied to the drain force line DF, the source voltage is supplied to the source force line SF, and the gate voltage is supplied to the gate force line GF, thereby driving the transistor DUT to be measured, which is generated in the drain sense line DS. The characteristics of the transistor DUT to be measured are evaluated by detecting the drain voltage and the source voltage generated on the source sense line SS and the gate voltage generated on the gate sense line GS.

  On the other hand, when the X selection signal or Y selection signal indicating “0” is output to at least one of the X address line XAd and the Y address line YAd by the decoder and the evaluation unit 200 is not selected, the output of the NAND circuit 100 Becomes “1” high level, and the output of the inverter 110, that is, the selection signal becomes “0” low level. In this case, all of the first transistor T10, the second transistor T20, the third transistor T30, the fourth transistor T40, the fifth transistor T50, and the sixth transistor T60 are in the OFF state, and the measured transistor DUT is in the non-selected state.

  In the semiconductor evaluation circuit having such an evaluation unit 200, a switch (transistor) is provided for each transistor to be measured, and a completely separated Kelvin sense evaluation is possible, so that highly accurate evaluation is possible. However, since one evaluation unit 200 has a relatively large area, it is not suitable for a large capacity DMA. However, for example, in the case of configuring a medium-scale DMA capable of evaluating 256K transistors to be measured with the configuration of n = m = 512, the first transistor T10 on the drain force line DF side or the source force line SF side If the third transistor T30 has a drain current of 1 mA, for example, W = 20 μm, and the total size for 256K is 512 × 512 × 20 μm = 5242880 μm, and the off-leakage current when not selected is 0.1 pA / μm. As a result, the total leakage current becomes 500 nA and cannot be used as a DMA.

  In order to solve such a problem, a semiconductor evaluation circuit according to a third embodiment and a semiconductor evaluation circuit according to a fourth embodiment which will be described later are devised. FIG. 4 is a circuit configuration diagram of a semiconductor evaluation circuit according to the third embodiment. 4, the same components as those in FIG. 10 are denoted by the same reference numerals, and the description thereof is omitted. As shown in FIG. 4, the difference between the semiconductor evaluation circuit according to the third embodiment and the fully-separated Kelvin sense semiconductor evaluation circuit of FIG. 10 is that a drain-source bias line (reference voltage supply line) DSB and The seventh transistor (drain reference voltage application switching element) T70 and the eighth transistor (source reference voltage application switching element) T80 are newly provided. The reference symbol of the evaluation unit in the third embodiment is 200 '.

  The seventh transistor T70 and the eighth transistor T80 are 3V type n-channel MOS transistors having stable characteristics. The drain terminal of the seventh transistor T70 is connected to the drain-source bias line DSB, the source terminal is connected to the drain terminal of the transistor under test DUT, and the gate terminal is connected to the input terminal of the inverter 110. The drain terminal of the eighth transistor T80 is connected to the drain-source bias line DSB, the source terminal is connected to the source terminal of the transistor under test DUT, and the gate terminal is connected to the input terminal of the inverter 110. The drain source bias line DSB is a wiring for supplying a bias voltage, as in the first embodiment.

  Next, the operation of the semiconductor evaluation circuit according to the second embodiment configured as described above will be described. First, when the evaluation unit 200 ′ is selected, the output of the NAND circuit 100 is “0”, so that the seventh transistor T70 and the eighth transistor T80 are in the OFF state, and the characteristic evaluation of the measured transistor DUT is performed as in the conventional case. It can be performed.

  On the other hand, when the evaluation unit 200 ′ is not selected, the output of the NAND circuit 100 is “1”, so that the seventh transistor T70 and the eighth transistor T80 are in the ON state, and the drain terminal of the transistor DUT to be measured and A bias voltage is applied to the source terminal. Here, for example, if the bias voltage is set to + 0.2V, the drain voltage of the first transistor T10 is 1.0V, the source voltage is 0.2V, and the gate voltage is 0V, which is lower than the source voltage. The off-leakage current of the first transistor T10 can be reduced by about two digits. Further, the off-leakage current of the third transistor T30 can be similarly reduced.

  As described above, according to the semiconductor evaluation circuit according to the third embodiment, it is possible to reduce the off-leak current generated in the evaluation unit 200 ′ in the non-selected state even in the configuration of the completely separated Kelvin sense method. As a result, the characteristics of the transistor under measurement can be evaluated with high accuracy.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. In the following, differences from the semiconductor evaluation circuit according to the third embodiment will be described.

  FIG. 5 is a circuit configuration diagram of the semiconductor evaluation circuit according to the second embodiment. As shown in FIG. 5, the difference between the semiconductor evaluation circuit according to the second embodiment and FIG. 10 is that the well of the 1V system transistor DUT and the 3V system selection circuit are the same as in the second embodiment. A structure that electrically isolates the well of the system (first transistor T10, second transistor T20, third transistor T30, fourth transistor T40, fifth transistor T50, sixth transistor T60, NAND circuit 100, inverter 110). Adopted and applied different voltages to each well. That is, as shown in FIG. 5, the VDD of the NAND circuit 100 and the inverter 110 that are the selection circuit system is 3.3V, and VSS is −0.5V. In FIG. 5, in order to distinguish from FIG. 10, the evaluation circuit 200 ′, the first transistor T10 ′, the second transistor T20 ′, the third transistor T30 ′, the fourth transistor T40 ′, the fifth transistor T50 ′, and the sixth transistor The signs of T60 ′, NAND circuit 100 ′, and inverter 110 ′ are changed.

  Next, the operation of the semiconductor evaluation circuit according to the fourth embodiment configured as described above will be described. First, when the evaluation unit 200 ′ is selected, the output of the inverter 110 ′ becomes a high level (3.3 V), and the first transistor T10 ′, the second transistor T20 ′, the third transistor T30 ′, and the fourth transistor T40 ′. Since 3.3 V is applied to the gate terminals of the fifth transistor T50 ′ and the sixth transistor T60 ′, all of these transistors are in the ON state, and the characteristics of the measured transistor DUT can be evaluated in the same manner as in FIG. it can. Here, by setting the voltage of the drain force line DF to 1.2 V, the first transistor T10 ′, the second transistor T20 ′, the third transistor T30 ′, the fourth transistor T40 ′, the fifth transistor T50 ′, and the The 6-transistor T60 ′ operates sufficiently in the region between the three electrodes, and the resistance can be set sufficiently small.

  On the other hand, when the evaluation unit 200 ′ is not selected, the output of the inverter 110 ′ is at a low level (−0.5 V), and thus the first transistor T10 ′, the second transistor T20 ′, and the third transistor T30 ′. The fourth transistor T40 ′, the fifth transistor T50 ′, and the sixth transistor T60 ′ are all turned off, and the measured transistor DUT is not selected. Here, −0.5V is applied to the gate terminals of the first transistor T10 ′, the second transistor T20 ′, the third transistor T30 ′, the fourth transistor T40 ′, the fifth transistor T50 ′, and the sixth transistor T60 ′. Therefore, the off-leakage current generated in these transistors can be significantly reduced (about 3 digits).

  As described above, according to the semiconductor evaluation circuit according to the fourth embodiment, it is possible to reduce the off-leak current generated in the evaluation unit 200 ′ in the non-selected state even in the configuration of the completely separated Kelvin sense method. As a result, when the DMA is configured, the characteristics of the transistor under measurement can be evaluated with high accuracy.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. The semiconductor evaluation circuit according to the fifth embodiment makes it possible to further reduce the off-leakage current when the DMA is configured by using a plurality of fully-separated Kelvin sense type semiconductor evaluation circuits of the fourth embodiment.

  FIG. 6 is a circuit configuration diagram of a semiconductor evaluation circuit according to the fifth embodiment. As shown in FIG. 6, in the semiconductor evaluation circuit according to the fifth embodiment, in addition to the components of the fourth embodiment, a drain switch transistor 120 and a source switch transistor 130 are newly provided. The drain switch transistor 120 is an N-type MOS transistor, and has a gate terminal connected to the Y address line YAd, a drain terminal connected to the drain force pad DFP, and a source terminal connected to the drain force line DF. The source switch transistor 130 is an N-type MOS transistor, and has a gate terminal connected to the Y address line YAd, a drain terminal connected to the source force pad SFP, and a source terminal connected to the source force line SF.

  As a result, when the evaluation unit 200 ′, that is, the transistor under test DUT is not selected, the drain switch transistor 120 and the source switch transistor 130 are turned off, so that the unselected evaluation unit 200 ′ is connected to the drain force line DF and The source force line SF can be separated, and the off-leak current for one evaluation unit can be reduced.

  For example, as shown in FIG. 7, a specific description will be given on the assumption that a DMA is configured by arranging two columns of semiconductor evaluation circuits of the fifth embodiment. In FIG. 7, the evaluation unit in the first column, the drain switch transistor, the source switch transistor, and the Y address line are denoted by 200′-1, 120-1, 130-1, and YAd1, respectively. The symbols of the unit, the drain switch transistor, the source switch transistor, and the Y address line are 200′-2, 120-2, 130-2, and YAd2, respectively.

  Here, the evaluation unit 200′-1 in the first column is selected (Y address line YAd1 is high level), and the evaluation unit 200′-2 in the second column is not selected (Y address line YAd2 is low level). In this case, the drain switch transistor 120-1 and the source switch transistor 130-1 are turned on, and the drain switch transistor 120-2 and the source switch transistor 130-2 are turned off. That is, the total off-leakage current flowing through the drain force line DF and the source force line SF includes only that generated by the selected evaluation unit 200′-1, and the off-leakage generated by the evaluation unit 200′-2. Current is not included. Therefore, the off-leakage current flowing in the drain force line DF and the source force line SF is reduced by one evaluation unit (one column) and becomes ½.

  Similarly, for example, when the DMA is configured by arranging the semiconductor evaluation circuits of the fifth embodiment for eight columns, the off-leakage current flowing in the drain force line DF and the source force line SF can be reduced to 1/8, and further, 512 columns. When the DMA is configured by arranging the parts separately, the off-leakage current can be reduced to 1/512, so that the off-leakage current flowing through the drain force line DF and the source force line SF hardly becomes a problem.

  As described above, by using the semiconductor evaluation circuit according to the fifth embodiment, the influence of the off-leakage current can be made extremely small even when a large-scale DMA of the completely separated Kelvin sense method is configured. It is possible to evaluate the characteristics of the transistor under measurement with high accuracy.

  Hereinafter, in the fully-separated Kelvin sense semiconductor evaluation circuit shown in the fifth embodiment, the drain force line DF, the source force line SF, the voltage setting example of VDD and VSS of the selection circuit system will be described with reference to FIG. To do. In FIG. 8, only the force-side transistors (first transistor T10 ', third transistor T30', and fifth transistor T50 ') necessary for operation in FIG.

  As shown in FIG. 8, it is assumed that the drain voltage (the voltage at the point b) is 1.2V and the source voltage (the voltage at the point c) is 0V as the measurement voltage of the transistor under test DUT. In order to apply such a voltage to the drain terminal and the source terminal of the transistor under test DUT, the resistance components of the first transistor T10 ′, the third transistor T30 ′, the drain switch transistor 120, and the source switch transistor 130 are considered. Then, a voltage of 1.5 V is set for the drain force line DF, 1.4 V for the point a, -0.2 V for the point d, and -0.3 V for the source force line SF. Here, it is assumed that the drain switch transistor 120 and the source switch transistor 130 are twice as large as the first transistor T10 '.

When the evaluation unit 200 ′ is not selected, the output of the Y decoder composed of the NAND circuit 140 and the inverter 150 and the output of the decoder in the evaluation unit 200 ′ composed of the NAND circuit 100 ′ and the inverter 110 ′ are both. The first transistor T10 ′, the third transistor T30 ′, the drain switch transistor 120, and the source switch transistor 130 are completely turned off, and the off-leakage current is reduced. Here, as a matter to be particularly noted in the Kelvin sense method, the resistance component of the switches (first transistor T10 ′, third transistor T30 ′, drain switch transistor 120 and source switch transistor 130), the parasitic resistance of the wiring, etc. For example, in order to set the voltage at the point c to 0V, the source force line SF needs to be set to -0.3V. In order to completely turn off the third transistor T30 ′ and the source switch transistor 130, it is necessary to set the voltage VSF> VSS of the source force line SF.
Therefore, as described above, in this example, VSF = −0.3V and VSS = −0.5V were set.

As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.
For example, the transistor under measurement and other transistors may be p-channel MOS transistors, or the relationship between the rows and columns may be switched (a common gate line is provided in the row direction, a common drain line and a common source are provided in the column direction). Provide a line).
In the present invention, since a fine transistor is assumed for the DUT, a stable 3V process is used for the evaluation control circuit (decoder, etc.) separately from the fine process DUT transistor. As long as the process is relatively stable, the evaluation control circuit may use a transistor made in the same process as the DUT without departing from the gist of the present invention.

Here, a voltage detection terminal (sense line) in the Kelvin sense method will be described.
The purpose of the voltage detection terminal is that a parasitic resistance enters the measurement system due to the configuration of the DMA, and a voltage drop occurs in the drain-source path through which current flows due to the parasitic resistance, and accurate measurement cannot be performed. Therefore, it is a terminal for detecting the drain voltage or source voltage at the base of the transistor under measurement. Therefore, normally, detection terminals are provided in the drain, source and gate, but the most important is the drain-source current path, and since there is no current flow path in the gate, some measurement is performed with emphasis on the area of the DUT. If the accuracy can be lowered, the detection terminal of the gate can be omitted.

  According to the semiconductor evaluation circuit of the present invention, it is possible to reduce both the characteristic evaluation time of the transistor under measurement and improve the characteristic evaluation accuracy.

Claims (19)

A drain power supply line for supplying drain power to the drain terminal of one or a plurality of transistors to be measured; and a source power supply line for supplying source power to the source terminal, wherein the drain terminal, the source terminal, At least one of them is a semiconductor evaluation circuit connected to the drain power supply line or the source power supply line corresponding to each via a switching element that is turned on when the transistor under measurement is selected,
A reference voltage application circuit for applying a predetermined reference voltage to at least one of the drain terminal and the source terminal in the non-selected transistor under measurement ;
The reference voltage application circuit includes:
A reference voltage supply line for supplying a predetermined reference voltage;
N drain reference voltage application switching elements that are provided for each row and switch connection / disconnection between the common drain line of each row and the reference voltage supply line; and the common source line of each row N source reference voltage application switching elements for switching connection / disconnection to / from a reference voltage supply line, and a logical inversion signal of a row selection signal output from the row selection control circuit, provided for each row, for each row. A drain reference voltage application switching element and a logic inversion circuit for outputting to the source reference voltage application switching element;
Semiconductor circuit for evaluating Ru equipped with. The transistors to be measured are arranged in a matrix of n rows and m columns,
N common drain lines provided for each row and connected to the drain terminals of the transistors under measurement in each row;
N common source lines provided for each row and connected to the source terminals of the transistors under measurement in each row;
M common gate lines provided for each column and connected to the gate terminals of the transistors under measurement in each column;
A drain voltage detection line;
A source voltage detection line;
A gate power line,
A gate voltage detection line;
N drain power switching elements that are provided for each row and switch connection / disconnection between the common drain line of each row and the drain power supply line;
N drain voltage detection switching elements that are provided for each row and switch connection / disconnection between the common drain line of each row and the drain voltage detection line;
N source power switching elements that are provided for each row and switch connection / disconnection between the common source line of each row and the source power supply line;
N source voltage detection switching elements that are provided for each row and switch connection / disconnection between the common source line of each row and the source voltage detection line;
M number of gate power switching elements provided for each column, for switching connection / non-connection between the common gate line of each column and the gate power supply line, and a common gate line for each column provided for each column; M gate voltage detection switching elements for switching connection / disconnection with the gate voltage detection line;
Based on an address signal input from a host controller to select a transistor to be measured for characteristic evaluation, the drain power source switching element, the drain voltage detection switching element, and the source power source switching in a row to be selected A row selection control circuit for outputting a row selection signal for turning on the element and the source voltage detection switching element;
A column selection control circuit that outputs a column selection signal for turning on the gate power supply switching element and the gate voltage detection switching element in a column to be selected based on the address signal;
With
The semiconductor evaluation circuit according to claim 1, wherein the reference voltage application circuit applies a predetermined reference voltage to the common drain line and the common source line in a non-selected row based on a logical inversion signal of the row selection signal. The drain power switching element is disposed at one end of the common drain line, the drain voltage detecting switching element is disposed at the other end of the common drain line, and the source power switching element is disposed on the common source line. The semiconductor evaluation circuit according to claim 1 , wherein the semiconductor evaluation circuit is disposed at one end and the switching element for detecting the source voltage is disposed at the other end of the common source line. A gate reference voltage supply line for supplying a predetermined gate reference voltage, and m gate references provided for each column, for switching connection / disconnection between the common gate line of each column and the gate reference voltage supply line A voltage applying switching element;
Further comprising, said column selection control circuit, semiconductor evaluating circuit according to claim 1 or 2 outputs a logical inversion signal of the column selection signal to the gate reference voltage applying switching element. The transistor to be measured is a 1V low voltage MOS (Metal Oxide Semiconductor) transistor element, the drain power source switching element, the drain voltage detection switching element, the source power source switching element, and the source voltage detection switching. A switching element for gate power supply, a switching element for gate voltage detection, a switching element for application of a drain reference voltage, a switching element for application of a source reference voltage, and a switching element for application of a gate reference voltage. 5. The semiconductor evaluation circuit according to claim 4 , wherein said row selection control circuit and said column selection control circuit are transistor elements, each comprising a 3V high voltage MOS transistor element. A drain voltage detection line;
A source voltage detection line;
A gate power line,
A gate voltage detection line;
A first address line;
A drain power source switching element that is provided for the second address line and one transistor under measurement, and switches connection / disconnection between the drain terminal of the transistor under measurement and the drain power source line;
A drain voltage detecting switching element that is provided for the one transistor under measurement and switches connection / disconnection between the drain terminal of the transistor under measurement and the drain voltage detection line;
A source power switching element that is provided for the one transistor under measurement and switches connection / disconnection between the source terminal of the transistor under measurement and the source power source line;
A source voltage detection switching element that is provided for the one transistor under measurement and switches connection / disconnection between the source terminal of the transistor under measurement and the source voltage detection line;
Provided for the one transistor under measurement, provided for the gate power source switching element for switching connection / disconnection between the gate terminal of the transistor under measurement and the gate power supply line, and for the one transistor under measurement. A switching element for detecting a gate voltage for switching connection / disconnection between the gate terminal of the transistor under measurement and the gate voltage detection line, and the one transistor under measurement for selecting the transistor under measurement. The drain power source switching element, the drain voltage detecting switching element, the source power source switching element, and the source voltage based on an address signal input via the first address line and the second address line Switching element for detection, switching element for gate power supply And a selection circuit that outputs a selection signal for turning on the switching element for detecting the gate voltage, and the reference voltage application circuit is based on a logical inversion signal of the selection signal, The semiconductor evaluation circuit according to claim 1, wherein a predetermined reference voltage is applied to the drain terminal and the source terminal. The reference voltage application circuit includes:
A reference voltage supply line for supplying a predetermined reference voltage;
A drain reference voltage application switching element for switching the connection / disconnection between the drain terminal of the transistor to be measured and the reference voltage supply line, and the one transistor to be measured; And a source reference voltage application switching element that switches connection / disconnection between the source terminal of the transistor under measurement and the reference voltage supply line, and the selection circuit outputs a logic inversion signal of the selection signal. The semiconductor evaluation circuit according to claim 6 , wherein the semiconductor evaluation circuit outputs the drain reference voltage application switching element and the source reference voltage application switching element. The transistor to be measured is a 1V low voltage MOS (Metal Oxide Semiconductor) transistor element, the drain power source switching element, the drain voltage detection switching element, the source power source switching element, and the source voltage detection switching. The element, the gate power supply switching element, the gate voltage detection switching element, the drain reference voltage application switching element and the source reference voltage application switching element are 3V high voltage MOS transistor elements, and the selection circuit 8. The semiconductor evaluation circuit according to claim 7 , wherein the semiconductor evaluation circuit is composed of a 3V high voltage MOS transistor element. The drain power source switching element, the drain voltage detection switching element, the source power source switching element, the source voltage detection switching element, the gate power source switching element, the gate voltage detection switching element, and the drain reference voltage application. use switching elements, and an evaluation unit corresponding to the combination of the source reference voltage application switching element and the selection circuit to a single transistor under measurement, claim 7 or configured by arranging a plurality of the evaluation unit in the form of a matrix 9. The semiconductor evaluation circuit according to 8 .   The semiconductor evaluation circuit according to claim 1, wherein the predetermined reference voltage is a ground level.   The semiconductor evaluation circuit according to claim 1, wherein the predetermined reference voltage is a positive voltage. A semiconductor evaluation circuit in which one or a plurality of transistors under measurement and a selection circuit system for selecting one of the transistors under measurement are formed on the same semiconductor substrate,
The measured transistor and the selection circuit system are formed on the semiconductor substrate by a well structure that is electrically separated,
The reference power supply voltage of the selection circuit system is set to a value lower than the well voltage applied to the well of the transistor under measurement ,
The transistors to be measured are arranged in a matrix of n rows and m columns,
N common drain lines provided for each row and connected to the drain terminals of the transistors under measurement in each row;
N common source lines provided for each row and connected to the source terminals of the transistors under measurement in each row;
M common gate lines provided for each column and connected to the gate terminals of the transistors under measurement in each column;
Drain power line,
A drain voltage detection line;
A source power line;
A source voltage detection line;
A gate power line,
A gate voltage detection line is formed on the semiconductor substrate;
The selection circuit system is:
N drain power supply transistors that are provided for each row and switch connection / disconnection between the common drain line of each row and the drain power supply line;
N drain voltage detection transistors provided for each row, for switching connection / disconnection between the common drain line of each row and the drain voltage detection line;
N source power supply transistors that are provided for each row and switch connection / disconnection between the common source line of each row and the source power supply line;
N source voltage detection transistors that are provided for each row and switch connection / disconnection between the common source line of each row and the source voltage detection line;
Provided for each column, m gate power supply transistors for switching connection / disconnection between the common gate line of each column and the gate power supply line, provided for each column, and the common gate line of each column M gate voltage detection transistors for switching connection / disconnection with the gate voltage detection line;
Based on an address signal input from a host controller to select a transistor to be measured for characteristic evaluation, the drain power supply transistor, the drain voltage detection transistor, the source power supply transistor in the row to be selected, and the source power supply transistor A row selection control circuit for outputting a row selection signal for turning on the source voltage detection transistor;
A column selection control circuit for outputting a column selection signal for turning on the gate power supply transistor and the gate voltage detection transistor in a column to be selected based on the address signal;
Consists of
A semiconductor evaluation circuit for setting a reference power supply voltage of the row selection control circuit and the column selection control circuit to a value lower than a well voltage applied to a well of the transistor under measurement . The drain power supply transistor is disposed at one end of the common drain line, the drain voltage detection transistor is disposed at the other end of the common drain line, and the source power supply transistor is disposed at one end of the common source line. The semiconductor evaluation circuit according to claim 12 , wherein the source voltage detection transistor is arranged at the other end of the common source line. A gate reference voltage supply line for supplying a predetermined gate reference voltage, and m gate references provided for each column, for switching connection / disconnection between the common gate line of each column and the gate reference voltage supply line A voltage application transistor;
14. The semiconductor evaluation circuit according to claim 12 , wherein the column selection control circuit outputs a logical inversion signal of the column selection signal to the gate reference voltage application transistor. The transistor under measurement is a 1V low voltage MOS (Metal Oxide Semiconductor) transistor, the drain power transistor, the drain voltage detection transistor, the source power detection transistor, the source voltage detection transistor, and the gate power supply. Transistor, gate voltage detection transistor and gate reference voltage application transistor are 3V high voltage MOS transistors, and the row selection control circuit and column selection control circuit are 3V high voltage MOS transistors. The semiconductor evaluation circuit according to claim 14, which is configured. Drain power line,
A drain voltage detection line;
A source power line;
A source voltage detection line;
A gate power line,
A gate voltage detection line;
A first address line;
A second address line is formed on the semiconductor substrate;
The selection circuit system is provided for one transistor to be measured, and a drain power supply transistor that switches connection / disconnection between the drain terminal of the transistor to be measured and the drain power supply line;
A drain voltage detecting transistor which is provided for the one transistor under measurement and switches connection / disconnection between the drain terminal of the transistor under measurement and the drain voltage detection line;
A source power transistor that is provided for the one transistor under measurement and that switches connection / disconnection between the source terminal of the transistor under measurement and the source power line;
A source voltage detection transistor that is provided for the one transistor under measurement and switches connection / disconnection between the source terminal of the transistor under measurement and the source voltage detection line;
Provided for the one transistor under measurement, provided for the gate power transistor for switching connection / disconnection between the gate terminal of the transistor under measurement and the gate power line, and for the one transistor under measurement, A gate voltage detection transistor for switching connection / disconnection between the gate terminal of the transistor under measurement and the gate voltage detection line, and the one transistor under measurement are provided for selecting the transistor under measurement. Based on an address signal input via the first address line and the second address line, the drain power supply transistor, the drain voltage detection transistor, the source power supply transistor, the source voltage detection transistor, Gate power supply transistor and gate voltage detection transistor And a selection control circuit for outputting a selection signal for turning on the register, and setting a reference power supply voltage of the selection control circuit to a value lower than a well voltage applied to the well of the transistor under measurement. Item 13. A semiconductor evaluation circuit according to Item 12 . One combination of the drain power supply transistor, the drain voltage detection transistor, the source power supply transistor, the source voltage detection transistor, the gate power supply transistor, the gate voltage detection transistor, and the selection control circuit. 17. The semiconductor evaluation circuit according to claim 16 , wherein the evaluation unit corresponds to a transistor, and the plurality of evaluation units are arranged in a matrix of n rows and m columns. A drain power supply pad for supplying drain power from the outside to the drain power line;
A source power supply pad for supplying source power to the source power supply line from the outside, and a drain provided for each column, for switching connection / disconnection between the drain power supply pad and the drain power supply line of each column And a source switch transistor that is provided for each column and switches connection / disconnection between the source power supply pad and the source power supply line in each column, the drain switch transistor, 18. The semiconductor evaluation circuit according to claim 17 , wherein the gate terminal of the source switch transistor is connected to one of the first address line and the second address line corresponding to each column. The transistor under measurement is a 1V low voltage MOS transistor, the drain power transistor, the drain voltage detection transistor, the source power transistor, the source voltage detection transistor, the gate power transistor, the gate 19. The semiconductor according to claim 18 , wherein the voltage detection transistor, the drain switch transistor, and the source switch transistor are 3V high voltage MOS transistors, and the selection control circuit is formed of a 3V high voltage MOS transistor. Evaluation circuit.

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