WO2009017223A1 - Semiconductor evaluation circuit - Google Patents

Semiconductor evaluation circuit Download PDF

Info

Publication number
WO2009017223A1
WO2009017223A1 PCT/JP2008/063867 JP2008063867W WO2009017223A1 WO 2009017223 A1 WO2009017223 A1 WO 2009017223A1 JP 2008063867 W JP2008063867 W JP 2008063867W WO 2009017223 A1 WO2009017223 A1 WO 2009017223A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
drain
evaluation circuit
source
terminal
Prior art date
Application number
PCT/JP2008/063867
Other languages
French (fr)
Japanese (ja)
Inventor
Masamichi Asano
Original Assignee
Toppan Printing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co., Ltd. filed Critical Toppan Printing Co., Ltd.
Priority to JP2009525460A priority Critical patent/JP5343851B2/en
Publication of WO2009017223A1 publication Critical patent/WO2009017223A1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor evaluation circuit is provided with a drain power supply line for supplying drain power supply to a drain terminal of one or a plurality of transistors to be measured, and a source power supply line for supplying source power supply to a source terminal. At least the drain terminal or the source terminal is connected to the corresponding drain power supply line or the source power supply line through a switching element which is turned on when the transistor to be measured is selected. The semiconductor evaluation circuit is provided with a reference voltage applying circuit for applying a prescribed reference voltage to at least the drain terminal or the source terminal of the unselected transistor to be measured.
PCT/JP2008/063867 2007-08-02 2008-08-01 Semiconductor evaluation circuit WO2009017223A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009525460A JP5343851B2 (en) 2007-08-02 2008-08-01 Semiconductor evaluation circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007201923 2007-08-02
JP2007201922 2007-08-02
JP2007-201922 2007-08-02
JP2007-201923 2007-08-02

Publications (1)

Publication Number Publication Date
WO2009017223A1 true WO2009017223A1 (en) 2009-02-05

Family

ID=40304452

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/063867 WO2009017223A1 (en) 2007-08-02 2008-08-01 Semiconductor evaluation circuit

Country Status (2)

Country Link
JP (1) JP5343851B2 (en)
WO (1) WO2009017223A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147224A (en) * 2008-12-18 2010-07-01 Toppan Printing Co Ltd Semiconductor evaluating circuit and semiconductor evaluating device
JP2010287769A (en) * 2009-06-12 2010-12-24 Toppan Printing Co Ltd Semiconductor device and method of evaluating semiconductor device
CN110166031A (en) * 2018-02-16 2019-08-23 富士电机株式会社 Semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102179035B1 (en) * 2014-03-07 2020-11-16 삼성전자주식회사 Semiconductor device
EP3627120B1 (en) * 2017-05-15 2021-08-18 Socionext Inc. Temperature measurement device and temperature measurement method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000090695A (en) * 1999-09-21 2000-03-31 Toshiba Corp Semiconductor storage device
JP2005521878A (en) * 2002-04-02 2005-07-21 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Testable cascode circuit and method for testing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3187019B2 (en) * 1998-12-10 2001-07-11 沖電気工業株式会社 Semiconductor integrated circuit and test method therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000090695A (en) * 1999-09-21 2000-03-31 Toshiba Corp Semiconductor storage device
JP2005521878A (en) * 2002-04-02 2005-07-21 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Testable cascode circuit and method for testing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147224A (en) * 2008-12-18 2010-07-01 Toppan Printing Co Ltd Semiconductor evaluating circuit and semiconductor evaluating device
JP2010287769A (en) * 2009-06-12 2010-12-24 Toppan Printing Co Ltd Semiconductor device and method of evaluating semiconductor device
CN110166031A (en) * 2018-02-16 2019-08-23 富士电机株式会社 Semiconductor device
CN110166031B (en) * 2018-02-16 2023-09-26 富士电机株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Also Published As

Publication number Publication date
JPWO2009017223A1 (en) 2010-10-28
JP5343851B2 (en) 2013-11-13

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