JP2010287769A - Semiconductor device and method of evaluating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of evaluating characteristics of large-scale transistors to be measured highly precisely and a method of evaluation with the use of the same. <P>SOLUTION: The semiconductor device includes evaluation cells C11 to Cnm having transistors DUT to be measured which are arrayed in a matrix of (n) rows by (m) columns, a drain stress line DVS etc., for applying a stress voltage to the transistors to be measured, row selection lines X1 to Xn for row selection signal supply and column selection lines Y1 to Ym for column selection signal supply for selecting the evaluation cells, and a selection circuit 10 which outputs a selection signal representing whether or not a transistor to be measured is selected in accordance with an input row selection signal and column selection signal. The row selection signal and the column selection signal are generated with a selection control signal etc., input to a selection signal supply circuit to switch a first transistor T1 to a ninth transistor T9 provided to each evaluation cell, and measurement evaluation of the transistors DUT to be measured or stress voltage applied to the transistors DUT to be measured is carried out. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a semiconductor device evaluation method, and more particularly to a semiconductor device and a semiconductor device evaluation method for evaluating the characteristics of a transistor under measurement which is a DUT (Device Under Test).

  When developing micro processes for semiconductors, TEG (Test Element Group) consisting of elements of various dimensions is fabricated on a semiconductor wafer to evaluate and analyze the characteristics of micro elements (transistors, resistor elements, etc.) We are developing devices that can withstand mass production by setting process conditions based on the results. In the process development so far, the optimum process conditions and transistor structure could be set by evaluating and analyzing the characteristics of individual transistors fabricated in the TEG. However, as miniaturization progresses, for example, characteristic variations caused by differences in the channel length (L) and channel width (W) of the transistors between the plurality of transistors, or channel injection that determines the threshold voltage of the transistors. Variations in characteristics due to variations (impurity variations) can no longer be ignored.

  Further, the phenomenon that the stress applied to the transistor changes depending on the state of the transistor and the characteristics of the transistor change cannot be ignored. From such a situation, for example, in a fine process with a processing level of 45 nm, the characteristics of both transistors vary even if they are adjacent transistors. Therefore, a minute signal such as SRAM (Static Random Access Memory) is transferred to a pair transistor (adjacent 2 It is predicted that the detection circuit and the amplification circuit that detect with two transistors) have a reduced operating margin or become inoperable. In this case, sufficient data cannot be obtained only by evaluating individual transistors. Therefore, the characteristics of a large number of transistors are evaluated, analyzed by statistical processing, and systematic characteristic differences and characteristic differences due to variations are separated. A large-scale TEG that can be analyzed is required.

Conventionally, as a TEG for performing large-scale element evaluation, for example, a DMA (Device Matrix Array) -TEG in which a plurality of transistors to be measured are arranged in a matrix of n rows and m columns as shown in FIG. (See Non-Patent Document 1).
The configuration of the DMA-TEG in the prior art will be described below with reference to FIG. DUT11 to DUTnm are transistors to be measured. The drains of the transistors under measurement DUT11 to DUT1m belonging to the first row are connected to the common drain line D1, and the sources are connected to the common source line S1. The common drain line D1 is connected via a switch SW2 to a common drain force line (Drain Force) to which a drain voltage is supplied. Further, in order to monitor the voltage of the common drain line D1, the sub-drain sense line DS1 is connected to the drain sense line (Drain Sense) via the switch SW1. The common source line S1 is connected to a common source power source (Source Force). Further, in order to monitor the voltage of the common source line S1, the common source line S1 is connected to a source sense line (Source Sense) via a switch SW3. The switches SW1 to SW3 have the circuit configuration shown in FIG. 21B, and are controlled by an output signal of a decoder (not shown) here.

The same connection as described above is repeated up to n rows, and the transistors under measurement DUTn1 to DUTnm are provided in the nth row. The gates of the transistors under measurement DUT11 to DUTn1 belonging to the first column are connected to the common gate line G1, and the gates of the transistors under test DUT1m to DUTnm belonging to the mth column are connected to the common gate line Gm. .
Further, either the gate voltage VG1 or the gate non-selection voltage VGX is supplied to the common gate line G1 through the gate selection circuit 500. When the selection signal EN1 becomes high level (selected), the gate voltage VG1 is supplied to the gate line G1, and when the selection signal EN1 becomes low level (unselected), the gate non-selection voltage VGX is supplied to the gate line G1. The gate non-selection voltage VGX is normally zero volts, but a negative voltage can be supplied as necessary.
With the DMA-TEG having such a configuration, the characteristics of n × m transistors DUT11 to DUTnm can be measured and evaluated.

On the other hand, in particular, in the P-channel MOS transistor, the problem of so-called NBTI (Negative Bias Temperature Instability), in which the characteristic deterioration due to stress fluctuation and the recovery change momentarily, has become remarkable. Has become popular.
However, this characteristic depends on the stress time and the recovery time. Conventionally, this characteristic was evaluated only with a single transistor, and there was no large-scale evaluation method.

Yoshiyuki Shimizu, Mitsuo Nakamura, Toshimasa Matsuoka, and Kenji Taniguchi, “Test structure for precise statistical characteristics measurement of MOSFETs”, IEEE 2002 Int. Conference on Microelectronic Test Structure (ICMTS 2002), pp. 49-54, April 2002 Sanjay Rangan, Neal Mielke, and Everett C.C.Yeh, “Universal Recovery Behavior of Negative Bias Temperature Instability”, IEEE 2003 M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribed, F. Perrier, Y. Rey-Tauriac, and N. Revil, “On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's ”, IEDM 2004

However, when the NBTI test is performed by the DMA-TEG according to the above-described prior art, the characteristics of the individual transistors to be measured are sequentially measured after applying the stress voltage to all the transistors to be measured DUT11 to DUTnm. As a result, the characteristics of the transistor under measurement to be measured later recover, and there is a problem that the characteristic change amount corresponding to the stress time cannot be obtained accurately.
In addition, in order to avoid degradation of measurement accuracy due to characteristic recovery, it is possible to measure characteristics immediately after applying a stress voltage for each measured transistor, but the stress application time is proportional to the number of measured transistors. Therefore, there is a problem that enormous evaluation time is required. Further, each signal line used for selecting a transistor to be measured also requires charging / discharging every time it is evaluated, which causes a problem of increasing current consumption. Furthermore, since the time required for stabilizing the internal potential of the measurement system is required due to the increase in current consumption, there is a problem that the evaluation time is further increased.
The present invention has been made in view of the above-described circumstances, and provides a semiconductor device and a semiconductor device evaluation method capable of measuring characteristics of a large-scale transistor under measurement with high accuracy and in a short time. Objective.

In order to solve the above problem, the present invention provides a semiconductor device for evaluating characteristics of a transistor under measurement as a first solving means relating to a semiconductor device,
n × m evaluation cells arranged in a matrix of n rows and m columns (n and m are positive integers) and having a transistor to be measured;
A row selection line provided for each row and for supplying a row selection signal for selecting the evaluation cell belonging to each row;
A column selection line provided for each column, for supplying a column selection signal for selecting the evaluation cell belonging to each column;
A drain power supply line for applying a stress voltage to the drain terminal for the transistor under measurement;
A source power line for applying a stress voltage to the source terminal for the transistor under measurement;
A gate power supply line for applying a stress voltage to the gate terminal for the transistor under measurement;
A main drain power supply line for supplying a drain voltage for the transistor under measurement;
A main source power line for supplying a source voltage for the transistor under measurement;
A main gate power supply line for supplying a gate voltage for the transistor under measurement;
A sub-drain power supply line that is provided for each row or column and supplies a drain voltage to the transistor under measurement belonging to each row or column;
A sub-source power supply line provided for each row or each column and for supplying a source voltage to the transistor under measurement belonging to each row or each column;
A sub-gate power supply line provided for each row or each column, for supplying a gate voltage to the transistor under measurement belonging to each row or each column;
Corresponding to the row selection signal belonging to the same row as the sub-drain power supply line or the column selection signal belonging to the column provided corresponding to the sub-drain power supply line, the sub-drain power supply line and the main drain power supply line are connected Or a drain power line switching circuit to be disconnected,
The sub-source power line is connected to the main source power line in response to a row selection signal belonging to the same row as the sub-source power line or a column selection signal belonging to the column. Or a source power line switching circuit to be disconnected,
Corresponding to the row selection signal belonging to the same row as the sub-gate power supply line or the column selection signal belonging to the column provided corresponding to the sub-gate power supply line, the sub-gate power supply line and the main gate power supply line are connected Or a gate power line switching circuit to be disconnected,
A main drain voltage detection line for detecting a drain voltage of the transistor under measurement;
A main source voltage detection line for detecting a source voltage of the transistor under measurement;
A main gate voltage detection line for detecting the gate voltage of the transistor under measurement;
A sub-drain voltage detection line provided for each row or each column and for detecting a drain voltage of the transistor under measurement belonging to each row or each column;
A sub-source voltage detection line provided for each row or each column, for detecting a source voltage of the transistor under measurement belonging to each row or each column;
A sub-gate voltage detection line provided for each row or each column, for detecting a gate voltage of the transistor under measurement belonging to each row or each column;
In response to a row selection signal belonging to the same row as the sub-drain voltage detection line or a column selection signal belonging to a column provided corresponding to the sub-drain voltage detection line, the sub-drain voltage detection line and the main drain voltage A drain detection line switching circuit for connecting or disconnecting the detection lines; and
The sub-source voltage detection line and the main source voltage are provided corresponding to the sub-source voltage detection line and according to a row selection signal belonging to the same row as the sub-source voltage detection line or a column selection signal belonging to the column. A source detection line switching circuit for connecting or disconnecting the detection line; and
The sub-gate voltage detection line and the main gate voltage are provided corresponding to the sub-gate voltage detection line and according to a row selection signal belonging to the same row as the sub-gate voltage detection line or a column selection signal belonging to a column. A gate detection line switching circuit for connecting or disconnecting the detection lines; and
A selection signal supply circuit for supplying a column selection signal to each column selection line and supplying a row selection signal to each row selection line;
Each of the evaluation cells is
One input terminal is connected to the row selection line belonging to its own row, and the other input terminal is connected to the column selection line belonging to its own column and supplied to the connected row selection line. A selection circuit for outputting a selection signal indicating selection / non-selection of its own transistor under measurement in accordance with a row selection signal and a column selection signal supplied to a column selection line;
A first switch for connecting or disconnecting the drain terminal and the drain power supply line according to the selection signal;
A second switch for connecting or disconnecting the source terminal and the source power line in accordance with the selection signal;
A third switch for connecting or disconnecting the gate terminal and the gate power supply line according to the selection signal;
A fourth switch for connecting or disconnecting the sub-drain power supply line belonging to the same row or column as the self and the drain terminal of the transistor under test according to the selection signal;
A fifth switch for connecting or disconnecting the sub-source power line belonging to the same row or column as the self and the source terminal of the transistor under test according to the selection signal;
A sixth switch for connecting or disconnecting the sub-gate power supply line belonging to the same row or column as itself and the gate terminal of the transistor under measurement according to the selection signal;
According to the selection signal, a seventh switch for connecting or disconnecting the sub-drain voltage detection line belonging to the same row or column as the self and the drain terminal of the transistor under measurement;
An eighth switch for connecting or disconnecting the sub-source voltage detection line belonging to the same row or column as itself and the source terminal of the transistor under measurement according to the selection signal;
A ninth switch for connecting or disconnecting the sub-gate voltage detection line belonging to the same row or column as itself and the gate terminal of the transistor under measurement according to the selection signal;
With
The selection signal supply circuit has a selection control signal, a clock signal, a column address signal, a row address signal, and a test signal as inputs,
Depending on the state of the test signal, the mode shifts to either the normal evaluation mode or the first test mode,
In the normal evaluation mode, a first address mode that generates the column selection signal and the row selection signal based on the column address signal and the row address signal according to the state of the selection control signal, and the clock signal Performing a count operation in synchronization, and switching between the second address mode for generating the column selection signal and the row selection signal based on the count result;
In the first test mode, the column selection signal and the row selection signal for deselecting all evaluation cells are generated.

Further, as a second solving means relating to the semiconductor device, in the first solving means, a transition is made to a second test mode according to the state of the test signal,
In the second test mode, the column selection signal and the row selection signal for selecting all evaluation cells are generated.

Further, as a third solution means for the semiconductor device, in the first or second solution means, in the second address mode,
In synchronization with the first clock signal, the column selection signal and the row selection signal are generated based on the column address signal and the row address signal,
A counting operation is performed in synchronization with the second and subsequent clock signals.

  Further, as a fourth solving means relating to the semiconductor device, in the first to third solving means, the evaluation cells arranged in a matrix of n rows and m columns may include the column address signal and the row address signal. Are divided into 2 to the power of j by the address of j (j is a positive integer) bit, and the channel width and the channel length of the transistor under measurement are the same in each of the divided arrays And

  Further, as a fifth solving means according to the semiconductor device, in the fourth solving means, the channel width or the channel length of the transistor under measurement or the channel width and the channel length are different between the arrays. .

  Further, as a sixth solving means relating to the semiconductor device, in any one of the first to fifth solving means, the drain power source line, the source power source line, the gate power source line, the main drain power source line, the main main power source line. Source power line, main gate power line, main drain voltage detection line, main source voltage detection line, main gate voltage detection line, power line, ground line, and well voltage line for applying a back bias voltage to the transistor under measurement And pad electrodes to which the selection control signal, the test signal, the clock signal, the column address signal, and the row address signal are respectively input, and the pad electrode is provided on one side of the chip. It is characterized by being arranged along.

On the other hand, the present invention is a semiconductor device evaluation method for evaluating the characteristics of a transistor under measurement as a first solving means related to a semiconductor evaluation method, and includes any one of the first to sixth solving means. When performing the characteristic evaluation using the first address mode of the normal evaluation mode using the described semiconductor device,
The state of the test signal input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit is set to a state corresponding to the first address mode. A first step of inputting a column address signal and a row address signal representing the position of the evaluation cell to be evaluated to the selection signal supply circuit;
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
And a third step of evaluating the characteristics of the transistor under measurement of the evaluation cell selected in the first step by measuring a current flowing through the main drain power source line or the main source power source line. Features.

Further, the present invention provides a semiconductor device evaluation method for evaluating characteristics of a transistor under measurement as a second solving means relating to the semiconductor evaluation method, wherein any one of the first to sixth solving means is provided. When performing the characteristic evaluation using the second address mode of the normal evaluation mode using the described semiconductor device,
The state of the test signal input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit is set to a state corresponding to the second address mode. A first step of:
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
And a third step of evaluating the characteristics of the transistor under measurement of the evaluation cell selected in the first step by measuring a current flowing through the main drain power source line or the main source power source line. Features.

According to another aspect of the present invention, there is provided a semiconductor device evaluation method for evaluating characteristics of a transistor to be measured, as a third solving means relating to the semiconductor evaluation method. When performing the characteristic evaluation using the first test mode using the described semiconductor device,
A first step of setting a state of a test signal input to the selection signal supply circuit to a state corresponding to a first test mode;
A desired stress voltage is supplied to the drain power supply line, a desired stress voltage is supplied to the source power supply line, and a desired stress voltage is supplied to the gate power supply line to perform a stress test on all the transistors under measurement. And a second step.

Further, the present invention provides a semiconductor device evaluation method for evaluating characteristics of a transistor under measurement as a fourth solution means related to a semiconductor evaluation method, wherein any one of the above second to sixth solution means is provided. When performing the characteristic evaluation using the second test mode using the described semiconductor device,
A first step of setting a state of a test signal input to the selection signal supply circuit to a state corresponding to a second test mode;
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
And measuring a current flowing in the main drain power source line or the main source power source line to perform characteristic evaluation of all the transistors under measurement.

Further, the present invention provides a semiconductor device evaluation method for evaluating characteristics of a transistor under measurement as a fifth solving means relating to a semiconductor evaluation method,
A first step of performing a characteristic evaluation of the transistor under measurement using the semiconductor device evaluation method according to the first or second solving means and obtaining a first characteristic evaluation result;
A second step of applying stress to the transistor under measurement for a desired time using the method for evaluating a semiconductor device according to the third means following the first step;
Subsequent to the second step, using the semiconductor device evaluation method described in the first or second solving means, a third characteristic evaluation is performed to obtain a second characteristic evaluation result by performing a characteristic evaluation of the transistor under measurement. And having a process
The stress time dependency of the transistor under measurement is derived based on the first characteristic evaluation result, the second characteristic evaluation result, and the time.

Further, the present invention provides a semiconductor device evaluation method for evaluating characteristics of a transistor under measurement as a sixth solving means relating to a semiconductor evaluation method,
Using the semiconductor device evaluation method according to the second solution means, a first step of performing characteristic evaluation of the transistor under measurement of the n × m evaluation cells and obtaining a first characteristic evaluation result;
A second step of selecting one of the semiconductor device evaluation methods described in the first or second solving means based on the first characteristic evaluation result;
A third step of performing the characteristic evaluation of the transistors under measurement of some evaluation cells of the n × m evaluation cells by the selected evaluation method;
It is characterized by having.

Further, according to the present invention, as a seventh solving means relating to the semiconductor evaluation method, the semiconductor device described in the sixth solving means is arranged in 2 rows and k columns (k is a positive integer), and the first solution A semiconductor device evaluation method for evaluation using the semiconductor device evaluation method described in the means,
In the first step, the test signal, the selection control signal, the column address signal, and the row address signal are simultaneously input to the plurality of arranged semiconductor devices to set the same mode,
In the second step, a desired drain voltage is supplied to the main drain power supply line, and a desired source voltage is supplied to the main source power supply line for each of the plurality of semiconductor devices arranged. Supplying a desired gate voltage to the main gate power line;
In the third step, the evaluation cell selected in the first step is measured by measuring a current flowing through the main drain power source line or the main source power source line of each of the plurality of semiconductor devices arranged. The characteristics of the transistor under measurement are evaluated.

Further, according to the present invention, as an eighth solution according to the semiconductor evaluation method, the semiconductor device described in the sixth solution is arranged in 2 rows and k columns (k is a positive integer), and the second solution. A semiconductor device evaluation method for evaluating using the semiconductor device evaluation method described in the means,
In the first step, the test signal, the selection control signal, the column address signal, and the row address signal are simultaneously input to the plurality of arranged semiconductor devices to set the same mode,
In the second step, a desired drain voltage is supplied to the main drain power supply line, and a desired source voltage is supplied to the main source power supply line for each of the plurality of semiconductor devices arranged. Supplying a desired gate voltage to the main gate power line;
In the third step, the evaluation cell selected in the first step is measured by measuring a current flowing through the main drain power source line or the main source power source line of each of the plurality of semiconductor devices arranged. The characteristics of the transistor under measurement are evaluated.

According to the present invention, as a ninth solution according to the semiconductor evaluation method, the semiconductor device described in the sixth solution is arranged in 2 rows and k columns (k is a positive integer), and the third solution. A semiconductor device evaluation method for evaluation using the semiconductor device evaluation method described in the means,
In the first step, the test signals are simultaneously input to the plurality of semiconductor devices arranged to set the first test mode,
In the second step, the drain, the source voltage, and the gate voltage are supplied to all the transistors under measurement of the plurality of semiconductor devices arranged.

According to the present invention, as a tenth solving means related to the semiconductor evaluation method, the semiconductor device described in the sixth solving means is arranged in 2 rows and k columns (k is a positive integer), and the fourth solution. A semiconductor device evaluation method for evaluation using the semiconductor device evaluation method described in the means,
In the first step, the test signal is simultaneously input to the plurality of semiconductor devices arranged to set the second test mode,
In the second step, a desired drain voltage is supplied to the main drain power supply line, and a desired source voltage is supplied to the main source power supply line for each of the plurality of semiconductor devices arranged. Supplying a desired gate voltage to the main gate power line;
In the third step, by measuring the current flowing through the main drain power source line or the main source power source line of each of the plurality of semiconductor devices arranged in the plurality, all the transistors under measurement for each of the semiconductor devices. Characteristic evaluation is performed.

The present invention also provides a semiconductor device evaluation method for evaluating the characteristics of a transistor under measurement as an eleventh means for solving the semiconductor evaluation method,
A first step of performing a characteristic evaluation of the transistor under measurement using the semiconductor device evaluation method according to the seventh or eighth solving means and obtaining a first characteristic evaluation result;
A second step of applying stress to the transistor under measurement for a desired time using the method for evaluating a semiconductor device according to the ninth means following the first step;
Subsequent to the second step, the semiconductor device evaluation method described in the seventh or eighth means is used to evaluate the characteristics of the transistor under measurement and obtain a second characteristic evaluation result. And having a process
The stress time dependency of the transistor under measurement is derived based on the first characteristic evaluation result, the second characteristic evaluation result, and the time.

Further, the present invention provides a semiconductor device evaluation method for evaluating characteristics of a transistor under measurement as a twelfth solving means relating to a semiconductor evaluation method,
Using the semiconductor device evaluation method according to the eighth solving means, a first step of performing a characteristic evaluation of the transistor under measurement of the n × m evaluation cells and obtaining a first characteristic evaluation result;
A second step of selecting one of the semiconductor device evaluation methods described in the seventh or eighth solving means based on the first characteristic evaluation result;
And a third step of evaluating the characteristics of the transistors under measurement in some of the n × m evaluation cells by the selected evaluation method.

According to the present invention, a switch for applying a stress voltage to the source, drain, and gate terminals of a transistor under measurement of an evaluation cell arranged in a matrix of n rows and m columns is provided, and the switch is selected to open or close the row. The selection circuit to which the signal and the column selection signal are input is used.
Thereby, while measuring and evaluating the transistor under measurement of one evaluation cell among the n × m evaluation cells, the stress voltage application state can be maintained in the transistors under measurement of the remaining evaluation cells. Therefore, according to the present invention, it is possible to realize a semiconductor device capable of accurately obtaining the characteristic change amount corresponding to the stress time for each transistor to be measured.

It is a circuit block diagram of the semiconductor device which concerns on one Embodiment of this invention. It is a circuit block diagram of the evaluation cell in FIG. It is a circuit block diagram of the selection signal supply circuit of the semiconductor device which concerns on one Embodiment of this invention. It is a circuit block diagram of the cell test circuit in FIG. FIG. 5 is a circuit configuration diagram of a counter circuit in FIG. 4. FIG. 5 is a circuit configuration diagram of a counter control circuit in FIG. 4 and a timing chart regarding its operation. FIG. 5 is a circuit configuration diagram of a decode signal output circuit and a selector circuit in FIG. 4. It is a truth table regarding operation | movement of the semiconductor device which concerns on one Embodiment of this invention. 3 is a timing chart regarding the operation of the semiconductor device according to the embodiment of the present invention. 3 is a timing chart regarding the operation of the semiconductor device according to the embodiment of the present invention. 3 is a timing chart regarding the operation of the semiconductor device according to the embodiment of the present invention. 3 is a timing chart regarding the operation of the semiconductor device according to the embodiment of the present invention. It is a table | surface which shows the bias state of the to-be-measured transistor using the semiconductor device which concerns on one Embodiment of this invention. It is a layout conceptual diagram of the semiconductor device concerning one embodiment of the present invention. It is a specification figure of the pad electrode of the semiconductor device which concerns on one Embodiment of this invention. It is a conceptual diagram at the time of performing 4-chip simultaneous measurement of the semiconductor device which concerns on one Embodiment of this invention. It is a terminal specification figure of the probe card used in the case of the measurement of FIG. It is a circuit block diagram of the semiconductor device which concerns on one Embodiment of this invention. It is a circuit block diagram of the evaluation cell in FIG. It is a supplementary explanatory drawing regarding the semiconductor device which concerns on one Embodiment of this invention. It is a circuit block diagram of the conventional semiconductor device.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit configuration diagram of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device according to the present embodiment is provided in n × m evaluation cells C11 to Cnm arranged in a matrix of n rows and m columns (n and m are positive integers). This is a DMA-TEG for evaluating the characteristics of the measured transistor. In one evaluation cell, a transistor under test DUT, which is a P-channel MOS (Metal Oxide Semiconductor) transistor manufactured by a fine process of 45 nm, for example, is provided. The detailed internal circuit configuration of the evaluation cells C11 to Cnm will be described later.

  The semiconductor device according to the first embodiment has a normal evaluation mode and first and second test modes as operation modes. In the normal evaluation mode, the transistor under test DUT in any evaluation cell can be measured and evaluated among the above-mentioned n × m evaluation cells by two access methods. Further, in the DUT full selection mode (second test mode), a voltage is collectively supplied to terminals such as the drains of the transistors under test DUT of all evaluation cells, and Ion (current flowing between the source and drain), etc. Can be measured and evaluated. Further, in the DUT all non-selection mode (first test mode) test mode, a stress voltage such as NBTI is applied by collectively supplying stress voltage to terminals such as drains of the transistors under test DUT of all evaluation cells. be able to. In the normal evaluation mode, a stress voltage can be applied to the measured transistors DUT of all remaining evaluation cells while measuring and evaluating the measured transistor DUT of one evaluation cell.

In FIG. 1, a drain stress line DVS (drain power supply line) is a power supply line for applying a stress voltage to the drain of the transistor under measurement, and one end thereof is a drain stress terminal DVSP for connection to an external power supply device. Connected with.
The source stress line SVS (source power line) is a power line for applying a stress voltage to the source of the transistor under measurement, and one end of the source stress line SVS is connected to a source stress terminal SVSP for connection to an external power supply device. Yes.
The gate stress line GVS (gate power supply line) is a power supply line for applying a stress voltage to the gate of the transistor under measurement, and one end thereof is connected to a gate stress terminal GVSP for connection to an external power supply device. Yes.

The main drain force line DF (main drain power supply line) is a power supply line for supplying a drain voltage to the transistor under measurement, and one end thereof is a drain power supply terminal DFP for connection to an external power supply device (not shown). And connected.
The main source force line SF (main source power supply line) is a power supply line for supplying a source voltage to the transistor under measurement, and one end of the main source force line SF is connected to a source power supply terminal SFP for connecting to an external power supply device. Yes.
The main gate force line GF (main gate power supply line) is a power supply line for supplying a gate voltage to the transistor under measurement, and one end of the main gate force line GF is connected to a gate power supply terminal GFP for connecting to an external power supply device. Yes.

The sub-drain force lines DF1 to DFm (sub-drain power supply lines) are provided for each column, and are power supply lines for supplying a drain voltage to the transistor under measurement of the evaluation cell belonging to each column. Specifically, the sub-drain force line DF1 is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the sub-drain force line DFm is connected to the evaluation cells C1m to Cnm belonging to the m-th column. .
The sub-gate force lines GF1 to GFm (sub-gate power supply lines) are provided for each column, and are power supply lines for supplying a gate voltage to the transistor under measurement of the evaluation cell belonging to each column. Specifically, the sub-gate force line GF1 is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the sub-gate force line GFm is connected to the evaluation cells C1m to Cnm belonging to the m-th column. .
The sub source force lines SF1 to SFm (sub source power supply lines) are provided for each column, and are power supply lines for supplying a source voltage to the transistor under measurement of the evaluation cell belonging to each column. Specifically, the sub source force line SF1 is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the sub source force line SFm is connected to the evaluation cells C1m to Cnm belonging to the m column. .

The main drain sense line DS (main drain voltage detection line) is a voltage detection line for detecting the drain voltage of the transistor under measurement, and one end thereof is a drain sense for connecting to an external voltage measuring device (not shown). It is connected to the terminal DSP.
The main gate sense line GS (main gate voltage detection line) is a voltage detection line for detecting the gate voltage of the transistor under measurement, and one end of the main gate sense line GS is connected to a gate sense terminal GSP for connection to an external voltage measuring device. Has been.
The main source sense line SS (main source voltage detection line) is a voltage detection line for detecting the source voltage of the transistor under measurement, and one end of the main source sense line SS is connected to the source sense terminal SSP for connection to an external voltage measuring device. Has been.

The sub-drain sense lines DS1 to DSn (sub-drain voltage detection lines) are voltage detection lines provided for each row and for detecting the drain voltage of the transistor under measurement of the evaluation cell belonging to each row. Specifically, the sub-drain sense line DS1 is connected to the evaluation cells C11 to C1m belonging to the first row, and the sub-drain sense line DSn is connected to the evaluation cells Cn1 to Cnm belonging to the n-th row. .
The sub-gate sense lines GS1 to GSn (sub-gate voltage detection lines) are provided for each row and are voltage detection lines for detecting the gate voltage of the transistor under measurement of the evaluation cell belonging to each row. Specifically, the sub-gate sense line GS1 is connected to the evaluation cells C11 to C1m belonging to the first row, and the sub-gate sense line GSn is connected to the evaluation cells Cn1 to Cnm belonging to the n-th row. .
The sub source sense lines SS1 to SSn (sub source voltage detection lines) are provided for each row, and are voltage detection lines for detecting the source voltage of the transistor under measurement of the evaluation cell belonging to each row. Specifically, the sub-source sense line SS1 is connected to the evaluation cells C11 to C1m belonging to the first row, and the sub-source sense line SSn is connected to the evaluation cells Cn1 to Cnm belonging to the n-th row. .

  The column selection lines Y1 to Ym are provided for each column and are selection lines for selecting an evaluation cell belonging to each column. One end of each column selection line Y1 to Ym is connected to a Y select main decoder MDY (corresponding to the Y select main decoder MDY in FIG. 3). Y select signals (column selection signals) YS1 to YSm output from the Y select main decoder MDY are input to the evaluation cells belonging to the respective columns via the respective column selection lines Y1 to Ym. Specifically, for example, the column selection line Y1 of the first column is connected to the evaluation cells C11 to Cn1 belonging to the first column, and the Y selection signal YS1 output from the Y selection main decoder MDY is the column selection line Y1. To the evaluation cells C11 to Cn1. Similarly, for example, the column selection line Ym of the mth column is connected to the evaluation cells C1m to Cnm belonging to the mth column, and the Y selection signal YSm output from the Y selection main decoder MDY is passed through the column selection line Ym. To the evaluation cells C1m to Cnm.

  The row selection lines X1 to Xn are provided for each row and are selection lines for selecting evaluation cells belonging to each row. One end of each row selection line X1 to Xn is connected to an X select main decoder MDX (corresponding to the X select main decoder MDX in FIG. 3). X select signals (row selection signals) XS1 to XSn output from the X select main decoder MDX are input to the evaluation cells belonging to the respective rows via the respective row selection lines X1 to Xn. Specifically, for example, the row selection line X1 of the first row is connected to the evaluation cells C11 to C1m belonging to the first row, and the X selection signal XS1 output from the X selection main decoder MDX is the row selection line X1. To the evaluation cells C11 to C1m. Similarly, for example, the row selection line Xn of the nth row is connected to the evaluation cells Cn1 to Cnm belonging to the nth row, and the X selection signal XSn output from the X selection main decoder MDX passes through the row selection line Xn. To the evaluation cells Cn1 to Cnm.

The power supply line switching circuits PSW1 to PSWm are provided for each column, and connect the sub-drain force line and the main drain force line DF belonging to the column according to the Y select signal supplied to the column selection line belonging to each column. Or a circuit in which the sub-source force line and the main source force line SF belonging to the column are connected or disconnected, and the sub-gate force line and the main gate force line GF belonging to the column are connected or disconnected. is there.
Each of the power supply line switching circuits PSW1 to PSWm is composed of three N-channel MOS transistors. Specifically, for example, the power line switching circuit PSW1 belonging to the first column includes a transistor DFT1 (drain power line switching circuit), a transistor GFT1 (gate power line switching circuit), and a transistor SFT1 (source power line switching circuit). Has been.

  The drain terminal of the transistor DFT1 is connected to the main drain force line DF, the source terminal is connected to the sub-drain force line DF1 belonging to the first column, and the gate terminal is connected to the column selection line Y1 belonging to the first column. The drain terminal of the transistor GFT1 is connected to the main gate force line GF, the source terminal is connected to the sub-gate force line GF1 belonging to the first column, and the gate terminal is connected to the column selection line Y1 belonging to the first column. The drain terminal of the transistor SFT1 is connected to the main source force line SF, the source terminal is connected to the sub-source force line SF1 belonging to the first column, and the gate terminal is connected to the column selection line Y1 belonging to the first column.

  Similarly, the power line switching circuit PSWm belonging to the m-th column includes a transistor DFTm, a transistor GFTm, and a transistor SFTm. The drain terminal of the transistor DFTm is connected to the main drain force line DF, the source terminal is connected to the sub-drain force line DFm belonging to the mth column, and the gate terminal is connected to the column selection line Ym belonging to the mth column. The drain terminal of the transistor GFTm is connected to the main gate force line GF, the source terminal is connected to the sub-gate force line GFm belonging to the m-th column, and the gate terminal is connected to the column selection line Ym belonging to the m-th column. The drain terminal of the transistor SFTm is connected to the main source force line SF, the source terminal is connected to the sub-source force line SFm belonging to the m-th column, and the gate terminal is connected to the column selection line Ym belonging to the m-th column.

The detection line switching circuits SSW1 to SSWn are provided for each row, and connect or not connect the sub-drain sense line belonging to the row and the main drain sense line DS according to the X select signal supplied to the row selection line belonging to each row. This is a circuit that connects, connects or disconnects the sub-source sense line and main source sense line SS belonging to the row, and connects or disconnects the sub-gate sense line and main gate sense line GS belonging to the row.
Each of the detection line switching circuits SSW1 to SSWn is composed of three N-channel MOS transistors. Specifically, for example, the detection line switching circuit SSW1 belonging to the first row includes a transistor DST1 (drain detection line switching circuit), a transistor GST1 (gate detection line switching circuit), and a transistor SST1 (source detection line switching circuit). Has been.

  The source terminal of the transistor DST1 is connected to the main drain sense line DS, the drain terminal is connected to the sub-drain sense line DS1 belonging to the first row, and the gate terminal is connected to the row selection line X1 belonging to the first row. The source terminal of the transistor GST1 is connected to the main gate sense line GS, the drain terminal is connected to the sub-gate sense line GS1 belonging to the first row, and the gate terminal is connected to the row selection line X1 belonging to the first row. The source terminal of the transistor SST1 is connected to the main source sense line SS, the drain terminal is connected to the sub-source sense line SS1 belonging to the first row, and the gate terminal is connected to the row selection line X1 belonging to the first row.

  Similarly, the detection line switching circuit SSWn belonging to the nth row includes a transistor DSTn, a transistor GSTn, and a transistor SSTn. The source terminal of the transistor DSTn is connected to the main drain sense line DS, the drain terminal is connected to the sub-drain sense line DSn belonging to the nth row, and the gate terminal is connected to the row selection line Xn belonging to the nth row. The source terminal of the transistor GSTn is connected to the main gate sense line GS, the drain terminal is connected to the sub-gate sense line GSn belonging to the nth row, and the gate terminal is connected to the row selection line Xn belonging to the nth row. The source terminal of the transistor SSTn is connected to the main source sense line SS, the drain terminal is connected to the sub-source sense line SSn belonging to the nth row, and the gate terminal is connected to the row selection line Xn belonging to the nth row.

Next, a detailed internal circuit configuration of the evaluation cells C11 to Cnm will be described. Since the internal circuit configuration of each of the evaluation cells C11 to Cnm is common, the following description will be given with reference to FIG. 2 in which only the circuit portion related to the evaluation cell C11 is extracted from FIG.
As shown in FIG. 2, the evaluation cell C11 includes a measured transistor DUT, a selection circuit 10, a first transistor T1 (fourth switch), a second transistor T2 (fifth switch), and a third transistor T3. (Sixth switch), fourth transistor T4 (seventh switch), fifth transistor T5 (eighth switch), sixth transistor T6 (ninth switch), seventh transistor T7 (thin switch) 1 switch), an eighth transistor T8 (second switch), and a ninth transistor T9 (third switch).
As described above, the transistor DUT to be measured is a P-channel MOS transistor manufactured by a fine process of 45 nm, for example. The first transistor T1 to the ninth transistor T9 are 3V N-channel MOS transistors with stable characteristics, and the selection circuit 10 is also composed of 3V MOS transistors manufactured by the same process. .

In the selection circuit 10, one input terminal is connected to a row selection line (X1 in this case) belonging to its own row (where the evaluation cell is located in the DMA), and the other input terminal is a column belonging to its own column. It is connected to a selection line (here, Y1) and is itself measured in response to an X selection signal XS1 supplied to the connected row selection line X1 and a Y selection signal YS1 supplied to a column selection line Y1. A selection signal indicating selection / non-selection of the transistor DUT is output. Specifically, the selection circuit 10 includes a NAND circuit 10a (negative AND circuit) and a logic inversion circuit 10b (inverter circuit).
In the NAND circuit 10a, one input terminal is connected to a row selection line (here, X1) belonging to its own row, and the other input terminal is connected to a column selection line (here, Y1) belonging to its own column. . Then, a NAND signal of the X select signal XS1 supplied to the row selection line X1 and the Y select signal YS1 supplied to the column selection line Y1 is converted into a logic inversion circuit 10b and a seventh transistor T7 (first switch). To the ninth transistor T9 (third switch). The logic inversion circuit 10b logically inverts the output signal of the NAND circuit 10a, and sends a selection signal indicating selection / non-selection of the transistor under test DUT to the first transistor T1 (fourth switch) to the sixth transistor. Output to T6 (9th switch).

The first transistor T1 connects or disconnects the sub-drain force line DF1 belonging to its own column (here, the first column) and the drain terminal of its own transistor under test DUT according to the selection signal. The drain terminal is connected to the sub-drain force line DF1, the source terminal is connected to the drain terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the logic inverting circuit 10b). ing.
The second transistor T2 connects or disconnects the sub-source force line SF1 belonging to its own column (here, the first column) and the source terminal of its own measured transistor DUT according to the selection signal. The source terminal is connected to the sub-source force line SF1, the drain terminal is connected to the source terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the logic inverting circuit 10b). ing.
The third transistor T3 connects or disconnects the sub-gate force line GF1 belonging to its own column (here, the first column) and the gate terminal of its own transistor under test DUT according to the selection control signal. The drain terminal is connected to the sub-gate force line GF1, the source terminal is connected to the gate terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the logic inverting circuit 10b). Has been.

The fourth transistor T4 connects or disconnects the sub-drain sense line DS1 belonging to its own row (here, the first row) and the drain terminal of its own transistor under test DUT according to the selection signal. The source terminal is connected to the sub-drain sense line DS1, the drain terminal is connected to the drain terminal of the transistor under test DUT, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the logic inverting circuit 10b). ing.
The fifth transistor T5 connects or disconnects the sub-source sense line SS1 belonging to its own row (here, the first row) and the source terminal of its own transistor DUT to be measured according to the selection signal. The source terminal is connected to the sub-source sense line SS1, the drain terminal is connected to the source terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the logic inverting circuit 10b). ing.
The sixth transistor T6 connects or disconnects the sub-gate sense line GS1 belonging to its own row (here, the first row) and the gate terminal of its own transistor DUT to be measured according to the selection signal. The source terminal is connected to the sub-gate sense line GS1, the drain terminal is connected to the gate terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the logic inverting circuit 10b). ing.

The seventh transistor T7 connects or disconnects the drain stress line DVS and the drain terminal of its own transistor under test DUT according to the selection signal, and its source terminal is connected to the drain stress line DVS. The drain terminal is connected to the drain terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the NAND circuit 10a).
The eighth transistor T8 connects or disconnects the source stress line SVS and the source terminal of the transistor under test DUT of its own according to the selection signal, and the source terminal is connected to the source stress line SVS. The drain terminal is connected to the source terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the NAND circuit 10a).
The ninth transistor T9 connects or disconnects the gate stress line GVS and the gate terminal of the transistor under test DUT of its own according to the selection signal, and its source terminal is connected to the gate stress line GVS. The drain terminal is connected to the gate terminal of the transistor DUT to be measured, and the gate terminal is connected to the output terminal of the selection circuit 10 (specifically, the NAND circuit 10a).

  As described above, the semiconductor device according to the present embodiment employs a completely separated Kelvin sense method capable of performing Kelvin sense evaluation for each measured transistor as the circuit configuration of the evaluation cell. Here, before describing the operation of the semiconductor device according to the present embodiment, a complete separation type Kelvin sensing method as a premise thereof will be described with reference to FIG. In FIG. 20, portions corresponding to those in FIG. 1 are omitted, circuits corresponding to the power supply line switching circuit PSW1 and the detection line switching circuit SSW1 are omitted, and the drain terminal and the main drain force line of the first transistor T1 are omitted. DF is directly connected, the source terminal of the second transistor T2 and the main source force line SF are directly connected, the drain terminal of the third transistor T3 and the main gate force line GF are directly connected, and the fourth The source terminal of the transistor T4 and the main drain sense line DS are directly connected, the source terminal of the fifth transistor T5 and the main source sense line SS are directly connected, and the source terminal of the sixth transistor T6 and the main gate sense line are connected. The case where it connects directly with GS is shown in figure.

  In FIG. 20, when the Y select signal YS1 and the X select signal XS1 indicating the logic level “1” are supplied to the column selection line Y1 and the row selection line X1, and the evaluation cell C11 is selected, the NAND circuit of the selection circuit 10 A signal indicating a logic level “0” is output from the circuit 10a, and a signal indicating a logic level “1” is output from the logic inversion circuit 10b. As a result, all of the first transistor T1 to the sixth transistor T6 are turned on, the drain terminal of the transistor DUT to be measured is connected to the main drain force line DF and the main drain sense line DS, and the source terminal is the main source force. The gate terminal is connected to the main gate force line GF and the main gate sense line GS, and is connected to the line SF and the main source sense line SS.

  In this state, the drain voltage is supplied from the external power supply device to the main drain force line DF, the source voltage is supplied to the main source force line SF, and the gate voltage is supplied to the main gate force line GF. The measurement transistor DUT is driven to detect the drain voltage generated in the main drain sense line DS, and also to detect the source voltage generated in the main source sense line SS and the gate voltage generated in the main gate sense line GS. Perform characterization.

On the other hand, when the Y select signal YS1 or the X select signal XS1 indicating the logic level “0” is output to at least one of the column selection line Y1 and the row selection line X1, and the evaluation cell C11 is not selected, the selection circuit 10 The output is a logic level “0”. In this case, all of the first transistor T1 to the sixth transistor T6 are turned off, and the measured transistor DUT is not selected.
As described above, in the evaluation cell adopting the complete separation type Kelvin sense method, a switch (transistor) is provided for each transistor to be measured, and it becomes possible to evaluate Kelvin sense completely separated. Evaluation is possible.

  However, for example, in the case where the evaluation cells shown in FIG. 20 are arranged in a matrix of n = m = 128 and a medium-scale DMA-TEG capable of evaluating 16K measured transistors DUT is configured, one evaluation target is provided. Assume that it takes about 10 μs to characterize the measurement transistor DUT. Then, it takes about 128 × 128 × 10 μsec≈0.16 sec until the last transistor under test DUT is evaluated after the stress voltage is applied. During this time, in the measured transistor DUT, the first transistor T1 to the sixth transistor T6 are off, and no stress voltage is applied. In general, in the NBTI test, the characteristics of the PMOS transistor are recovered in the order of milliseconds, which causes a problem that the characteristic variation corresponding to the time during which the stress is actually applied cannot be measured accurately.

In order to avoid such a problem, it is conceivable to evaluate the characteristics of each transistor under test DUT immediately after applying the stress voltage. However, it takes about 16K times the stress time to apply the stress voltage. As a result, there arises a problem that the measurement time increases.
Further, in order to put the 16K measured transistors DUT of the measured transistor DUT into the stress voltage application state, it is necessary to turn on all the gates of the first transistor T1 to the sixth transistor T6 described above. There is also a problem that a large current is consumed for charging / discharging and charging / discharging of the selection circuit 10 and the like. In addition, due to the current consumption when all the gates are turned on, the measurement of the transistor DUT to be measured has to wait for a certain time in order to stabilize the internal potential of the selection circuit and the like.

  Therefore, in the present embodiment, when the DMA-TEG is configured by arranging evaluation cells adopting the complete separation type Kelvin sense method in a matrix form, as described with reference to FIG. 2, the column selection belonging to each column is selected. In accordance with the Y select signal supplied to the line and the X select signal supplied to the row selection line belonging to each row, the first drain terminal DF1 and the drain terminal of its own transistor DUT to be connected are connected or disconnected. The transistor T1, the sub-source force line SF1, and the second transistor T2 that connects or disconnects the source terminal of the transistor under test DUT, or the sub-gate force line GF1 connects the gate terminal of the transistor under test DUT The third transistor T3 to be disconnected, the sub-drain sense line DS1, and the transistor to be measured A fourth transistor T4 that connects or disconnects the drain terminal of the DUT, a fifth transistor T5 that connects or disconnects the source terminal of the transistor under test DUT and the sub-source sense line SS1, and a sub-gate sense line GS1 A sixth transistor T6 for connecting or disconnecting the gate terminal of the transistor under test DUT with or without connecting to the drain stress line DVS and a drain terminal of the transistor under test DUT with its own connection or disconnecting. An eighth transistor T8 that connects or disconnects the source stress line SVS and the source terminal of the transistor under test DUT itself, and a ninth transistor T8 that connects or disconnects the gate stress line GVS and the gate terminal of the transistor under test DUT itself. The transistor T9 is provided.

Further, the evaluation cell includes a selection circuit 10 including a NAND circuit 10a and a logic inversion circuit 10b, and the output signal of the NAND circuit 10a is sent from the seventh transistor T7 (first switch) to the ninth transistor T9. (The third switch) is input to the gate, and the output signal of the logic inversion circuit 10b is input to the gates of the first transistor T1 (fourth switch) to the sixth transistor T6 (the ninth switch). Let
This solves the above problem by applying a stress voltage to the measured transistors DUT of the remaining evaluation cells during evaluation of the measured transistor DUT of one evaluation cell.

  Hereinafter, in the description of the operation of the semiconductor device according to the present embodiment shown in FIG. 1, a stress voltage is applied to the measured transistors DUT of the remaining evaluation cells while evaluating the measured transistor DUT of one evaluation cell. The principle will be described. In the following, a case where the transistor under test DUT of the evaluation cell C11 is selected as an evaluation target will be described as an example.

  First, when the Y select signal YS1 and the X select signal XS1 indicating the logic level “1” are supplied to the column selection line Y1 and the row selection line X1, and the evaluation cell C11 is selected, the power line switching circuit belonging to the first column The transistors DFT1, GFT1, and SFT1 in PSW1 are all turned on. Thereby, the sub drain force line DF1 and the main drain force line DF belonging to the first column are connected, the sub gate force line GF1 and the main gate force line GF are connected, and the sub source force line SF1 and the main source force line are connected. SF is connected.

  On the other hand, since the Y selection signals YS2 to YSm indicating the logic level “0” are supplied to the column selection lines Y2 to Ym belonging to the other columns (second column to m column), the second column to m column. Each transistor in the power supply line switching circuits PSW2 to PSWm belonging to the eyes is turned off. Thus, the sub-drain force lines DF2 to DFm, the sub-gate force lines GF2 to GFm, and the sub-source force lines SF2 to SFm belonging to the second to m-th columns are the main drain force line DF, the main gate force line GF, and the main gate force line GF. The source force line SF is disconnected.

  At this time, since the transistor DST1, the transistor GST1, and the transistor SST1 in the detection line switching circuit SSW1 belonging to the first row are all turned on, the sub-drain sense line DS1 and the main drain sense line DS belonging to the first row are The sub-gate sense line GS1 and the main gate sense line GS are connected, and the sub-source sense line SS1 and the main source sense line SS are connected.

  On the other hand, since the X select signals XS2 to XSn indicating the logic level “0” are supplied to the row selection lines X2 to Xn belonging to the other rows (the second row to the nth row), the second row to the nth row. The transistors in the detection line switching circuits SSW2 to SSWn belonging to the eyes are turned off. Accordingly, the sub-drain sense lines DS2 to DSm, the sub-gate sense lines GS2 to GSm, and the sub-source sense lines SS2 to SSm belonging to the second to n-th rows are the main drain sense line DS, the main gate sense line GS, and the main The source sense line SS is disconnected.

  In the evaluation cell C11, a selection signal indicating a logic level “1” is output from the logic inverting circuit 10b constituting the selection circuit 10, and all of the first transistor T1 to the sixth transistor T6 are turned on. The drain terminal of the measured transistor DUT is connected to the sub-drain force line DF1 (that is, the main drain force line DF) and the sub-drain sense line DS1 (that is, the main drain sense line DS), and the source terminal is connected to the sub-source force line SF1. (Ie, the main source force line SF) and the sub source sense line SS1 (ie, the main source sense line SS), and the gate terminals thereof are the sub gate force line GF1 (ie, the main gate force line GF) and the sub gate sense line GS1 (ie, Main gate sense line GS).

  On the other hand, in cells other than the evaluation cell C11, that is, in the remaining (16k−1) evaluation cells C21 to Cnm, a selection signal indicating a logic level “0” is output from the logic inversion circuit 10b constituting the selection circuit 10. Is done. The drain terminal of the transistor DUT to be measured is the main drain force line DF and the main drain sense line DS, the source terminal is the main source force line SF and the main source sense line SS, and the gate terminal is the main gate force line GF and the main drain sense line DS. The gate sense lines GS are not connected to each other. However, since the selection signal indicating the logic level “1” is output from the NAND circuit 10a constituting the selection circuit 10, the drain terminal of the transistor DUT to be measured is the drain stress line DVS, and the source terminal is the source stress line SVS. The gate terminals are connected to the gate stress line GVS.

  In such a state, the drain voltage VD is supplied from the external power supply device to the drain power supply terminal DFP (main drain force line DF), the source voltage VS is supplied to the source power supply terminal SFP (main source force line SF), By supplying the gate voltage VG to the gate power supply terminal GFP (main gate force line GF), the transistor under test DUT of the evaluation cell C11 is driven. At this time, the voltage of the drain sense terminal DSP (main drain sense line DS) is measured by an external voltage measuring device, the voltage of the source sense terminal SSP (main source sense line SS), and the gate sense terminal GSP (main gate sense line). GS) is measured to monitor the drain terminal voltage, the source terminal voltage, and the gate terminal voltage of the transistor DUT to be measured, and the drain voltage VD supplied from the power supply device so that each terminal voltage becomes a desired voltage. The source voltage VS and the gate voltage VG are adjusted.

  For example, the drain voltage VD and the source voltage VS are fixed, and the current flowing between the drain and the source when the gate voltage VG is swung in a desired range is measured to evaluate the characteristics of the measured transistor DUT. In order to measure the drain current or the source current, an ammeter may be connected in series between the drain power supply terminal DFP or the source power supply terminal SFP and the power supply device.

  On the other hand, a drain stress voltage is supplied from an external power supply device to a drain stress terminal DVSP (drain stress line DVS), a source stress voltage is supplied to a source stress terminal SVSP (source stress line SVS), and a gate stress terminal GVSP (gate). By supplying a gate stress voltage to the stress line GVS), the transistors to be measured DUT of (16k−1) evaluation cells C21 to Cnm are put into a stress application state.

  In this way, while the evaluation cell C11 is selected and the characteristics of the measured transistor DUT are being evaluated, all of the first transistors T1 to T6 in the other evaluation cells C21 to Cnm are in the OFF state. Become. However, since all of the seventh transistor T7 to the ninth transistor T9 are in the on state, the measured transistor DUT in C21 to Cnm has a drain terminal having a drain stress line DVS and a source terminal having a source stress line SVS. The gate terminals are electrically connected to the gate stress line GVS. That is, during the evaluation of the measured transistor DUT of the evaluation cell C11, a stress voltage is applied to the remaining (16k−1) measured cells DUT of the evaluation cells C21 to Cnm.

Next, the configuration of the semiconductor device according to the present embodiment will be described in detail with reference to FIGS.
FIG. 3 is an overall circuit diagram of a circuit for supplying Y select signals YS1 to YSm to the column selection lines Y1 to Ym and supplying X select signals XS1 to XSn to the row selection lines X1 to Xn. As shown in FIG. 3, the semiconductor device according to the present embodiment includes a cell test circuit 20, an X select predecoder PDX, and a Y select predecoder PDY as circuits for supplying an X select signal and a Y select signal. , An X select main decoder MDX and a Y select main decoder MDY. In FIG. 3, it is assumed that n = m = 128. The cell test circuit 20, the X select predecoder PDX, the Y select predecoder PDY, the X select main decoder MDX, and the Y select main decoder MDY constitute a selection signal supply circuit in the present invention.

  The cell test circuit 20 includes a selector control signal SELCONT (selection control signal), a clock signal CLK (clock signal), a 7-bit Y address signal AY0 to AY6 (column address signal), and a 7-bit X address signal AX0 to AX6 (row). Address signal) and test signals TEST0 and TEST1 (two test signals). Based on these signals, X address decode signals AXDEC0 to AXDEC6 and AXDECB0 to 6 are generated and output to the X select predecoder PDX. Also, Y address decode signals AYDEC0-6 and AYDECB0-6 are generated and output to the Y select predecoder PDY.

  Hereinafter, Y address signals AY0 to AY6, which are 7-bit address signals, are integrated and represented as Y address signal AY <6: 0>. Similarly, X address signals AX0 to AX6 are represented as X address signal AX < 6: 0>. Y address decode signals AYDEC0-6 are represented as Y address decode signals AYDEC <6: 0>, Y address decode signals AYDECB0-6 are represented as Y address decode signals AYDECB <6: 0>, and similarly, X address decode signals AXDEC0. -6 are represented as X address decode signals AXDEC <6: 0>, and X address decode signals AXDECB0-6 are represented as X address decode signals AXDECB <6: 0>.

  In the following description, when all the logic levels of the Y address signal AY <6: 0> are “0”, that is, AY6 is the most significant bit (hereinafter referred to as MSB), and AY0 is the highest. When the logical level of AY <6: 0> is “0000000” as a low-order bit (Least Significant Bit: hereinafter referred to as LSB), this is expressed in hexadecimal as AY <6: 0> = “00h”. . For example, when the logical level of AY <6: 0> is “1111111”, “7Fh” is obtained. X address signal AX <6: 0>, Y address decode signal AYDECB <6: 0>, Y address decode signal AYDECB <6: 0>, X address decode signal AXDEC <6: 0> and X address decode signal AXDECB <6 : 0> is also expressed as “00h” in the same manner as the Y address signal AY <6: 0>.

FIG. 4 is an internal circuit configuration diagram of the cell test circuit 20. As shown in FIG. 4, the cell test circuit 20 includes 14 decode signal output circuits DC (decode signal output circuits DC0 to DC13), 14 selector circuits ST (selector circuits ST0 to ST13), a counter circuit CT, The counter control circuit CTMS and the cell test circuit 20 are composed of a plurality of logic inverting circuits that logically invert each of the selector control signal SELCONT, the Y address signal AY <6: 0>, and the X address signal AX <6: 0>. Has been.
In order to describe these circuits constituting the cell test circuit 20 in more detail, the counter circuit CT is shown in FIG. 5, the counter control circuit CTMS is shown in FIG. 6, and the decode signal output circuit DC and the selector circuit ST are shown. FIG. 7 shows the circuit configuration. Hereinafter, the circuit configuration of the cell test circuit 20 will be described with reference to the drawings.

First, the circuit configuration of the counter circuit CT in FIG. 4 will be described.
The counter circuit CT shown in FIG. 4 includes a counter mode setting signal ADRCNTM, a counter start address latch signal ADRLTCH, a counter address initialization signal ADRINIT input from the counter control circuit CTMS, a clock signal CLK input to the cell test circuit 20, The logical inputs of Y address signal AY <6: 0> and X address signal AX <6: 0> input to cell test circuit 20 are input, and counter address signals CA0-13 are sent to selector circuits ST0-13. Output. Hereinafter, the 14-bit counter address signals CA0 to CA13 are represented as counter address signals CA <13: 0>. Of the counter address signals CA <13: 0>, the counter address signal CA <6: 0> is a Y address signal AY <6: 0>, and the counter address signal CA <13: 7> is an X address signal AX <. 6: 0>. Also, hereinafter, the logical inversion signal of the counter address signal CA <13: 0> is the counter address signal CAB <13: 0>, and the logical inversion signal of the Y address signal AY <6: 0> is the Y address signal AYB <6: 0. >, The logical inversion signal of the X address signal AX <6: 0> is taken as the X address signal AXB <6: 0>.

  In the following description, when all the logic levels of the counter address signal CA <13: 0> are “0”, that is, the counter address signal CA13 is MSB and the counter address signal CA0 is LSB, CA <13: When the logical level of 0> is “00000000000000”, this is expressed in hexadecimal as CA <13: 0> = “0000h”. For example, when the logical level of CA <13: 0> is “11111111111111”, it is “3FFFh”. Similarly to the counter address signal CA <13: 0>, the counter address signal CAB <13: 0> is expressed as “0000h”, and the Y address signal AYB <6: 0> and the X address signal AXB <6. : 0>, the counter address signal CA <6: 0>, and the counter address signal CA <13: 7> are expressed as “00h” in the same manner as the Y address signal AY <6: 0> described above. To do.

  The counter circuit CT is connected to the counter control circuit CTMS in order to determine the counter start address in the count operation based on the logic levels of the Y address signal AYB <6: 0> and the X address signal AXB <6: 0>. Then, the count operation is performed based on the counter mode setting signal ADRCNTM, the counter start address latch signal ADRLTCH, and the counter address initialization signal ADRINIT input from the counter control circuit CTMS.

FIG. 5 is a specific circuit configuration diagram of the counter circuit CT, and FIG. 6 is a specific circuit configuration diagram of the counter control circuit CTMS that generates the above-described control signals for controlling the counter circuit CT.
The counter circuit CT shown in FIG. 5 is connected to a D-type flip-flop DFc0-13 with reset terminal, a selector circuit connected to the D terminal and CLK terminal of each D-type flip-flop, and a QB terminal of each D-type flip-flop. The logic inversion circuit is configured.
The counter circuit CT is synchronized with the rising edge of the first clock signal CLK during the count operation (period in which the logic level of the counter mode setting signal ADRCNTM input to the RB terminal of each D-type flip-flop is “1”). Then, the Y address signal AYB <6: 0> and the X address signal AXB <6: 0> are fetched, and the counter address signal CA <13: 0> corresponding to the logic level is output. Thereafter, in synchronization with the rising edge of the clock signal CLK, the counter value is incremented by 1, and the 14-bit address consisting of the counter address signal CA <13: 0> is incremented by 1.

  For example, when AY <6: 0> = AX <6: 0> = “00h”, the counter address signal CA <13: 0> = “0000h”, and the start address of the counter address is “0000h”. Thereafter, the counter address signal CA <13: 0> is incremented from “0001h” to “3FFFh” in synchronization with the rising edge of the clock signal CLK while the counter mode setting signal ADRCNTM is “1”. This is because AY <6: 0> is incremented by 1 from “00h” to “7Fh”, and every time the Y address returns from “7Fh” to “00h”, the X address is incremented by 1 from “00h” to “ It corresponds to increasing to “7Fh”.

In order to realize such a counting operation, the counter control circuit CTMS generates a control signal such as a counter mode setting signal ADRCNTM with the circuit configuration shown in FIG.
The counter control circuit CTMS shown in FIG. 6A is a logic circuit such as a D-type flip-flop DFcs1 and 2 having a reset terminal (RB terminal), a logic inversion circuit connected to the RB terminal and the QB terminal of each D-type flip-flop. It is composed of
The counter control circuit CTMS receives the selector control signal SELCONT, the test signal TEST0, the test signal TEST1, and the clock signal CLK, and supplies the counter mode setting signal ADRCNTM, the counter start address latch signal ADRLTTCH, and the counter address initialization signal ADRINIT to the counter circuit CT. Output.

FIG. 6B is an operation timing chart of the counter control circuit CTMS. Hereinafter, the operation of the counter control circuit CTMS shown in FIG. 6A will be described with reference to the timing chart shown in FIG.
Before the time tcs1, for example, when all the logic levels of the selector control signal SELCONT and the test signals TEST0 and TEST1 are “0”, the logic level of the counter mode setting signal ADRCNTM is “0” and the logic of the counter address initialization signal ADRINIT The level is “0”. Since the logic level of the counter mode setting signal ADRCNTM input to the RB terminal is “0”, the D-type flip-flop DFcs1 forcibly holds the logic level of the QB terminal (referred to as node A) at “1”. ing. The D-type flip-flop DFcs2 also forcibly sets the logic level of the QB terminal (referred to as node B) to “1” because the logic level of the counter start address latch signal ADRLTCH input to the RB terminal is “0”. Hold on. In this period, the D-type flip-flops DFcs1 and 2 have the logic level of each RB terminal being “0”, so that even if the input clock signal CLK is input, each node and output signal of the counter control circuit CTMS There is no change in the logic level.

  For example, when the logic level of the selector control signal SELCONT transitions to “1” at time tcs1, the logic level of the counter mode setting signal ADRCNTM transitions to “1”. However, since the clock signal CLK is not yet input, the logic level of the node A is held at “1”, and the logic level of the counter start address latch signal ADRLTCH remains “0”. Further, since the logic level of the node B of the D-type flip-flop DFcs2 is held at “1”, the logic level of the counter address initialization signal ADRINIT is changed by the transition of the logic level of the counter mode setting signal ADRCNTM to “1”. The level transitions to “1”.

When the logic level of the clock signal CLK transitions to “1” at time tcs2, the D-type flip-flop DFcs1 takes in “1” from the D terminal and sets the QB terminal (node A) to “0”. As a result, the logical level of the counter start address latch signal ADRLTCH changes to “1”. However, since the logic level of the CLK terminal is “0”, the D-type flip-flop DFcs2 holds the logic level of the QB terminal (node B) at “1”.
When the logic level of the clock signal CLK transitions to “0” at time tcs3, the D-type flip-flop DFcs2 captures “1” from the D terminal and sets the logic level of the node B to “0”. As a result, the logical level of the counter address initialization signal ADRINIT transitions to “0”. After that, even if the clock signal CLK is input, the logic level of the D terminal is fixed to “1”, so that the logic levels of the node A and the node B are kept “0”, and the counter start address latch signal The logic level of ADRLTCH is held at “1”, and the logic level of the counter address initialization signal ADRINIT is kept at “0”.

  At time tcs4, for example, when the logic level of the selector control signal SELCONT is “1” and the logic level of the test signal TEST0 changes to “1”, the logic level of the counter mode setting signal ADRCNTM changes to “0”. . In the D-type flip-flop DFcs1, since the logic level of the RB terminal to which the counter mode setting signal ADRCNTM is input becomes “0”, the logic level of the node A is changed to “1”, and the logic of the counter start address latch signal ADRLTCH The level is changed to “0”. The D-type flip-flop DFcs2 also changes the logic level of the node B to “1” because the logic level of the RB terminal to which the counter start address latch signal ADRLTCH is input is “0”. Thereafter, even when the clock signal CLK is input, the logic level of the D terminal of the D flip-flop DFcs1, the logic level of the node A, the logic level of the D terminal of the D flip-flop DFcs2, and the logic level of the node B are “1”. Therefore, there is no change in the logic level of each node and output signal of the counter control circuit CTMS.

At time tcs5, when the logic level of the selector control signal SELCONT is “1”, for example, when the logic level of the test signal TEST0 transitions to “0”, the logic level of the counter mode setting signal ADRCNTM is “1” as at time tcs1. ”. At this time, the logic level of the clock signal CLK is “1”. However, since the logic level of the counter mode setting signal ADRCNTM is “0” at the rising edge of the clock signal CLK, the node of the D-type flip-flop DFcs1 The logic levels of the node B of the A and D flip-flops DFcs2 are both held at “1”. Further, since the logic level of the node B is “1”, the logic level of the counter address initialization signal ADRINIT transitions to “1”.
At time tcs6, the clock signal CLK rises and then falls at time tcs7, so that the logic level of the counter start address latch signal ADRLTCH is changed to “1” at time tcs6 as in the case of time tcs2 and tcs3. At tcs7, the logical level of the counter address initialization signal ADRINIT is changed to “0”.

  As described above, when the logic level of the counter mode setting signal ADRCNTM becomes “1” by the combination of the logic levels of the selector control signal SELCONT and the test signals TEST0 and TEST1, the counter control circuit CTMS outputs the logic of the counter address initialization signal ADRINIT. The level is changed to “1”. Further, when the clock signal CLK is input with the logic level of the counter mode setting signal ADRCNTM being “1”, the logic level of the counter address initialization signal ADRINIT is synchronized with the fall of the first clock signal CLK. Is changed to “0”.

  Further, when the clock signal CLK is input when the logic level of the counter mode setting signal ADRCNTM is “1”, the counter control circuit CTMS synchronizes with the rising edge of the first clock signal CLK, and starts the counter start address latch. The logic level of the signal ADRLTCH is changed to “1”. When the logic level of the counter mode setting signal ADRCNTM transitions to “0”, the logic level of the counter start address latch signal ADRLTCH is transitioned to “0”.

The counter circuit CT shown in FIG. 5 has the above-described logical configuration of the counter control circuit CTMS that generates a control signal such as the input counter mode setting signal ADRCNTM. In response, the following counting operation is performed.
Before the logic level of the counter mode setting signal ADRCNTM becomes “1” (corresponding to before the time tcs1 in FIG. 6B), each RB of the D-type flip-flops DFc0 to 13 to which the counter mode setting signal ADRCNTM is input. Since the logic levels of the terminals are “0”, the logic levels of the respective QB terminals are all “1”, that is, the counter address signal CAB <13: 0> = “3FFFh”. Thereby, the counter address signal CA <13: 0> = “0000h”.

  When the logical level of the counter mode setting signal ADRCNTM becomes “1” (corresponding to the time tcs1 in FIG. 6B), the logical level of each RB terminal of the D flip-flops DFc0 to DFc13 becomes “1”. The counter circuit CT shifts to a count operation. In addition, when the logical level of the counter address initialization signal ADRINIT becomes “1”, each selector circuit connected to the D terminal has the Y address signal AYB <6: 0> and the X address signal AXB <6: 0>. Is output to the D terminal. The selector circuit connected to the CLK terminal outputs the counter start address latch signal ADRLTCH to the CLK terminal. However, since the logic level of the counter start address latch signal ADRLTCH is “0”, the logic levels of the respective QB terminals are all “1”, that is, the counter address signal CAB <13: 0> = “3FFFh”.

  When the first clock signal CLK is input (corresponding to the time tcs2 in FIG. 6B), the logic level of the counter start address latch signal ADRLTCH becomes “1”, and the D-type flip-flops DFc0 to 13 are connected to each D flip-flop DFc0-13. The Y address signal AYB <6: 0> and the X address signal AXB <6: 0> are fetched from the terminal, and the logic level of the QB terminal is changed. For example, if AY <6: 0> = “02h” and AX <6: 0> = “00h”, only the logic level of the QB terminal of the D-type flip-flop DFc1 becomes “0”, and other D-type flip-flops The logic levels of the QB terminals of the group are all “1”. That is, CAB <13: 0> = “3FFDh”. As a result, the counter address signal CA <13: 0> becomes “0002h”. That is, the start address in the count operation is set according to the logic level of the address signal input to the cell test circuit.

  When the first clock signal CLK falls (corresponding to time tcs3 in FIG. 6B), the logic level of the counter address initialization signal ADRINIT becomes “0”, and the D terminal of each D-type flip-flop Are electrically disconnected and electrically connected to each QB terminal. The clock signal CLK is input to the CLK terminal of the D-type flip-flop DFc0, and the CLK terminals of the other D-type flip-flops are electrically connected to the QB terminal of the preceding D-type flip-flop. Note that the counter address signal CA <13: 0> remains “0002h”.

Thereafter, the counter circuit CT advances the count operation in synchronization with the rising edge of the clock signal CLK. That is, the counter circuit CT increments the counter address signal CA <13: 0> bit by bit with “0002h” as the start address, and every time “0003h”, “0004h” and the clock signal CLK are input. Incremented counter address signal CA <13: 0> is generated and output to selector circuits ST0-ST13.
When the logic level of the counter mode setting signal ADRCNTM becomes “0” (corresponding to the time tcs4 in FIG. 6B), the logic of each RB terminal of the D-type flip-flops DFc0 to 13 to which the counter mode setting signal ADRCNTM is input. Since the levels are all “0”, the logic levels of the respective QB terminals are all “1”, that is, the counter address signal CAB <13: 0> is “3FFFh”. As a result, the counter address signal CA <13: 0> is reset to “0000h”.

  As described above, the counter circuit CT performs the Y address signal AYB <6: in synchronization with the rising edge of the first clock signal CLK during the counting operation (period in which the logic level of the counter mode setting signal ADRCNTM is “1”). 0> and X address signal AXB <6: 0> are fetched, and counter address signal CA <13: 0> corresponding to the logic level is output. Thereafter, in synchronization with the rising edge of the clock signal CLK, the counter value is incremented by 1, and the 14-bit address consisting of the counter address signal CA <13: 0> is incremented by 1. Further, as shown in FIG. 4, the counter circuit CT outputs a counter address signal CA <13: 0> to the selector circuits ST0 to ST13.

Next, the selector circuits ST0 to ST13 in FIG. 4 will be described with reference to FIG.
The selector circuit ST shown in FIG. 7A has the same circuit configuration as the selector circuits ST0 to ST13. As shown in FIG. 7A, the selector circuit ST includes a logic inversion circuit, an N channel type MOS transistor, and a P channel type MOS transistor.
The selector circuit ST includes a SEL signal that is a logical inversion signal of the selector control signal SELCONT, a counter address signal CA (one bit of the counter address signal CA <13: 0>), and an X address signal AX or a Y address signal AY. (One bit of either the X address signal <6: 0> or the Y address signal <6: 0> corresponding to any one bit of the counter address signal CA <13: 0>) and the SEL signal The counter address signal CA and either the X address signal AX or the Y address signal AY are selectively output to the decode signal output circuit DC as the address signal ATEST according to the logic level.

  Specifically, when the logic level of the SEL signal is “0” (that is, the logic level of the selector control signal SELCONT is “1”), the counter address signal CA is output, and the logic level of the SEL signal is “1” ( That is, when the logic level of the selector control signal SELCONT is “0”), the X address signal AX or the Y address signal AY is output. That is, the selector circuit ST has an X address signal AX or a Y address signal AY (first address mode) and a counter address signal (second address mode) according to the state of the selector control signal SELCONT (selection control signal). Are output to the decode signal output circuit DC.

Next, the decode signal output circuits DC0 to DC13 in FIG. 4 will be described with reference to FIG.
The decode signal output circuit DC shown in FIG. 7B has the same circuit configuration as the decode signal output circuits DC0 to DC13.
As shown in FIG. 7B, the decode signal output circuit DC is composed of a logic inversion circuit and a NAND circuit, and the output signal ATEST of the selector circuit ST, the logic inversion signal TESTB0 of the test signal TEST0, and the test A logic inversion signal TESTB1 of the signal TEST1 is input.

  The decode signal output circuit DC outputs the output signal ATEST of the selector circuit ST when the logic levels of both the TESTB0 signal and the TESTB1 signal are “1” (that is, when the logic levels of both the test signals TEST0 and TEST1 are “0”). The address decode signal ADEC, which is a signal having the same logic level as the output signal, and the address decode signal ADECB, which is a logical inversion signal thereof, are output.

Further, in the decode signal output circuit DC, the logic level of TESTB0 is “0” (the logic level of test signal TEST0 is “1”) and the logic level of TESTB1 is “1” (the logic level of test signal TEST1 is “0”). In this case, address decode signals ADEC and ADECB having a logic level of “0” are output.
Furthermore, the decode signal output circuit DC is not related to the logic level of TESTB0 (regardless of the level of the test signal TEST0), and when the logic level of TESTB1 is “0” (the logic level of the test signal TEST1 is “1”), Address decode signals ADEC and ADECB having a logic level of “1” are output.

By configuring the decode signal output circuit DC and the selector circuit ST as described above, the decode signal output circuit DC0 shown in FIG. 4 has the logic level of the selector control signal SELCONT and the test signal TEST0. When both logical levels of TEST1 and TEST1 are "0", the Y address decode signal AYDEC0, which is a signal having the same logical level as the Y address signal AY0, is output, and the Y address decode signal AYDECB0, which is a logical inversion signal thereof, is output. .
The decode signal output circuit DC0 has a counter address signal output from the counter circuit CT when the logic level of the selector control signal SELCONT is “0” and the logic levels of both the test signals TEST0 and TEST1 are “0”. A Y address decode signal AYDEC0, which is a signal having the same logic level as CA0, is output, and a Y address decode signal AYDECB0, which is a logical inversion signal thereof, is output.

On the other hand, when the test signal TEST0 is “1” and the test signal TEST1 is “0” regardless of the logic level of the selector control signal SELCONT, the decode signal output circuit DC0 performs address decoding with the logic level “0”. Signals AYDEC0 and AYDECB0 are output.
Further, the decode signal output circuit DC0 has the address decode signals AYDEC0 and AYDECB0 having the logic level “1” when the logic level of the test signal TEST1 is “1” regardless of the logic levels of the selector control signal SELCONT and the test signal TEST0. Is output.

  Similarly, the decode signal output circuits DC1 to DC6 are connected to the selector circuits ST1 to ST6, respectively, and output Y address decode signals AYDEC1 to AYDEC1 and AYDECB1 to 6, respectively. That is, for example, the decode signal output circuit DC6 receives the output signal of the selector circuit ST6, the TESTB0 signal, and the TESTB1 and inputs the Y address decode signal AYDEC6 according to the logic levels of the selector control signal SELCONT, TEST0 signal, and TEST1 signal. And Y address decode signal AYDECB6.

  Similarly, the decode signal output circuits DC7 to DC13 that output the X address decode signal are also connected to the selector circuits ST7 to ST13, respectively, and output X address decode signals AXDEC0 to AXDECB0 to AXDECB0 to 6, respectively. That is, for example, the decode signal output circuit DC13 receives the output signal of the selector circuit ST13, the TESTB0 signal, and the TESTB1, and inputs the X address decode signal AXDEC6 according to the logic levels of the selector control signal SELCONT, TEST0 signal, and TEST1 signal. And the X address decode signal AXDECB6.

The above is the description of the cell test circuit 20, and the description will be continued below by returning to FIG.
The Y select predecoder PDY predecodes the Y address decode signals AYDEC <6: 0> and AYDECB <6: 0> input from the cell test circuit 20, and then outputs a predecode signal as a result of the Y decode. Output to select main decoder MDY. The Y select main decoder MDY generates Y select signals YS1 to YSm (m = 128) based on the predecode signal input from the Y select predecoder PDY and supplies it to the column select lines Y1 to Ym.

  The X select predecoder PDX predecodes the X address decode signals AXDEC <6: 0> and AXDECB <6: 0> input from the cell test circuit 20, and then outputs the predecode signal, which is the result of the process, to X Output to the main decoder MDX for selection. The X select main decoder MDX generates X select signals XS1 to XSn (n = 128) based on the predecode signals input from the X select predecoder PDX and supplies them to the row select lines X1 to Xn.

FIG. 8 shows a truth table representing the relationship between the input signal and the output signal of the semiconductor device configured as described above. In FIG. 8, “X” indicates “Invalid”, that is, the logical level “0” or “1” does not relate to the operation mode.
As shown in FIG. 8, when the logic levels of both the test signals TEST0 and TEST1 are “0” and the logic level of the selector control signal SELCONT is “0” (indicated by No. 1 in the figure), the semiconductor device is The normal evaluation mode (random access: first address mode in the normal evaluation mode) is entered. Then, the Y address decode signal AYDEC <6: 0> and the X address decode signal AXDEC <6, which are signals of the same logic level as the input Y address signal AY <6: 0> and X address signal AX <6: 0>. : 0> and Y address decode signal AYDECB <6: 0> and X address decode signal AXDECB <6: 0>, which are logically inverted signals, are output. For example, if AY <6: 0> = “02h” and AX <6: 0> = “00h”, then AYDEC <6: 0> = “02h”, AXDEC <6: 0> = “00h”, AYDECB <6: 0> = “7Dh” and AXDECB <6: 0> = “7Fh” are output.

  When the logic levels of both the test signals TEST0 and TEST1 are “0” and the logic level of the selector control signal SELCONT is “1”, the semiconductor device operates in the normal evaluation mode (counter access: second in the normal evaluation mode). Address mode). Then, the Y address decode signal AYDEC <6: 0>, which is a signal having the same logic level as the counter address signal CA <6: 0> output from the counter circuit CT, is output, and the Y address decode signal which is a logical inversion signal thereof. AYDECB <6: 0> is output. Further, the X address decode signal AXDEC <6: 0>, which is a signal having the same logic level as the counter address signal CA <13: 7> output from the counter circuit CT, is output, and the X address decode signal which is a logical inversion signal thereof. AXDECB <6: 0> is output.

  In the counter access, as described above, the logical levels of the Y address signal AY <6: 0> and the X address signal AX <6: 0> captured at the first rising edge of the clock signal CLK are set to the counter address signal CA. The logic levels of <6: 0> and counter address signal CA <13: 7> are set (setting of the start address indicated by No. 2-1 in the figure). Subsequently, the counter address signal CA <13: 0> is incremented bit by bit in synchronization with the rising edge of the clock signal CLK (indicated by No. 2-2 in the figure). For example, if AY <6: 0> = “04h” and AX <6: 0> = “02h” at the first rising edge of the clock signal CLK, CA <6: 0> = “04h”, CA <13. : 7> = “02h”, AYDEC <6: 0> = “04h”, AXDEC <6: 0> = “02h”, AYDECB <6: 0> = “7Bh”, AXDECB <6: 0> = “7Dh” is output. Subsequently, when the clock signal CLK is input, CA <6: 0> = “05h”, “06h”, “07h” and the counter address signal CA are incremented bit by bit from the LSB, and AYDEC <6: 0>. Are changed to “05h”, “06h”, “07h”, and AYDECB <6: 0> are changed to “7Ah”, “79h”, and “78h”.

  When the logic level of TEST1 is “1” (indicated by No. 3 in the figure) regardless of the logic levels of the selector control signal SELCONT and the test signal TEST0, the semiconductor device operates in the test mode (DUT full selection mode: first). 2 test mode) state. The logical levels of the Y address decode signal AYDEC <6: 0>, the Y address decode signal AYDECB <6: 0>, the X address decode signal AXDEC <6: 0>, and the X address decode signal AXDECB <6: 0> are all “1”. That is, AYDEC <6: 0> = AYDECB <6: 0> = AXDEC <6: 0> = AXDECB <6: 0> = “7Fh”.

  In addition, when the logic of the test signal TEST0 is “1” and the logic of the TEST1 is “0” (indicated by No. 4 in the drawing) regardless of the logic level of the selector control signal SELCONT, the semiconductor device is in the test mode (DUT All non-selection mode: first test mode) state. The logical levels of the Y address decode signal AYDEC <6: 0>, the Y address decode signal AYDECB <6: 0>, the X address decode signal AXDEC <6: 0>, and the X address decode signal AXDECB <6: 0> are all “0”. That is, AYDEC <6: 0> = AYDECB <6: 0> = AXDEC <6: 0> = AXDECB <6: 0> = “00h”.

Subsequently, the operation of the semiconductor device including the cell test circuit 20, the X-select predecoder PDX, the Y-select predecoder PDY, the X-select main decoder MDX, and the Y-select main decoder MDY as described above and the transistor under measurement A DUT evaluation method will be described with reference to FIGS.
FIG. 9 shows that the semiconductor device according to the present embodiment shifts from the normal evaluation mode (random access: first address mode in the normal evaluation mode) to the test mode (DUT all non-selection mode: first test mode). Then, it is a timing chart showing the temporal relationship of each signal when shifting to normal evaluation mode (random access: first address mode in normal evaluation mode) again.

FIG. 10 shows that the semiconductor device according to the present embodiment is between a normal evaluation mode (random access: first address mode in normal evaluation mode) and a test mode (DUT all non-selection mode: first test mode). 6 is a timing chart showing the temporal relationship of each signal when shifting.
FIG. 11 shows that the semiconductor device according to the present embodiment performs normal evaluation from the normal evaluation mode (random access: first address mode in the normal evaluation mode) after the test mode (DUT all non-selection mode: first test mode). It is a timing chart showing the temporal relationship of each signal when shifting to a mode (counter access: second address mode in normal evaluation mode).

  FIG. 12 shows that the semiconductor device according to the present embodiment shifts from the normal evaluation mode (counter access: the second address mode in the normal evaluation mode) to the test mode (DUT all non-selection mode: first test mode). FIG. 5 is a timing chart showing the temporal relationship of each signal when shifting to the normal evaluation mode (counter access: the second address mode in the normal evaluation mode) again.

  FIG. 13 shows the bias state of the transistor under test DUT in each mode, and corresponds to each mode in the truth table shown in FIG. In the figure, in the normal evaluation mode (random access and counter access), the transistor characteristics of the measured transistor DUT of any evaluation cell can be evaluated, and a stress voltage can be applied to the measured transistor DUT of other evaluation cells. In addition, in the DUT all non-selection (first test mode), a stress voltage can be applied to the measured transistors DUT of all the evaluation cells. These are described in detail below, including transitions between modes.

  In FIG. 9, the main drain force line DF is 0.95 V, the main source force line SF is 1.0 V, the main gate force line GF is 0.6 V, the drain stress line DVS and the source stress line SVS are 3.0 V, and the gate. The case where 0V is supplied to the stress line GVS is shown. The Y address signal AY <6: 0> and the X address signal AX <6: 0> represent addresses in hexadecimal as described above.

  For convenience of explanation, an evaluation cell selected by AY <6: 0> = “00h” and AX <6: 0> = “00h” is defined as an evaluation cell A0, and the drain terminal of the transistor DUT to be measured in the evaluation cell A0. The voltage is represented as VD (A0), the source terminal voltage is represented as VS (A0), and the gate terminal voltage is represented as VG (A0). Similarly, the evaluation cell selected by AY <6: 0> = “00h” and AX <6: 0> = “01h” is set as the evaluation cell A1, and the drain terminal voltage of the transistor DUT to be measured in the evaluation cell A1 is set to VD ( A1), the source terminal voltage is represented as VS (A1), and the gate terminal voltage is represented as VG (A1). Further, an evaluation cell selected by AY <6: 0> = “7Fh” and AX <6: 0> = “7Fh” is defined as an evaluation cell A2, and the drain terminal voltage of the transistor DUT to be measured in the evaluation cell A2 is set to VD (A2 ), The source terminal voltage is represented as VS (A2), and the gate terminal voltage is represented as VG (A2).

  As shown in FIG. 13, the bias state of the measured transistor DUT of the selected evaluation cell in the normal evaluation mode is 0.95V for the drain terminal voltage VD, 1.0V for the source terminal voltage VS, and 0 for the gate terminal voltage VG. The current flowing from the source terminal to the drain terminal in this state is measured and evaluated. In addition, the bias state of the measured transistor DUT of all the evaluation cells in the test mode is the drain terminal voltage VD and the source terminal voltage are 3.0 V, and the gate terminal voltage VG is 0 V. This state is the stress voltage in the NBTI test. It is in the state of being applied.

  As shown in FIG. 9, since the logic levels of both the test signals TEST0 and TEST1 are “0” and the logic level of the selector control signal SELCONT is “0” at times t1 to t2 and t3 to t4, the semiconductor device Is in the normal evaluation mode (random access: first address mode in the normal evaluation mode). Then, the Y address decode signal AYDEC <6: 0> and the X address decode signal AXDEC <6, which are signals of the same logic level as the input Y address signal AY <6: 0> and X address signal AX <6: 0>. : 0> and also outputs the Y address decode signal AYDECB <6: 0> and the X address decode signal AXDECB <6: 0>, which are the logical inversion signals.

That is, in this case, the evaluation cell arranged at a desired XY coordinate (row and column) by freely setting the Y address signal AY <6: 0> and the X address signal AX <6: 0> by the user. Can be selected (random access: first address mode in normal evaluation mode).
For example, when the evaluation cell A0 is selected at time t1, 0.95V is supplied to the main drain force line DF, 1.0V to the main source force line SF, and 0.6V to the main gate force line GF. The drain terminal voltage VD (A0) of the transistor under test DUT of the evaluation cell A0 is 0.95V, the source terminal voltage VS (A0) is 1.0V, and the gate terminal voltage VG (A0) is 0.6V. A current flows to the terminal (corresponding to the bias state of the transistor under test DUT in the random access mode in FIG. 13).

On the other hand, for the (16K−1) evaluation cells other than the evaluation cell A0, since the logic level of the output of the logic inverting circuit 10b in the selection circuit 10 is “0”, the measured transistor DUT has a main drain force. It is not electrically connected to the line DF, the main source force line SF, and the main gate force line GF.
Therefore, as described above, the current of only the evaluation cell A0 can be measured by the ammeter connected in series between the drain power supply terminal DFP or the source power supply terminal SFP and the power supply device.

  For (16K−1) evaluation cells other than the evaluation cell A0, the logical level of the output of the NAND circuit 10a in the selection circuit 10 is “1”, and the drain stress line DVS and the source stress line SVS have 3 Since 0 V is supplied to the gate stress line GVS, the drain terminal voltage VD and the source terminal voltage VS of the transistor DUT to be measured are 3.0 V and the gate terminal voltage as in the evaluation cells A1 and A2 shown in the figure. VG becomes 0V. That is, a stress voltage in the NBTI test is applied to the measured transistor DUT (corresponding to a bias state other than the measured transistor DUT in the random access mode in FIG. 13).

Next, when the address is switched from AY <6: 0> = “00h” and AX <6: 0> = “01h”, the evaluation cell becomes the evaluation cell A1 from the evaluation cell A0, and the transistor under test DUT of the evaluation cell A1 The drain terminal voltage VD (A1) of the transistor is 0.95V, the source terminal voltage VS (A1) is 1.0V, the gate terminal voltage VG (A1) is 0.6V, and the current flows from the source terminal to the drain terminal of the transistor DUT to be measured. Flows. (This corresponds to the bias state of the transistor DUT under measurement in the random access mode in FIG. 13).
On the other hand, in the evaluation cell A0, the drain terminal voltage VD and the source terminal voltage VS of the measured transistor DUT are 3.0V, the gate terminal voltage VG is 0V, and the stress voltage in the NBTI test is applied (in FIG. 13). This corresponds to a bias state other than the transistor under test DUT in the random access mode).

  Thus, between time t1 and t2, AY <6: 0> and AX <6: 0> are changed from AY <6: 0> = “00h” and AX <6: 0> = “00h”. For example, the X address signal AX0 is changed to LSB and the Y address signal AY6 is changed to 1 bit at a time. Finally, the address is evaluated as AY <6: 0> = “7Fh” and AX <6: 0> = “7Fh”. The current of the transistor under test DUT in the cell A2 is measured and evaluated. Thereby, it is possible to measure and evaluate the currents of all the transistors under test DUT of 16K evaluation cells. In addition, the stress voltage in the NBTI test is applied to the measured transistors DUT of (16k−1) evaluation cells other than the evaluation cell being measured and evaluated.

  Next, in the test mode (time t2 to t3), when the logic level of the test signal TEST0 becomes “1” at time t2, the cell test circuit 20 causes the Y address decode signal AYDEC <6: 0> of “00h” and “00h” X address decode signal AXDEC <6: 0> is output, and “00h” Y address decode signal AYDECB <6: 0> and “00h” X address decode signal AXDECB <6: 0> are output. To do. Therefore, the logic level of the output of the NAND circuit 10a is “1” and the logic level of the output of the logic inverting circuit 10b is “0” among the selection circuits 10 of all the evaluation cells. In this case, like the evaluation cells A0 to A2 shown in the figure, the drain terminal voltage VD and the source terminal voltage VS of the measured transistors DUT of all the evaluation cells are 3.0 V, the gate terminal voltage VG is 0 V, and 16K pieces. The stress voltage of the NBTI test is applied to all the measured transistors DUT of the evaluation cell (corresponding to the bias state in which all DUTs are not selected in FIG. 13).

  Next, when the logic level of the test signal TEST0 becomes “0” at time t3, the test mode ends and the normal evaluation mode is entered. In the normal evaluation mode (time t3 to t4), the Y address signal AY <6: 0> and the X address signal AX <6: 0> are switched in the same order as the addresses at the previous times t1 to t2. It is possible to measure the drain currents of all the transistors DUT to be measured in 16K evaluation cells. In addition, at times t3 to t4, all the DUTs other than the DUT that measures and evaluates the current can be in a state where a stress voltage is applied.

  It is also possible to apply additional stress to the transistor under test DUT of the evaluation cell. In general, in the NBTI test of a PMOS transistor, it is known that the absolute value of the threshold voltage of the PMOS transistor tends to increase (the drain current decreases) as time passes. It is necessary to evaluate how it will change. In the semiconductor device according to the present embodiment, as described below, after the measurement evaluation after applying the stress voltage, a stress voltage can be additionally applied, so the dependency between the threshold voltage and the stress time is investigated. It is also possible to evaluate.

  FIG. 10 shows a transition from the normal evaluation mode after the test mode (random access: first address mode in the normal evaluation mode) to the test mode (DUT all non-selection mode: first test mode), and then normal evaluation again. It is a timing chart showing the temporal relationship of each signal when shifting to a mode (random access: first address mode in normal evaluation mode).

  FIG. 10 shows a case where the two bits of the evaluation cells A0 and A2 used in the description of FIG. 9 are accessed for convenience of description. In FIG. 10, the cell test circuit 20 is in the period (time t1 to t3, time t4 to t6, time t7 to t9) in which the logic levels of the selector control signal SELCONT, the test signal TEST0, and the test signal TEST1 are all “0”. In normal evaluation mode (random access: first address mode in normal evaluation mode). Then, in the remaining period, that is, the period in which the logic level of the test signal TEST0 is “1” (time t3 to t4, time t6 to t7), the cell test circuit 20 operates in the test mode (DUT all non-selection mode: first Test mode).

  For example, taking the evaluation cell A0 as an example, the initial characteristics before applying the stress voltage of the transistor under test DUT are measured and evaluated at times t1 to t2. At subsequent times t2 to t3, a stress voltage is applied to the evaluation cell A0 while the measured transistor DUT of the evaluation cell A2 is being measured and evaluated. Also, at times t3 to t4, since the measured transistors DUT of all the evaluation cells are in the all non-selection mode, the stress voltage is applied to the evaluation cell A0. Therefore, after the first stress time (t4-t2) has elapsed for the evaluation cell A0, the characteristics of the transistor under test DUT after the first stress voltage application are measured and evaluated at times t4 to t5. Similarly, after the second stress time (t7-t5) has elapsed, the characteristics of the transistor DUT after the second stress voltage application are measured and evaluated at times t7 to t8.

  Similarly, for the evaluation cell A2, the first stress time is (t5-t3) and the second stress time is (t8-t6), and each of these stress times is the same for each evaluation cell. Then, it can be set to the same time as the first and second stress times of the evaluation cell A0. In addition, since the user can arbitrarily set the time during which the logic level of the test signal TEST0 is “1” (time t3 to t4 and time t6 to 7), the first stress time and the second stress are described above. The user can arbitrarily set the time. Therefore, for the evaluation cells A0 and A2, for example, when creating a graph in which the horizontal axis is the stress time and the vertical axis is the source-drain current of the transistor under measurement, the evaluation cells A0 and A2 can be plotted at the same stress time. It becomes possible.

  Here, the evaluation cell (here, two bits of the evaluation cells A0 and A2), the number of times of stress application (here, twice), and the measurement content (here, current measurement) are examples. Therefore, by changing the number of stresses and the time for all 16k evaluation cells and evaluating them, it is also possible to determine, for example, the change dependency of the threshold voltage characteristics over the same stress time. It is possible to find out whether there is a transistor under test DUT (having a large characteristic variation in the NBTI test as compared with others).

In the above-described normal evaluation mode, the measurement evaluation operation by random access has been described. However, measurement evaluation by counter access (second address mode in the normal evaluation mode) can be performed.
FIG. 11 shows that the semiconductor device according to the present embodiment changes from the normal evaluation mode after the test mode (random access: first address mode in the normal evaluation mode) to the normal evaluation mode (counter access: second address in the normal evaluation mode). It is a timing chart showing the temporal relationship of each signal when shifting to (mode).

  During the period from the time t1 to the time t2, the evaluation cell of AY <6: 0> = “7Fh” and AX <6: 0> = “7Eh” is selected. Although not shown in FIG. The drain terminal voltage VD is 0.95 V, the source terminal voltage VS is 1.0 V, the gate terminal voltage VG is 0.6 V, and current flows from the source terminal to the drain terminal (in FIG. 13, the transistor under test DUT in the random access mode). Equivalent to the bias state).

In the period from time t2 to time t3, the evaluation cell with AY <6: 0> = “7Fh” and AX <6: 0> = “7Fh” is selected, and the drain terminal voltage VD of the transistor DUT to be measured is 0. .95 V, source terminal voltage VS is 1.0 V, and gate terminal voltage VG is 0.6 V, and current flows from the source terminal to the drain terminal (corresponding to the bias state of the transistor under test DUT in the random access mode in FIG. 13). ).
Subsequently, in the period from time t3 to time t4, the drain terminal voltage VD and source terminal voltage VS of the measured transistors DUT of all the evaluation cells are 3.0 V, the gate terminal voltage VG is 0 V, and 16K evaluation cells The stress voltage of the NBTI test is applied to all the transistors to be measured DUT (corresponding to the bias state in which all DUTs are not selected in FIG. 13).

In the period from time t4 to time t5 after the stress application, an evaluation cell with AY <6: 0> = “00h” and AX <6: 0> = “00h” is selected, and the drain terminal voltage VD of the transistor DUT to be measured Is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V, so that a current flows from the source terminal to the drain terminal (in FIG. 13, the measured transistor DUT is biased in the random access mode). Equivalent to).
In the subsequent period from time t5 to t6, the evaluation cell of AY <6: 0> = “00h” and AX <6: 0> = “01h” is selected, and the drain terminal voltage VD of the transistor DUT to be measured is 0. 95 V, source terminal voltage VS is 1.0 V, and gate terminal voltage VG is 0.6 V, and current flows from the source terminal to the drain terminal (corresponding to the bias state of the transistor under test DUT in the random access mode in FIG. 13). .

At time t6, when the logic level of the selector control signal SELCONT becomes “1”, the logic level of the SEL signal that is the logic inversion signal of the selector control signal SELCONT in FIG. 4 becomes “0”, and the selector circuits ST0 to ST13 Address signal CA is selectively output to decode signal output circuits DC0-13.
At this time, the counter circuit CT receives a counter mode setting signal ADRCNTM input to the RB terminals of the D-type flip-flops DFc0 to Dfc13 and a counter address initialization signal which is a selector circuit switching signal connected to the D terminal and the CLK terminal. The logic levels of ADRINIT are all “1” (corresponding to the above-described time tcs1 or tcs5 in FIG. 6B). As a result, the counter circuit CT shifts to the count operation, but since the clock signal CLK is not yet input, the logic level of the QB terminal (the logic level of the counter address signal CAB <13: 0>) is all “1”. is there. That is, the counter address signal CAB <13: 0> = “3FFFh”. Accordingly, the counter address signal CA <13: 0> becomes “0000h”, and the selector circuits ST0 to ST13 output the counter address signal CA whose logic level is “0” to the decode signal output circuits DC0 to DC13. To do.

  As a result, the cell test circuit 20 uses the “00h” Y address decode signal AYDEC <6: 0> (AYDECB <6: 0> is “7Fh”), and the “00h” X address decode signal AXDEC <6: 0>. (AXDECB <6: 0> is “7Fh”), and the evaluation cell A0 is selected. The drain terminal voltage VD of the measured transistor DUT of the selected evaluation cell A0 is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V, so that a current flows from the source terminal to the drain terminal ( In FIG. 13, this corresponds to the bias state of the transistor DUT under measurement in the counter access mode).

At time t7, when the first clock signal CLK is input, the logic level of the counter start address latch signal ADRLTCH in the counter circuit CT becomes “1”, and the D flip-flops DFc0 to DFc0-13 receive the address signal ( Y address signals AY0B to AY6B and X address signals AX0B to AX6B) are taken in and the logic level of the QB terminal is changed (corresponding to the time tcs2 or tcs6 in FIG. 6B).
In FIG. 11, since the Y address signal <6: 0> is “00h” and the X address signal is “02h”, only the logic level of the QB terminal of the D-type flip-flop DFc8 (CA8B logic level) is “0”. Thus, the logic levels of the QB terminals of the other D-type flip-flops are all “1”. Accordingly, the counter address signal CA <13: 0> is “0100h” (the counter address signal CA <6: 0> corresponding to the Y address signal AY and the X address signal AX is “00h”, and the counter address signal CA < 13: 7> becomes “02h”).

  The cell test circuit 20 outputs the Y address decode signal AYDEC <6: 0> of “00h” and the X address decode signal AXDEC <6: 0> of “02h” and the Y address decode signal AYDECB <7Fh of “7Fh”. The X address decode signal AXDECB <6: 0> of 6: 0> and “7Dh” is output. Thereby, in the semiconductor device, the evaluation cell of the corresponding address is selected, the drain terminal voltage VD of the transistor under test DUT of the evaluation cell is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is The voltage is 0.6 V, and a current flows from the source terminal to the drain terminal (corresponding to the bias state of the transistor DUT to be measured in the counter access mode in FIG. 13).

That is, the start address in the count operation is set according to the logic level of the address signal input to the cell test circuit 20, and the measured transistor DUT of the corresponding evaluation cell is measured and evaluated.
When the first clock signal CLK falls (corresponding to the time tcs3 or tcs7 in FIG. 6B described above), the logical level of the counter address initialization signal ADRINIT becomes “0”, and the D terminal of each D-type flip-flop Is electrically disconnected from the address signal and electrically connected to each QB terminal. The clock signal CLK is input to the CLK terminal of the D-type flip-flop DFc0, and the CLK terminals of the other D-type flip-flops are electrically connected to the QB terminal of the preceding D-type flip-flop.
Thereafter, in synchronization with the rise of the clock signal CLK at times t8, t9, and t10, the counter circuit CT performs a count operation, and the counter address signal CA <13: 0> uses “0100h” as a start address “0101h”. ”,“ 0102h ”, and“ 0103h ”are incremented bit by bit.

  The cell test circuit 20 sequentially changes the Y address decode signal AYDEC <6: 0> from “00h” to “01h”, “02h”, “03h”, and changes the X address decode signal AXDEC <6: 0> to “02h”. ”. Although not shown, the Y address decode signal AYDECB <6: 0> is sequentially shifted from “7Fh” to “7Eh”, “7Dh”, “7Ch”, and the X address decode signal AXDECB <6: 0> is changed to “7Dh”. ”. In any period from time t8 to t9, time t9 to t10, and time t10 to t11, the drain terminal voltage VD of the measured transistor DUT of the selected evaluation cell is 0.95 V, the source terminal voltage VS is 1.0 V, The gate terminal voltage VG becomes 0.6 V, and a current flows from the source terminal to the drain terminal (corresponding to the bias state of the measured transistor DUT in the counter access mode in FIG. 13).

  As described above, in the counter access, 0.95V is supplied to the main drain force line DF, 1.0V is supplied to the main source force line SF, and 0.6V is supplied to the main gate force line GF. The drain terminal voltage VD of the measured transistor DUT of the cell is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V. As a result, a current flows from the source terminal to the drain terminal of the transistor DUT to be measured, so that the current is selected by the ammeter connected in series between the drain power supply terminal DFP or the source power supply terminal SFP and the power supply device as described above. The current of only the evaluation cell can be measured.

  For (16K−1) evaluation cells other than the evaluation cell, the logic level of the output of the NAND circuit 10a in the selection circuit 10 is “1” as in random access, and the drain stress line DVS and the source stress are The line SVS is supplied with 3.0V, and the gate stress line GVS is supplied with 0V. As a result, the drain terminal voltage VD and the source terminal voltage VS of the measured transistor DUT are 3.0 V, the gate terminal voltage VG is 0 V, and the stress voltage in the NBTI test is applied to the measured transistor DUT.

Also in the counter access, it is possible to apply additional stress to the measured transistor DUT of the evaluation cell, similarly to the random access in FIG.
12 shows that the semiconductor device according to the present embodiment changes from the normal evaluation mode (counter access: the second address mode in the normal evaluation mode) in FIG. 11 to the test mode (all evaluation cells are not selected: the first test mode). It is a timing chart showing the temporal relationship of each signal when it transfers to normal evaluation mode (counter access: 2nd address mode in normal evaluation mode) again after that.
In FIG. 12, the operation of the semiconductor device in the period from time t6 to t11 is the same as the operation in the period from time t6 to t11 in FIG.

  At time t11, when the logic level of the test signal TEST0 becomes “1”, the cell test circuit 20 reads the “00h” Y address decode signal AYDEC <6: 0> and the “00h” X address decode signal AXDEC <6: 0> is output, and the Y address decode signal AYDECB <6: 0> of “00h” and the X address decode signal AXDECB <6: 0> of “00h” are output. Therefore, the logic level of the output of the NAND circuit 10a is “1” and the logic level of the output of the logic inverting circuit 10b is “0” among the selection circuits 10 of all the evaluation cells. As a result, the drain terminal voltage VD and the source terminal voltage VS of the measured transistors DUT of all the evaluation cells are 3.0 V, and the gate terminal voltage VG is 0 V. The NBTI test is performed on all the measured transistors DUT of 16K evaluation cells. The stress voltage is applied (corresponding to the DUT all unselected bias state in FIG. 13).

  Further, in the counter control circuit CTMS, the logic level of the counter mode setting signal ADRCNTM becomes “0” (corresponding to the time tcs4 in FIG. 6B described above), and therefore, in the counter circuit CT, the counter mode setting signal ADRCNTM. All the logic levels of the RB terminals of the D-type flip-flops DFc0 to 13 input to “0”. As a result, the counter address signal CA <13: 0> is reset to “0000h”, and the counter address signal CA <13: 7> corresponding to the Y address signal AY and the X address signal AX is “00h”. The address signal CA <6: 0> is “00h”.

When the logic level of the test signal TEST0 becomes “0” at time t12, the counter mode setting signal ADRCNTM input to the RB terminals of the D-type flip-flops DFc0 to Dfc13 and the D terminal and the CLK terminal are connected in the counter circuit CT. The logic level of the counter address initialization signal ADRINIT, which is the selector circuit switching signal, becomes “1” (corresponding to the above-described time tcs1 or tcs5 in FIG. 6B).
As a result, the counter circuit CT shifts to the count operation, but since the clock signal CLK is not yet input, the logic level of the QB terminal (the logic level of the counter address signal CAB <13: 0>) is all “1”. is there. That is, the counter address signal CAB <13: 0> = “3FFFh”. Therefore, since the counter address signal CA <13: 0> is “0000h”, the selector circuits ST0 to ST13 are all counter signals CA0 to which the logic level is “0” with respect to the decode signal output circuits DC0 to DC13. Is output.

  As a result, the cell test circuit 20 uses the “00h” Y address decode signal AYDEC <6: 0> (AYDECB <6: 0> is “7Fh”), and the “00h” X address decode signal AXDEC <6: 0>. (AXDECB <6: 0> is “7Fh”), and the evaluation cell A0 is selected. The drain terminal voltage VD of the measured transistor DUT of the selected evaluation cell A0 is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V, so that a current flows from the source terminal to the drain terminal ( In FIG. 13, this corresponds to the bias state of the transistor DUT under measurement in the counter access mode).

When the first clock signal CLK is input at time t13, the logical level of the counter start address latch signal ADRLTCH in the counter circuit CT becomes “1”, and the D flip-flops DFc0 to DFc0-13 receive the address signal ( Y address signals AY0B to AY6B and X address signals AX0B to AX6B) are taken in and the logic level of the QB terminal is changed (corresponding to the time tcs2 or tcs6 in FIG. 6B).
In FIG. 12, the Y address signal <6: 0> is “04h” and the X address signal is “02h”. Only the logic levels of CA2B and CA8B) are “0”, and the logic levels of the QB terminals of the other D-type flip-flops are all “1”. That is, CAB <13: 0> = “3EFBh”. Thus, the counter address signal CA <13: 0> is “0104h” (the counter address signal CA <6: 0> corresponding to the Y address signal AY is “04h”, and the counter address signal CA corresponding to the X address signal AX is set. <13: 7> is “02h”).

  The cell test circuit 20 outputs the Y address decode signal AYDEC <6: 0> of “04h” and the X address decode signal AXDEC <6: 0> of “02h” and the Y address decode signal AYDECB <7B ”of“ 7Bh ”. The X address decode signal AXDECB <6: 0> of 6: 0> and “7Dh” is output. Thereby, in the semiconductor device, the evaluation cell of the corresponding address is selected. The drain terminal voltage VD of the transistor under test DUT of the selected evaluation cell is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V, so that a current flows from the source terminal to the drain terminal (see FIG. 13 corresponds to the bias state of the transistor under test DUT in the counter access mode).

When the first clock signal CLK falls (corresponding to the time tcs3 or tcs7 in FIG. 6B described above), the logical level of the counter address initialization signal ADRINIT becomes “0”, and the D terminal of each D-type flip-flop Is electrically disconnected from the address signal and electrically connected to each QB terminal. The clock signal CLK is input to the CLK terminal of the D-type flip-flop DFc0, and the CLK terminals of the other D-type flip-flops are electrically connected to the QB terminal of the preceding D-type flip-flop.
Thereafter, in synchronization with the rise of the clock signal CLK at times t14, t15, and t16, the counter circuit CT performs a count operation, and the counter address signal CA <13: 0> has “0104h” as the start address “0105h”. "," 0106h "and" 0107h "are incremented bit by bit.

The cell test circuit 20 sequentially changes the Y address decode signal AYDEC <6: 0> from “04h” to “05h”, “06h”, “07h”, and changes the X address decode signal AXDEC <6: 0> to “02h”. ”. Although not shown, the Y address decode signal AYDECB <6: 0> is sequentially changed from “7Bh” to “7Ah”, “79h”, “78h”, and the X address decode signal AXDECB <6: 0> is changed to “7Dh”. ”. In any period of time t14 to t15, time t15 to t16, and time t16 to t17, the drain terminal voltage VD of the measured transistor DUT of the selected evaluation cell is 0.95 V, the source terminal voltage VS is 1.0 V, The gate terminal voltage VG becomes 0.6 V, and a current flows from the source terminal to the drain terminal (corresponding to the bias state of the measured transistor DUT in the counter access mode in FIG. 13).
As described above, also in the counter access, it is possible to apply additional stress to the measured transistor DUT of the evaluation cell, as in the random access.

FIG. 13 is a diagram in which the above-described evaluation method of the transistor under measurement in the semiconductor device of the present invention is arranged together with the bias state. As No in the figure, the same number as the operation mode classification in FIG. 8 is used.
As shown in FIG. 13, in the normal evaluation mode (indicated by No. 1 and No. 2 in the figure), the main drain force line DF is 0.95 V, the main source force line SF is 1.0 V, and the main gate force line GF is 0. Supply 6V. As a result, the drain terminal voltage VD of the transistor under test DUT of the evaluation cell is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V, and current flows from the source terminal to the drain terminal. Therefore, the current of the transistor under test DUT can be measured by an ammeter connected in series between the drain power supply terminal DFP or the source power supply terminal SFP and the power supply device.

Note that the above-described Ion is not the only item that can be measured in the normal evaluation mode. For example, 0 V is supplied to the main drain force line DF, 1.0 V is supplied to the main source force line SF and the main gate force line GF, the drain terminal voltage VD of the transistor DUT to be measured of the evaluation cell is 0 V, the source terminal voltage VS and the gate. By setting the terminal voltage VG to 1V, the off-current (Ioff) at the source-drain voltage of 1V can also be measured.
In addition, the voltage supplied to the main gate force line GF is changed within a desired range in a state where 0 V is supplied to the main drain force line DF and 1 V is supplied to the main source force line SF. For example, the voltage at which a source current of 1 microampere flows , The threshold voltage (Vt) at the source-drain voltage 1 V of the transistor under test DUT of the evaluation cell can also be obtained.

  For the remaining (16K-1) evaluation cells other than the evaluation cell, 3.0 V is supplied to the drain stress line DVS and the source stress line SVS, and 0 V is supplied to the gate stress line GVS, so that the transistor DUT to be measured is supplied. The drain terminal voltage VD and the source terminal voltage VS are 3.0 V, the gate terminal voltage VG is 0 V, and the stress voltage in the NBTI test is applied.

Further, as shown in FIG. 13, in the second test mode (all DUT selection indicated by No. 3 in the figure), all the evaluation cells are selected simultaneously, so that the drain power supply terminal DFP, the gate power supply terminal GFP, and the source power supply are selected. By applying each voltage to the measured transistors DUT of all the evaluation cells via the terminal SFP, the characteristics of all the measured transistors DUT can be collectively evaluated.
Specifically, the drain voltage VD = 0.95V is supplied to the main drain force line DF, the source voltage VS = 1.0V is supplied to the main source force line SF, and the gate voltage VG = 0 is supplied to the main gate force line GF. By supplying .6 V, the drain terminal voltage VD is 0.95 V, the source terminal voltage VS is 1.0 V, and the gate terminal voltage VG is 0.6 V in each of the measured transistors DUT of 16k evaluation cells. Current flows from the terminal to the drain terminal.

Therefore, the current of 16k transistors under test DUT can be measured by an ammeter connected in series between the drain power supply terminal DFP or the source power supply terminal SFP and the power supply device. Moreover, the average current of the transistor under test DUT in the DMA can be obtained by dividing the measurement result by 16k. For example, by using this test mode, it is possible to know in a short time whether or not a manufactured semiconductor device exhibits desired device characteristics.
Similarly to the above-described normal evaluation mode, voltages are supplied to the main drain force line DF, the main source force line SF, and the main gate force line GF, and measurement evaluation is performed, so that Ioff and Vt of the 16k transistors DUT to be measured. Can also be measured.

  On the other hand, as shown in FIG. 13, in the first test mode (DUT all unselected indicated by No. 4 in the figure), a stress voltage can be applied to the measured transistors DUT of all 16k evaluation cells. Specifically, by supplying 3.0 V to the drain stress line DVS and the source stress line SVS and 0 V to the gate stress line GVS, the drain terminal voltage VD and the source terminal voltage VS of each measured transistor DUT are 3. 0V and the gate terminal voltage VG are 0V, and the stress voltage in the NBTI test is applied to all 16k transistors DUT.

  As described above, by using the semiconductor device according to the present embodiment, in the normal evaluation mode (random access and counter access), the transistor characteristics of the measured transistor DUT of any evaluation cell can be evaluated. The stress voltage can be applied to the transistor under test DUT of other evaluation cells. In the first test mode, a stress voltage can be applied to the measured transistors DUT of all the evaluation cells. Therefore, in the normal evaluation mode, the characteristics of the transistor DUT to be measured are evaluated, the stress voltage is applied by shifting to the first test mode, and the characteristics of the transistor DUT to be measured is further shifted to the normal evaluation mode. Since the transistor under test DUT of the evaluation cell is in a state in which a stress voltage is applied except for the time during which the measurement is evaluated, the problem that the characteristics of the transistor under measurement after the measurement described above are recovered can be solved. .

  As described with reference to FIG. 11, in the normal evaluation mode, either random access or counter access can be used depending on the logic level of the selector control signal SELCONT. Regardless of which access method is used, the evaluation method of the transistor under measurement of the selected evaluation cell is the same as described above. Therefore, regardless of which access method is used, the transistor under measurement DUT of the evaluation cell is measured. The stress voltage is applied during the time other than the evaluation time.

  Moreover, the stress time applied to all the evaluation cells can be made the same. Referring to FIG. 9 described above, during the time of the first normal evaluation mode (time t1 to t2), the measurement of the measured transistors DUT of all the evaluation cells of 16K is performed in order, and the time of the first test mode At (time t2 to t3), a stress voltage is applied to the measured transistors DUT of all the evaluation cells. Next, during the subsequent normal evaluation mode time (time t3 to t4), the measured transistors DUT of all evaluation cells are measured in the same order as the previous times t1 to t2. In this way, the stress voltage application time of the transistor under test DUT of all evaluation cells is set to the time required for one evaluation cell × (16K−1) + test mode time (corresponding to the time t3−t2). be able to. Therefore, by using the semiconductor evaluation circuit according to this embodiment, the stress voltage application time of the transistors under test DUT of all evaluation cells can be made equal, and a highly accurate TEG can be provided.

  In the semiconductor device according to the present embodiment, the circuit configuration is such that the address signal and the output of the counter circuit CT are switched according to the logic level of the selector control signal SELCONT. For example, the logic level of the selector control signal SELCONT is changed. By fixing the logic levels of “1”, Y address signal AY <6: 0> and X address signal AX <6: 0> to “0”, it is possible to evaluate only in the counter access mode. . In that case, the address input pin is not necessary. Therefore, for example, when many semiconductor evaluation circuits according to embodiments of the present invention are measured and evaluated simultaneously after assembling the package, the number of pins for evaluation can be greatly reduced.

Further, as in the embodiment of the present invention, having random access and counter access has the following advantages.
(1) In measuring the initial characteristics, when evaluating the transistor under test DUT of the entire semiconductor device, it is not necessary to input an address every time the evaluation cell is changed. Therefore, the characteristics are evaluated in the counter access mode that can be controlled by the clock signal CLK. To do. For example, the Y address signal AY <6: 0> and the X address signal AX <6: 0> are set to “00h” and “00h”, the start address is set in the evaluation cell A0, and the clock signal CLK is input thereafter. The counter circuit CT counts up to “7Fh” and “7Fh” (the above-described evaluation cell A2), and the initial characteristics of all the transistors DUT to be measured can be acquired.

  (2) Next, after acquiring the data in (1), if a problem occurs such as gathering the measured transistors DUT with abnormal characteristics that deviate from the normal distribution in a specific area in the DMA, the address is found The area in question needs to be re-evaluated in detail again. In this case, it is possible to evaluate characteristics by combining random access and counter access. For example, when such a specific area occurs along the same X address on the outer periphery of the DMA, the address of the X address and the lowest address of the Y address in the area are input, and then the logic level of the selector control signal SELCONT is set to “1”. By inputting the clock signal CLK, measurement and evaluation of the transistor under test DUT in the specific region can be performed in more detail.

(3) Further, in the evaluation of (1) or (2) above, when a plurality of abnormal measured transistors DUT that deviate greatly from the normal distribution are found, it is necessary to specify the measured transistor DUT and perform detailed evaluation. In this case, it is possible to perform detailed measurement evaluation by directly inputting the address of the transistor DUT to be measured using the random read mode.
Thus, the semiconductor device of the present invention can use various modes depending on the purpose of the evaluation.

In the measurement evaluation in the above (2) and (3), the same drain, source, and gate voltages as in (1) may be supplied to the main drain force line DF or the like. Good. For example, the relevant evaluation cell is selected, 1V is supplied to the main drain force line DF, 0V is supplied to the main source force line SF, the voltage supplied to the main gate force line GF is changed from 1V to 0V, and VG− An ID curve may be obtained.
Also, for example, 0V is fixed to the main source force line SF and the voltage supplied to the main gate force line GF is fixed to several points (for example, fixed to four points of 0.75V, 0.5V, 0.25V, and 0V). The VD-ID curve may be obtained by changing the voltage supplied to the main drain force line DF from 1 V to 0 V in the supply voltage to each main gate force line GF.

Next, the measurement environment and the like in the evaluation of the semiconductor device will be described with reference to FIGS.
FIG. 14 is a conceptual diagram of the layout of the semiconductor device according to the embodiment of the present invention. In FIG. 14, P1 to P35 indicate pad electrodes. In the figure, the control circuit includes the X-select predecoder PDX, the Y-select predecoder PDY, the X-select main decoder MDX, the Y-select main decoder MDY, and the cell test circuit 20. . Although not shown, the 16k evaluation cells are arranged in a matrix, and 4k are arranged in each of the DUT arrays 1 to 4 in the figure.

  FIG. 15 is a specification diagram of each pad electrode in FIG. 14 and shows the pad number P, the pad name, and the contents (use). In FIG. 15, a pad for supplying a power supply voltage or the like is applied to pad electrodes P1 to P3, an evaluation pad for the transistor under measurement DUT is connected to pad electrodes P5 to P10, and a pad for applying a stress voltage to the transistor under measurement DUT is a pad electrode P11. To P13, control signal and the like and address signal pads input to the cell test circuit 20 are assigned to P15 to P35.

  In FIG. 14, 16k evaluation cells are divided into 4k by 4k in DUT arrays 1 to 4, because power wiring from pad electrodes P1 to P3 and pad electrodes P5 to P10 are connected to each evaluation cell. This is because the voltage drop is suppressed by reducing the wiring resistance of the measurement power supply wiring and the stress application wiring from the pad electrodes P11 to P13, and the measured transistor DUT is accurately measured.

  In addition, the 16k evaluation cells are divided into 4 kbits into the DUT arrays 1 to 4 so that the measured transistors DUT having different circuit constants (gate width W, gate length L, etc.) are arranged for each DUT array. Measurement evaluation can be made. For example, in the DUT arrays 1 to 4, it is possible to obtain data on L dependency of characteristic fluctuations such as Vt due to stress application, assuming that W of the transistor DUT to be measured has the same size and the size of L is different for each array. I can do it. In addition, it is assumed that L is the same size and W size is different in each of the DUT arrays 1 to 4 to obtain W dependency, or L and W are different in each of the DUT arrays 1 to 4 to obtain gate area dependency. It is good also as a structure which can be acquired.

  Further, the present invention is not limited to the above example, and the dimensions of the transistor DUT to be measured may be further changed in each DUT array. Alternatively, without changing the dimension of L or W in the layout, for example, when a wafer is manufactured, a dedicated reticle (photomask) is prepared, and the gate oxide film thickness of the transistors under measurement in the arrays 1 to 4 is set for each array. It is also possible to change. In general, it is said that the NBTI resistance deteriorates as the gate oxide film thickness decreases. Therefore, when determining the gate oxide film thickness in the process development, the NBTI evaluation characteristics corresponding to the four types of film thicknesses are obtained once. It can be collected by evaluation, and process conditions can be set quickly.

  Note that which one of the DUT arrays 1 to 4 is selected is determined by which address is used for the MSB and its lower address. In the above embodiment, the X address signal is selected. AX6 and AX5 correspond to such addresses. For example, depending on the combination of the logic levels of the X address signals AX6 and AX5 (AX6, AX5), (0, 0) is DUT array 1, (0, 1) is DUT array 2, (1,0) In the case of DUT array 3, the evaluation cell of DUT array 4 is selected in the case of (1, 1).

In FIG. 14, the PAD arrangement is arranged in a line on a straight line parallel to one side of the chip (semiconductor device) in order to facilitate simultaneous measurement of 4 chips (plural chips). The reason for this will be described with reference to FIGS.
FIG. 16 is a conceptual diagram of simultaneous measurement of four chips (a plurality of semiconductor devices) performed after the semiconductor device is manufactured up to the pad electrode formation step.
FIG. 17 is a diagram showing the terminal specifications of the probe card used for the simultaneous measurement of 4 chips. And pad number P is shown.

  In FIG. 16, the probe needles show only the probe needles that are in contact with the pad electrode P35 (Y address signal AY6 in FIG. 15) of each chip. The four probe needles are electrically connected to a probe card (not shown in FIG. 16) whose specifications are shown in FIG. 17, and are short-circuited by printed wiring in the probe card or a tester on which the probe card is mounted ( Shorted on the performance board of the semiconductor evaluation equipment. If a voltage is supplied to the terminal Q44 (Y address signal AY6) by the tester, the same voltage is supplied to the pad electrode P35 of the four chips through the four probe needles of the probe card. In this probe card in which four chips are measured simultaneously, most of the other pins are shared in order to reduce the number of tester pins used (number of terminals).

  For example, a tester supplies a voltage to the terminals Q31-44 of the probe card whose specifications are shown in FIG. Corresponding four chips of address signal input pad electrodes P19 to P35 are supplied with the same voltage in the four chips via probe needles in contact with the respective chips. Further, since the control signals input to the cell test circuit 20 correspond to the terminals Q45 to 48 and are common to all four chips, the operation mode of the four chips is the same by using the probe card whose specifications are shown in FIG. become.

Also, the power supply voltage (VDD), ground voltage (GND), stress voltage (G STRESS, D STRESS, S STRESS applied to the gate power supply line, drain power supply line, and source power supply line, respectively) corresponding to the terminals Q1 to Q6, and A well voltage (WELL) for supplying a back bias voltage to the transistor under measurement is commonly supplied to the four chips, and the four chips operate at the same power supply voltage and are applied with the same stress voltage.
On the other hand, the terminals Q7 to 30 are terminals used for measurement and evaluation of the transistor DUT to be measured, and are provided separately for each chip and each pad electrode so that the bias supplied to the chips 1 to 4 can be individually set. . That is, by using the probe card whose specifications are shown in FIG. 17, it is possible to set the voltages supplied to these pad electrodes to different voltages in the four chips.

  For example, by using the probe card whose specification is shown in FIG. 17, four chips are changed from the normal evaluation mode (random access: first address mode in the normal evaluation mode) to the test mode (DUT all non-selection mode: first test). In the case of shifting to the normal evaluation mode (random access: the first address mode in the normal evaluation mode), the operation of 4 chips is as follows. It is assumed that 0V is supplied to the terminal Q3 (gate stress terminal) of the probe card, and 3V is supplied to the terminal Q4 (drain stress terminal) and the terminal Q5 (source stress terminal).

  A predetermined voltage (for example, VDD = 1.2V, GND = 0V, WELL = 1.2V) is supplied to the terminals Q1, 2, and 6 (VDD, GND, WELL), and the test signal TEST0, which is input to the terminal Q45, the terminal When the logic levels of the test signal TEST1 input to Q46 and the selector control signal SELCONT input to the terminal Q48 are set to “0” (voltage level 0V), the chips 1 to 4 are in the normal evaluation mode (random access: normal evaluation mode). (First address mode).

For example, when the Y address signal AY <6: 0> = “00h” and the X address signal AX <6: 0> = “00h” are set, the evaluation cell A0 is selected in each of the chips 1 to 4. When 0.95V is supplied to the terminals Q10, 16, 22, and 28, 1.0V is supplied to the terminals Q12, 18, 24, and 30 and 0.6V is supplied to the terminals Q8, 14, 20, and 26, A drain voltage VD = 0.95V is supplied to the drain force line DF, a source voltage VS = 1.0V is supplied to the main source force line SF, and a gate voltage VG = 0.6V is supplied to the main gate force line GF.
Accordingly, in each of the chips 1 to 4, the drain terminal voltage VD (A0) of the transistor under test DUT of the evaluation cell A0 is 0.95V, the source terminal voltage VS (A0) is 1.0V, and the gate terminal voltage VG (A0). Becomes 0.6 V, and a current flows from the source terminal to the drain terminal. If the current flowing out from the terminals Q12, 18, 24, 30 corresponding to the source terminal is monitored in the tester, the current value of the transistor DUT to be measured can be individually acquired.

Since the terminals in the tester corresponding to the drain, source, and gate terminals of the transistor DUT to be measured are provided for each chip as shown in FIG. 17, the same voltage is applied to the chips 1 to 4 as described above. The transistor under test DUT may be measured and evaluated under different conditions by supplying voltages individually without supplying them.
Further, during the period when the measured transistor DUT of the evaluation cell A0 of each chip is being evaluated, a stress voltage is applied to the remaining (64k-4) measured transistors DUT from the terminals Q3 to Q5. The drain terminal voltage VD and the source terminal voltage VS are 3.0V, and the gate terminal voltage VG is 0V. That is, the transistor under test DUT is in a state where a stress voltage in the NBTI test is applied.

Further, in this mode, the user can freely set the Y address signal AY <6: 0> and the X address signal AX <6: 0>, whereby the evaluation arranged at the desired XY coordinates (row and column). The measured transistor DUT of the cell can be measured and evaluated.
For example, the Y address signal AY <6: 0> and the X address signal AX <6: 0> are changed from AY <6: 0> = “00h” and AX <6: 0> = “00h” to the X address signal AX0. LSB and Y address signal AY6 as MSB, and the address is changed bit by bit. Finally, the address is set to AY <6: 0> = “7Fh” and AX <6: 0> = “7Fh”. Then, by measuring and evaluating the current of the transistor under test DUT of the evaluation cell in each period, the current of all the transistors under test DUT of the 64K evaluation cells is converted to the 16k measurement time described in the operation description of FIG. Can be measured and evaluated at the same time.

  Next, when the logic level of the test signal TEST0 input to the terminal Q45 is set to “1” (voltage level 1.2 V), the chips 1 to 4 enter the test mode (DUT all non-selection mode: first test mode). Transition. A stress voltage is applied to the 64 k measured transistors DUT from the terminals Q3 to Q5, and the drain terminal voltage VD and the source terminal voltage VS are 3.0 V and the gate terminal voltage VG is 0 V, respectively. That is, all the transistors under test DUT are in a state where the stress voltage in the NBTI test is applied.

  Next, the logic level of the test signal TEST0 input to the terminal Q45 is set to “0” (voltage level 1.2V), so that the four chips are again in the normal evaluation mode (random access: first address in the normal evaluation mode). Mode). As in the normal evaluation mode described above, from AY <6: 0> = “00h” and AX <6: 0> = “00h”, the X address signal AX0 is LSB and the Y address signal AY6 is MSB bit by bit. Finally, the address is changed to AY <6: 0> = “7Fh” and AX <6: 0> = “7Fh”. Then, by measuring and evaluating the current of the measured transistor DUT of the evaluation cell in each period, it is possible to measure and evaluate the current of all the measured transistors DUT of the 64K evaluation cells after applying the stress voltage in the NBTI test. it can.

In this way, in the 4-chip simultaneous measurement, if the time required for measurement and evaluation of one measured transistor DUT is set to the same time as that for one-chip measurement, the measurement evaluation time for all the measured transistors DUT is measured by one chip. At the same time. That is, the measurement evaluation of the transistor under measurement can be performed four times in the same time. However, the number of transistors under test DUT that perform the NBTI test can be quadrupled in the same time (period in which the logic level of the test signal TEST0 is “1”).
In the four-chip simultaneous measurement described above, the same example as the transition of the operation mode in one chip described with reference to FIG. 9 has been described, but stress addition corresponding to the operation of FIG. 10 and the operation of FIG. The transition from the random mode to the counter mode and the stress addition in the counter mode corresponding to the operation of FIG. In any case, when the measured transistor DUT is measured and evaluated using the probe card whose specification is shown in FIG. 17, the XY coordinates (row and column) of the selected evaluation cell are the same in the chips 1 to 4.

When the measured transistor DUT of the evaluation cell at the coordinates is measured and evaluated, the same stress voltage is applied to the other measured transistors DUT. In the DUT all non-selection mode (shown as No. 4 in FIG. 13), the same stress voltage is applied to the transistors under test DUT of all four chips.
In the DUT all selection mode (shown in No. 3 in FIG. 13), Ion, Ioff, and Vt of 16k transistors under test DUT can be measured. Since each measurement terminal is provided separately, each of the above items can be measured under different bias conditions.

In addition, by using the simultaneous measurement probe card whose specifications are shown in FIG. 17, the number of terminals used in measurement by the tester can be reduced. The number of terminals of the probe card necessary for the measurement of the four chips of the semiconductor device is originally 120 times four times the 30 pad electrodes shown in FIG. 15, but the majority of the pad electrodes should be shared by using this probe card. Thus, a total of 48 terminals can be used, and the number of terminals used during test measurement can be reduced.
Further, as shown in FIG. 14, in the layout of the semiconductor device, since all the pad electrodes are arranged on a straight line parallel to one side of the chip constituting the semiconductor device, for example, even when four chips are measured simultaneously The probe needles on the probe card do not cross. In FIG. 16, the probe needles that are in contact with the pad electrodes of the chips 1 and 2 extend straight from the respective pads upward in the drawing, and the probe needles that are in contact with the pad electrodes of the chips 3 and 4 are upward from the pads in the drawing. It extends straight forward and each probe needle is connected to a probe card. Therefore, by adopting a configuration in which all pads are arranged on a straight line parallel to one side of the chip, each probe needle is not crossed in the probe card, and simultaneous measurement of a plurality of chips can be easily performed.

Although the embodiment of the present invention has been described in detail, the specific configuration is not limited to this embodiment, and includes design changes and the like within a scope not departing from the gist of the present invention. For example, in the example described above, a P-channel MOS transistor has been described as an example of the transistor to be measured, but the transistor to be measured may be an N-channel MOS transistor.
According to this embodiment, since different stress voltages can be applied to the drain terminal and the source terminal of the transistor under measurement of the evaluation cell, when the transistor under measurement is an N-channel MOS transistor, for example, a stress voltage is applied. In the first test mode, the drain terminal voltage VD is set to 3.0V, the source terminal voltage VS is set to 0V, and the gate terminal voltage VG is set to 1.5V.

Moreover, in the said embodiment, although the circuit shown in FIG. 2 was illustrated and demonstrated as an internal circuit structure of an evaluation cell, it is not limited to this, For example, even if the modification of an evaluation cell as shown in FIG. 19 is employ | adopted. good.
In FIG. 19, the eighth transistor T8 includes a drain stress line DVS (drain power supply line) and the source of the transistor under test DUT in response to the X select signal XS1 and the Y select signal YS1 supplied to the column selection line Y1. A terminal is connected or disconnected.
18 is a circuit configuration diagram of the semiconductor device on which the evaluation cell shown in FIG. 19 is mounted. The difference from the semiconductor device shown in FIG. 1 is that the source stress terminal SVSP is not provided. When the transistor under measurement is a P-channel type MOS transistor and the NBTI test is performed, the source stress terminal SVSP is omitted because there is no need to provide a difference between the source voltage and the drain voltage when applying the stress voltage in the first test mode. However, the number of pad electrodes is reduced.

  In addition, the number of transistors DUT to be measured is not limited to the above-described example. For example, assuming that m = 1024 and n = 1024, a total of 1 mega evaluation cells may each include a transistor DUT to be measured. In this case, 20 bits of the X address signal AX <9,0> and the Y address signal AY <9,0> are input to the cell test circuit 20.

  In addition, the relationship between rows and columns may be interchanged. For example, in the above example, the MSB is the X address signal AX6 and the LSB is the Y address signal AY0. However, the present invention is not limited to this. For example, the addresses from LSB to MSB may be in the order of AX2-6, AY0-6, AX0, AX1. In this case, when a 4-chip configuration is used in one chip, the array switching address signals are AX1 and AX0. When the logical level of both address signals is (A1, A0), the DUT array 1 is (A1, A0). = (0,0), array 2 is (A1, A0) = (0,1), array 3 is (A1, A0) = (1,0), and array 4 is (A1, A0) = ( 1, 1) may be selected.

At this time, the address signal input to the selector circuits ST0 to ST13 shown in FIG. 4 and the address signal input to the D-type flip-flops DFc0 to DFc13 of the counter circuit CT are the address signals determined by the above LSB to MSB. And its logic inversion signal is inputted in order.
Note that the number of array divisions is not limited to four, and can be divided by selecting an address of an arbitrary j (j is a positive integer) bit from the Y address signal and the X address signal. For example, if j = 3, the array division is 8, and the DUT arrays 1 to 8 can be switched using a 3-bit address signal.

  In the above embodiment, the number of chips to be simultaneously measured has been described as four. However, the number is not limited to this number. 2 × k pieces of probe cards are prepared by arranging two pieces in the vertical direction with respect to a straight line parallel to one side of the chip and k pieces (k is a positive integer) in the same direction as the straight line. These chips may be measured simultaneously.

  In the above-described embodiment, three sub-drain force lines, sub-source force lines, and sub-gate force lines are provided in the column direction, and three sub-drain sense lines, sub-source sense lines, and sub-gate sense lines are provided in the row direction. Although the case where they are provided is illustrated, it is not determined whether the force lines and the sense lines are provided in the row direction or the column direction. For example, all of the force lines and the sense lines (six lines) may be provided in one of the row direction and the column direction, or the force line and the sense line may be paired to form a drain force, a drain sense, and a gate force. A combination of gate sense, source force, and source sense may be used in two rows and four columns.

  In the semiconductor device of the present invention, as shown in FIG. 8, two test signals TEST0 and TEST1 are used as test signals, and a first test mode (DUT full non-selection) and a second test mode (DUT full select) are used. Two modes are provided. However, the greatest point of the present invention is to apply stress to all DUTs at once by deselecting all evaluation cells. From this point of view, the semiconductor device of the present invention only needs to have a function of deselecting all DUTs in the first test mode as a necessary minimum function. If you want to reduce the number of pins (the number of external terminals), you can reduce the number of pins by switching the test mode to the first test mode (DUT all unselected) and normal evaluation mode. it can.

C11, C21, Cn1, C1m, A0, A1, A2 ... evaluation cells,
DF ... Main drain force line, GF ... Main gate force line, SF ... Main source force line, DF1, DF2, DFm ... Sub drain force line,
GF1, GF2, GFm ... Sub-gate force line,
SF1, SF2, SFm ... sub source force line,
DS ... main drain sense line, GS ... main gate sense line, SS ... main source sense line,
DS1, DS2, DSn ... sub-drain sense line,
GS1, GS2, GSn ... sub-gate sense lines,
SS1, SS2, SSn ... sub-source sense lines,
DVS ... drain stress line, GVS ... gate stress line, SVS ... source stress line, Y1, Y2, Ym ... column selection line, X1, X2, Xn ... row selection line,
PSW1, PSW2, PSWm ... power line switching circuit,
SSW1, SSW2, SSWn ... detection line switching circuit,
DUT, DUT11, DUT1m, DUTn1 ... transistor under test,
DESCRIPTION OF SYMBOLS 10 ... Selection circuit, 10a ... NAND circuit, 10b ... Logic inversion circuit, 20 ... Cell test circuit, DC, DC0, DC1, DC6, DC7, DC13 ... Decode signal output circuit,
ST, ST0, ST1, ST6, ST7, ST13 ... selector circuit, CT ... counter circuit, CTMS ... counter control circuit,
DFc0, DFc1, DFc2, DFc8, DFcs1, DFcs2,... D-type flip-flop,
AY, AYB, AY0, AY6, AY0B ... Y address signal, AX, AXB, AX0, AX6, AX0B ... X address signal,
CA, CAB, CA0, CA2B, CA13... Counter address signal,
SELCONT ... selector control signal, CLK ... clock signal, TEST0, TEST1 ... test signal, ADRCNTM ... counter mode setting signal, ADRLTCH ... counter start address latch signal, ADRINIT ... counter address initialization signal,
T1 ... 1st transistor, T2 ... 2nd transistor, T3 ... 3rd transistor,
T4 ... fourth transistor, T5 ... fifth transistor, T6 ... sixth transistor,
T7 ... seventh transistor, T8 ... eighth transistor, T9 ... ninth transistor,
PDX ... X select predecoder, PDY ... Y select predecoder,
MDX ... X select main decoder, MDY ... Y select main decoder,
500: Gate selection circuit,
DFP: drain power supply terminal, SFP: source power supply terminal, GFP: gate power supply terminal,
DSP ... Drain sense terminal, SSP ... Source sense terminal, GSP ... Gate sense terminal, DVSP ... Drain stress terminal, SVSP ... Source stress terminal, GVSP ... Gate stress terminal

Claims (18)

A semiconductor device for evaluating the characteristics of a transistor under measurement,
n × m evaluation cells arranged in a matrix of n rows and m columns (n and m are positive integers) and having a transistor to be measured;
A row selection line provided for each row and for supplying a row selection signal for selecting the evaluation cell belonging to each row;
A column selection line provided for each column, for supplying a column selection signal for selecting the evaluation cell belonging to each column;
A drain power supply line for applying a stress voltage to the drain terminal for the transistor under measurement;
A source power line for applying a stress voltage to the source terminal for the transistor under measurement;
A gate power supply line for applying a stress voltage to the gate terminal for the transistor under measurement;
A main drain power supply line for supplying a drain voltage for the transistor under measurement;
A main source power line for supplying a source voltage for the transistor under measurement;
A main gate power supply line for supplying a gate voltage for the transistor under measurement;
A sub-drain power supply line that is provided for each row or column and supplies a drain voltage to the transistor under measurement belonging to each row or column;
A sub-source power supply line provided for each row or column and for supplying a source voltage to the transistor under measurement belonging to each row or column;
A sub-gate power supply line provided for each row or each column, for supplying a gate voltage to the transistor under measurement belonging to each row or each column;
Corresponding to the row selection signal belonging to the same row as the sub-drain power supply line or the column selection signal belonging to the column provided corresponding to the sub-drain power supply line, the sub-drain power supply line and the main drain power supply line are connected Or a drain power line switching circuit to be disconnected,
The sub-source power line is connected to the main source power line in response to a row selection signal belonging to the same row as the sub-source power line or a column selection signal belonging to the column. Or a source power line switching circuit to be disconnected,
Corresponding to the row selection signal belonging to the same row as the sub-gate power supply line or the column selection signal belonging to the column provided corresponding to the sub-gate power supply line, the sub-gate power supply line and the main gate power supply line are connected Or a gate power line switching circuit to be disconnected,
A main drain voltage detection line for detecting a drain voltage of the transistor under measurement;
A main source voltage detection line for detecting a source voltage of the transistor under measurement;
A main gate voltage detection line for detecting the gate voltage of the transistor under measurement;
A sub-drain voltage detection line provided for each row or each column and for detecting a drain voltage of the transistor under measurement belonging to each row or each column;
A sub-source voltage detection line provided for each row or each column, for detecting a source voltage of the transistor under measurement belonging to each row or each column;
A sub-gate voltage detection line provided for each row or each column, for detecting a gate voltage of the transistor under measurement belonging to each row or each column;
In response to a row selection signal belonging to the same row as the sub-drain voltage detection line or a column selection signal belonging to a column provided corresponding to the sub-drain voltage detection line, the sub-drain voltage detection line and the main drain voltage A drain detection line switching circuit for connecting or disconnecting the detection lines; and
The sub-source voltage detection line and the main source voltage are provided corresponding to the sub-source voltage detection line and according to a row selection signal belonging to the same row as the sub-source voltage detection line or a column selection signal belonging to the column. A source detection line switching circuit for connecting or disconnecting the detection line; and
The sub-gate voltage detection line and the main gate voltage are provided corresponding to the sub-gate voltage detection line and according to a row selection signal belonging to the same row as the sub-gate voltage detection line or a column selection signal belonging to a column. A gate detection line switching circuit for connecting or disconnecting the detection lines; and
A selection signal supply circuit for supplying a column selection signal to each column selection line and supplying a row selection signal to each row selection line;
Each of the evaluation cells is
One input terminal is connected to the row selection line belonging to its own row, and the other input terminal is connected to the column selection line belonging to its own column and supplied to the connected row selection line. A selection circuit for outputting a selection signal indicating selection / non-selection of its own transistor under measurement in accordance with a row selection signal and a column selection signal supplied to a column selection line;
A first switch for connecting or disconnecting the drain terminal and the drain power supply line according to the selection signal;
A second switch for connecting or disconnecting the source terminal and the source power line in accordance with the selection signal;
A third switch for connecting or disconnecting the gate terminal and the gate power supply line according to the selection signal;
A fourth switch for connecting or disconnecting the sub-drain power supply line belonging to the same row or column as the self and the drain terminal of the transistor under test according to the selection signal;
A fifth switch for connecting or disconnecting the sub-source power line belonging to the same row or column as the self and the source terminal of the transistor under test according to the selection signal;
A sixth switch for connecting or disconnecting the sub-gate power supply line belonging to the same row or column as itself and the gate terminal of the transistor under measurement according to the selection signal;
According to the selection signal, a seventh switch for connecting or disconnecting the sub-drain voltage detection line belonging to the same row or column as the self and the drain terminal of the transistor under measurement;
An eighth switch for connecting or disconnecting the sub-source voltage detection line belonging to the same row or column as itself and the source terminal of the transistor under measurement according to the selection signal;
A ninth switch for connecting or disconnecting the sub-gate voltage detection line belonging to the same row or column as itself and the gate terminal of the transistor under measurement according to the selection signal;
With
The selection signal supply circuit has a selection control signal, a clock signal, a column address signal, a row address signal, and a test signal as inputs,
Depending on the state of the test signal, the mode shifts to either the normal evaluation mode or the first test mode,
In the normal evaluation mode, a first address mode that generates the column selection signal and the row selection signal based on the column address signal and the row address signal according to the state of the selection control signal, and the clock signal Performing a count operation in synchronization, and switching between the second address mode for generating the column selection signal and the row selection signal based on the count result;
In the first test mode, the column selection signal and the row selection signal for deselecting all evaluation cells are generated.
A semiconductor device. Depending on the state of the test signal, the mode shifts to the second test mode,
The semiconductor device according to claim 1, wherein in the second test mode, the column selection signal and the row selection signal for selecting all evaluation cells are generated. In the second address mode,
In synchronization with the first clock signal, the column selection signal and the row selection signal are generated based on the column address signal and the row address signal,
3. The semiconductor device according to claim 1, wherein a count operation is performed in synchronization with the second and subsequent clock signals.   The evaluation cells arranged in a matrix of n rows and m columns are divided into 2 to the power of j by the address of j (j is a positive integer) bit of the column address signal and the row address signal. 4. The semiconductor device according to claim 1, wherein each of the divided arrays has the same channel width and channel length of the transistor under measurement.   5. The semiconductor device according to claim 4, wherein a channel width or a channel length, or a channel width and a channel length of the transistor under measurement are different between the arrays.   The drain power supply line, the source power supply line, the gate power supply line, the main drain power supply line, the main source power supply line, the main gate power supply line, the main drain voltage detection line, the main source voltage detection line, and the main gate A pad electrode to which a voltage detection line, a power supply line, a ground line, and a well voltage line for applying a back bias voltage to the transistor under measurement are connected; a selection control signal; a test signal; a clock signal; a column address signal; 6. The semiconductor device according to claim 1, further comprising a pad electrode to which each of the row address signals is input, wherein the pad electrode is disposed along one side of the chip. A semiconductor device evaluation method for evaluating characteristics of a transistor under measurement, wherein the semiconductor device according to claim 1 is used, and the characteristic evaluation is performed using the first address mode of the normal evaluation mode. If you do
The state of the test signal input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit is set to a state corresponding to the first address mode. A first step of inputting a column address signal and a row address signal representing the position of the evaluation cell to be evaluated to the selection signal supply circuit;
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
A third step of evaluating the characteristics of the transistor under measurement of the evaluation cell selected in the first step by measuring a current flowing through the main drain power source line or the main source power source line;
A method for evaluating a semiconductor device, comprising: A semiconductor device evaluation method for evaluating characteristics of a transistor under measurement, wherein the semiconductor device according to claim 1 is used, and characteristic evaluation is performed using a second address mode of the normal evaluation mode. If you do
The state of the test signal input to the selection signal supply circuit is set to a state corresponding to the normal evaluation mode, and the state of the selection control signal input to the selection signal supply circuit is set to a state corresponding to the second address mode. A first step of:
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
A third step of evaluating the characteristics of the transistor under measurement of the evaluation cell selected in the first step by measuring a current flowing through the main drain power source line or the main source power source line;
A method for evaluating a semiconductor device, comprising: A semiconductor device evaluation method for evaluating characteristics of a transistor under measurement, wherein the semiconductor device according to claim 1 is used and characteristic evaluation is performed using the first test mode. ,
A first step of setting a state of a test signal input to the selection signal supply circuit to a state corresponding to a first test mode;
A desired stress voltage is supplied to the drain power supply line, a desired stress voltage is supplied to the source power supply line, and a desired stress voltage is supplied to the gate power supply line to perform a stress test on all the transistors under measurement. A second step;
A method for evaluating a semiconductor device, comprising: A method for evaluating a semiconductor device for evaluating characteristics of a transistor under measurement, wherein the semiconductor device according to claim 2 is used and characteristic evaluation is performed using the second test mode. ,
A first step of setting a state of a test signal input to the selection signal supply circuit to a state corresponding to a second test mode;
A second step of supplying a desired drain voltage to the main drain power line, supplying a desired source voltage to the main source power line, and supplying a desired gate voltage to the main gate power line;
A third step of evaluating the characteristics of all the transistors under measurement by measuring a current flowing through the main drain power source line or the main source power source line;
A method for evaluating a semiconductor device, comprising: A method for evaluating a semiconductor device for evaluating the characteristics of a transistor under measurement,
A first step of performing a characteristic evaluation of the transistor under measurement using a method for evaluating a semiconductor device according to claim 7 or claim 8 to obtain a first characteristic evaluation result;
A second step of applying stress to the transistor under measurement for a desired time using the semiconductor device evaluation method according to claim 9 subsequent to the first step;
A third step of performing characteristic evaluation of the transistor under measurement by using the method for evaluating a semiconductor device according to claim 7 or 8 following the second step and obtaining a second characteristic evaluation result. ,
Have
A method for evaluating a semiconductor device, wherein stress time dependence of the transistor under measurement is derived based on the first characteristic evaluation result, the second characteristic evaluation result, and the time. A method for evaluating a semiconductor device for evaluating the characteristics of a transistor under measurement,
A first step of performing a characteristic evaluation of the transistor under measurement of the n × m evaluation cells using the semiconductor device evaluation method according to claim 8 to obtain a first characteristic evaluation result;
A second step of selecting one of the semiconductor device evaluation methods according to claim 7 or 8, based on the first characteristic evaluation result;
A third step of performing the characteristic evaluation of the transistors under measurement of some evaluation cells of the n × m evaluation cells by the selected evaluation method;
A method for evaluating a semiconductor device, comprising: A semiconductor device evaluation method according to claim 6, wherein the semiconductor device is arranged in 2 rows and k columns (k is a positive integer) and evaluated using the semiconductor device evaluation method according to claim 7,
In the first step, the test signal, the selection control signal, the column address signal, and the row address signal are simultaneously input to the plurality of arranged semiconductor devices to set the same mode,
In the second step, a desired drain voltage is supplied to the main drain power supply line, and a desired source voltage is supplied to the main source power supply line for each of the plurality of semiconductor devices arranged. Supplying a desired gate voltage to the main gate power line;
In the third step, the evaluation cell selected in the first step is measured by measuring a current flowing through the main drain power source line or the main source power source line of each of the plurality of semiconductor devices arranged. A method for evaluating a semiconductor device, wherein the characteristics of the transistor under measurement are evaluated. A semiconductor device evaluation method, wherein the semiconductor device according to claim 6 is arranged in 2 rows and k columns (k is a positive integer), and the semiconductor device evaluation method according to claim 8 is evaluated.
In the first step, the test signal, the selection control signal, the column address signal, and the row address signal are simultaneously input to the plurality of arranged semiconductor devices to set the same mode,
In the second step, a desired drain voltage is supplied to the main drain power supply line, and a desired source voltage is supplied to the main source power supply line for each of the plurality of semiconductor devices arranged. Supplying a desired gate voltage to the main gate power line;
In the third step, the evaluation cell selected in the first step is measured by measuring a current flowing through the main drain power source line or the main source power source line of each of the plurality of semiconductor devices arranged. A method for evaluating a semiconductor device, wherein the characteristics of the transistor under measurement are evaluated. A semiconductor device evaluation method according to claim 6, wherein the semiconductor device is arranged in 2 rows and k columns (k is a positive integer) and evaluated using the semiconductor device evaluation method according to claim 9,
In the first step, the test signals are simultaneously input to the plurality of semiconductor devices arranged to set the first test mode,
In the second step, the drain, the source voltage, and the gate voltage are supplied to all the transistors under measurement of the plurality of semiconductor devices arranged in plurality. A semiconductor device evaluation method according to claim 6, wherein the semiconductor device is arranged in 2 rows and k columns (k is a positive integer) and evaluated using the semiconductor device evaluation method according to claim 10,
In the first step, the test signal is simultaneously input to the plurality of semiconductor devices arranged to set the second test mode,
In the second step, a desired drain voltage is supplied to the main drain power supply line, and a desired source voltage is supplied to the main source power supply line for each of the plurality of semiconductor devices arranged. Supplying a desired gate voltage to the main gate power line;
In the third step, by measuring the current flowing through the main drain power source line or the main source power source line of each of the plurality of semiconductor devices arranged in the plurality, all the transistors under measurement for each of the semiconductor devices. And evaluating the characteristics of the semiconductor device. A method for evaluating a semiconductor device for evaluating the characteristics of a transistor under measurement,
A first step of performing a characteristic evaluation of the transistor under measurement using the semiconductor device evaluation method according to claim 13 or 14 to obtain a first characteristic evaluation result;
A second step of applying stress to the transistor under measurement for a desired time using the semiconductor device evaluation method according to claim 15 following the first step.
A third step of performing a characteristic evaluation of the transistor under measurement and obtaining a second characteristic evaluation result by using the semiconductor device evaluation method according to claim 13 or 14 following the second step. ,
Have
A method for evaluating a semiconductor device, wherein stress time dependence of the transistor under measurement is derived based on the first characteristic evaluation result, the second characteristic evaluation result, and the time. A method for evaluating a semiconductor device for evaluating the characteristics of a transistor under measurement,
A first step of performing a characteristic evaluation of a transistor under measurement of the n × m evaluation cells using the semiconductor device evaluation method according to claim 14 to obtain a first characteristic evaluation result;
A second step of selecting one of the semiconductor device evaluation methods according to claim 13 or 14, based on the first characteristic evaluation result;
A third step of performing the characteristic evaluation of the transistors under measurement of some evaluation cells of the n × m evaluation cells by the selected evaluation method;
A method for evaluating a semiconductor device, comprising:

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