JP2011027534A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for measuring the characteristics of respective transistors, while shortening time required to evaluate the characteristics of the transistors constituting a large-scale semiconductor device. <P>SOLUTION: The semiconductor device includes an evaluation cell array comprising the plurality of transistors for comparing magnitude relation between an input voltage and a reference voltage, and having evaluation cells disposed in m rows and n columns, with each cell being equipped with paired transistors for outputting a comparison result from two output terminals; an evaluation cell selector for selecting one evaluation cell from the cell array to input an output of the evaluation cell into an amplifying circuit; the amplifying circuit for amplifying a potential difference between two output terminals of the evaluation cell selected by the cell selector; and a plurality of external terminals connected to the drain, the source and the gate, respectively, of a transistor possessed by the evaluation cell selected by the cell selector. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of evaluating characteristics of a large number of semiconductor elements in a large-scale DMA-TEG.

  In the development of semiconductor microprocesses (hereinafter referred to as processes), TEG (Test Element Group), which evaluates microelements with various dimensions, is used to evaluate and analyze the characteristics of microelements (transistors, resistor elements, etc.). Created on a wafer and conducts evaluation analysis of the created microelements. We are developing microelements that can withstand mass production by setting the conditions for semiconductor microprocesses based on the results of evaluation analysis.

In process development, the process conditions and transistor structure optimal for manufacturing were set by evaluating and analyzing the characteristics of the individual transistors configured in the TEG. As the size of the semiconductor wafer becomes smaller, variation in characteristics among a plurality of transistors included in the semiconductor wafer cannot be ignored.
Further, with the progress of miniaturization, the stress applied to the transistor is relatively increased due to the electric field and the structure generated around the transistor, and the phenomenon that the characteristics of the transistor change cannot be ignored.

From such a situation, for example, in a fine process with a manufacturing level of 45 nm, the characteristics of both transistors vary even if they are adjacent transistors. Therefore, a small signal such as SRAM (Static Random Access Memory) is used as a pair transistor (adjacent It is expected that the detection circuit and the amplification circuit that detect with two transistors) have a reduced operating margin or become inoperable.
In this case, sufficient data for developing a fine process cannot be obtained only by evaluation analysis of individual transistors. Therefore, the characteristics of a large number of transistors are evaluated, statistically processed and analyzed, and the characteristics according to the transistor configuration. A large-scale TEG that can separate and analyze the difference and the characteristic difference due to manufacturing variation is required.

  As a TEG for performing large-scale element evaluation, there is a DMA (Device Matrix Array) -TEG in which a plurality of transistors are arranged in a matrix and the characteristics of the transistors can be evaluated (Non-patent Document 1). When the DMA-TEG is configured on a large scale and the number of transistors to be measured increases, there is a problem that a huge amount of time is required for measurement.

  Therefore, the inventor does not directly measure the threshold voltage of a transistor by using a pair of paired transistors as the measurement target transistor according to what is described in Patent Document 1, but using an amplifier. By measuring the difference between the threshold voltages of the transistors, variations in transistor characteristics are measured and analyzed. The transistor described in Patent Document 1 measures a transistor in a shorter time than when measuring individual transistors.

JP 2008-1171920 A

Yoshiyuki Shimizu, Mitsuo Nakamura, Toshimasa Matsuoka, and Kenji Taniguchi, "Test structure for precise statistical characteristics measurement of MOSFETs", IEEE 2002 Int. Conference on Microelectronic Test Structure (ICMTS 2002), pp. 49-54, April 2002.

  However, in the method shown in Patent Document 1, although the evaluation analysis time of a large-scale DMA-TEG can be shortened, which transistor is judged to be defective due to the difference in threshold voltage in the pair transistor configuration. It is difficult to measure whether the threshold voltage is such a characteristic.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to increase the time required for evaluating the characteristics of transistors formed in a semiconductor device such as a large-scale DMA-TEG without increasing the time required for the individual transistors. An object of the present invention is to provide a semiconductor device capable of measuring characteristics.

  (1) In order to solve the above problem, the present invention is a semiconductor device for evaluating transistor characteristics, and includes a plurality of transistors for comparing the magnitude relationship between an input voltage and a reference voltage, and two output terminals. An evaluation cell array having m rows and n columns (m and n are positive integers) in which evaluation cells including comparators that output comparison results are arranged in a matrix in the row and column directions, and for each column of the evaluation cell array A first and second data line belonging to the column; an amplifier circuit for amplifying and outputting a potential difference between the first and second data lines; and provided for each column of the evaluation cell array. A first switch and a second switch for switching connection between the first and second data lines and the amplifier circuit; and the evaluation cell includes one of the two output terminals of the comparator and the first data. Switch connection to line And a fourth switch for switching the connection between the other of the two output terminals of the comparator and the second data line, and the semiconductor device is configured to turn on and off the first and second switches. A column selection signal for switching between and a row selection signal for switching on and off the third and fourth switches to select any one of the evaluation cells included in the evaluation cell array, An evaluation cell selection unit that inputs the output of the selected evaluation cell to the amplifier circuit, and a plurality of transistors connected to the sources, drains, and gates of the plurality of transistors included in the evaluation cell selected by the evaluation cell selection unit An external terminal of the semiconductor device.

  (2) Further, the present invention is the above-described invention, wherein the comparator has a first transistor in which the input voltage is applied to a gate and a drain is connected to one of the two output terminals; A second transistor connected to the source of the first transistor, the reference voltage applied to the gate, and the drain connected to the other of the two output terminals. The sources of the first and second transistors It is connected to a source.

  (3) Further, according to the present invention, in the invention described above, the comparator includes a third transistor having a drain and a gate connected to the drain of the first transistor, and a gate connected to the gate of the third transistor. A fourth transistor having a source connected to the source of the third transistor and a drain connected to the drain of the second transistor.

  (4) In the invention described above, the present invention provides a first and second drain force line provided for each column of the evaluation cell array and commonly connected to the evaluation cells belonging to the column of the evaluation cell array, A source force line; first and second drain sense lines; a source sense line; an input signal line commonly connected to a gate of the first transistor included in the evaluation cell; and the second transistor included in the evaluation cell. A reference signal line commonly connected to the gates of the first and second gates, and the evaluation cell is configured to provide a drain of the first transistor according to a measurement switching signal for switching between measurement of the comparator and measurement of a transistor included in the comparator. And a fifth switch for switching the connection with the first drain force line, and the drain of the first transistor by the measurement switching signal. A sixth switch for switching the connection with the first drain sense line, a seventh switch for switching the connection between the drain of the second transistor and the second drain force line by the measurement switching signal, and the measurement switching. An eighth switch that switches connection between the drain of the second transistor and the second drain sense line by a signal, and a source of the first and second transistors and the source force line by the measurement switching signal. A ninth switch for switching connection; and a tenth switch for switching connection between the source of the first and second transistors and the source sense line by the measurement switching signal, and the first and second drain force lines. The source force line, the first and second drain sense lines, the source sense line, the input Signal lines, each of said reference signal line, and being connected to different ones of the plurality of external terminals.

  (5) In the present invention described above, the first and second drain force lines, the source force line, the first and second drain sense lines, and the source sense that are commonly connected to the evaluation cell. An input signal line commonly connected to a gate of the first transistor included in the evaluation cell, and a reference signal line commonly connected to a gate of the second transistor included in the evaluation cell, The evaluation cell includes a fifth switch that switches connection between the drain of the first transistor and the first drain force line, and a sixth switch that switches connection between the drain of the first transistor and the first drain sense line. A seventh switch for switching connection between the drain of the second transistor and the second drain force line, and the second transistor An eighth switch that switches connection between the drain and the second drain sense line; a ninth switch that switches connection between the source of the first and second transistors and the source force line; and the first and second switches. A tenth switch for switching a connection between the source of the transistor and the source sense line; and detecting that the own cell is selected according to the row selection signal and the column selection signal; A decoder circuit which turns off the fifth to tenth switches and turns on the fifth to tenth switches when measuring the transistors included in the comparator of its own cell. And

  (6) In the invention described above, the present invention provides first and second drain force lines provided for each column of the evaluation cell array and commonly connected to the evaluation cells belonging to the column of the evaluation cell array, A source force line, a gate force line, first and second drain sense lines, a source sense line, a gate sense line, and an input signal line commonly connected to the gate of the first transistor included in the evaluation cell; A reference signal line commonly connected to a gate of the second transistor included in the evaluation cell, wherein the evaluation cell switches between measurement of the comparator and measurement of the transistor included in the comparator. A fifth switch for switching connection between the drain of the first transistor and the first drain force line by a switching signal; and the measurement switching signal. Accordingly, the sixth switch for switching the connection between the drain of the first transistor and the drain sense line, and the second switch for switching the connection between the drain of the second transistor and the second drain force line by the measurement switching signal. 7 switches, an eighth switch for switching connection between the drain of the second transistor and the second drain sense line by the measurement switching signal, and sources of the first and second transistors by the measurement switching signal. A ninth switch for switching the connection with the source force line, a tenth switch for switching the connection between the sources of the first and second transistors and the source sense line by the measurement switching signal, and the measurement switching signal. To connect the gates of the third and fourth transistors to the gate force line. An eleventh switch for switching between the gates of the third and fourth transistors and the gate sense line by the measurement switching signal, and the third and fourth by the measurement switching signal. A thirteenth switch for switching a connection between the gate of the transistor and the drain of the first transistor; when the fifth to twelfth switches are on, the thirteenth switch is off; When the switch is off, the thirteenth switch is on and the first and second drain force lines, the source force line, the gate force line, the first and second drain sense lines, the source sense line, Each of the gate sense line, the input signal line, and the reference signal line is connected to the different external terminals. And features.

  (7) Further, according to the present invention, in the above-described invention, the first and second drain force lines, the source force line, the gate force line, and the first and second drain senses commonly connected to the evaluation cell. A line, a source sense line, a gate sense line, an input signal line commonly connected to the gate of the first transistor included in the evaluation cell, and a gate connected to the gate of the second transistor included in the evaluation cell. A reference signal line, and the evaluation cell includes a fifth switch that switches connection between the drain of the first transistor and the first drain force line, the drain of the first transistor, and the drain sense line. A sixth switch for switching the connection between the drain, the drain of the second transistor, and the second switch for switching the connection with the second drain force line. An eighth switch for switching connection between the switch, the drain of the second transistor, and the second drain sense line; and a ninth switch for switching connection between the source of the first and second transistors and the source force line. A tenth switch for switching connection between the sources of the first and second transistors and the source sense line, and an eleventh switch for switching connection between the gates of the third and fourth transistors and the gate force line. A twelfth switch for switching connection between the gates of the third and fourth transistors and the gate sense line, and a second switch for switching connection between the gates of the third and fourth transistors and the drain of the third transistor. 13 that the own cell is selected according to the row selection signal and the column selection signal. And measuring the comparator of the own cell, turning off the fifth to twelfth switches and turning on the thirteenth switch, and measuring the transistors included in the comparator of the own cell, And a decoder circuit that turns on the fifth to twelfth switches and turns off the thirteenth switch.

  (8) Further, the present invention is characterized in that, in the above-described invention, the output of the amplifier circuit is the reference voltage.

  (9) Moreover, the present invention provides the first and second drain force lines provided for each column of the evaluation cell array and commonly connected to the evaluation cells belonging to the column of the evaluation cell array, in the invention described above. A source force line; first and second drain sense lines; a source sense line; and an input signal line commonly connected to a gate of the first transistor included in the evaluation cell. A fifth switch for switching a connection between the drain of the first transistor and the first drain force line by a measurement switching signal for switching between the measurement of the comparator and the measurement of the transistor included in the comparator; and the measurement switching A sixth switch for switching connection between the drain of the first transistor and the first drain sense line according to the signal; and the measurement switching signal. The seventh switch for switching the connection between the drain of the second transistor and the second drain force line, and the connection between the drain of the second transistor and the second drain sense line by the measurement switching signal. An eighth switch for switching, a ninth switch for switching connection between the source of the first and second transistors and the source force line by the measurement switching signal, and the first and second transistors by the measurement switching signal. And a tenth switch for switching the connection between the source sense line and the gate of the second transistor of the evaluation cell is applied with the output of the amplifier circuit, and the first and second drain forces are applied. Line, source force line, first and second drain sense lines, source sense line, front Each input signal line, and being connected to different ones of the plurality of external terminals.

  (10) The present invention also provides an evaluation cell having a plurality of transistors for comparing the magnitude relationship between the input voltage and the reference voltage, and having a comparator for outputting a comparison result from one output terminal in the row and column directions. An evaluation cell array of m rows and n columns (m and n are positive integers) arranged in a matrix, first and second data lines belonging to each column of the evaluation cell array, An amplifier circuit that amplifies and outputs the potential difference between the first and second data lines, and a first switch that is provided for each column of the evaluation cell array and switches the connection between the first data line belonging to the column and the amplifier circuit. And the evaluation cell includes a second switch that switches connection between the one output terminal of the comparator and the second data line, and the semiconductor device is configured to turn on and off the first switch. Switch column An evaluation signal and a row selection signal for switching on and off of the second switch to select any one evaluation cell from among the evaluation cells included in the evaluation cell array. An evaluation cell selection unit that inputs an output to the amplifier circuit, and a plurality of transistors that measure or apply voltages to the sources, drains, and gates of the plurality of transistors included in the evaluation cell selected by the evaluation cell selection unit. And an external terminal, wherein the input voltage is applied via the first data line, and the reference voltage is a comparison result output from the comparator included in the evaluation cell.

  (11) In the present invention described above, the comparator includes a first transistor having a gate connected to the first data line, a source connected to a source of the first transistor, and a gate. Is connected to the second data line, a drain is connected to the one output terminal, a third transistor is connected to the drain of the first transistor, and a drain is connected to the drain. A fourth transistor having a source connected to a drain of the second transistor and a source connected to a source of the third transistor, wherein the sources of the first and second transistors are connected to a current source. And

  (12) The present invention provides the first and second drain force lines provided for each column of the evaluation cell array and commonly connected to the evaluation cells belonging to the column of the evaluation cell array, in the invention described above, A source force line; a gate force line; first and second drain sense lines; a source sense line; and a gate sense line. The evaluation cell includes a measurement of the comparator; A third switch for switching connection between the drain of the first transistor and the first drain force line by a measurement switching signal for switching between measurement of the transistors having; and a drain for the first transistor by the measurement switching signal; A fourth switch for switching connection with the first drain sense line; and a drain of the second transistor by the measurement switching signal. A fifth switch for switching the connection with the second drain force line, a sixth switch for switching the connection between the drain of the second transistor and the second drain sense line according to the measurement switching signal, and the measurement A switch for switching connection between the source of the first and second transistors and the source force line by a switching signal; a source of the first and second transistors by the measurement switching signal; and the source sense line. An eighth switch for switching the connection, a ninth switch for switching the connection between the gates of the third and fourth transistors and the gate force line by the measurement switching signal, and the third and the fourth switching by the measurement switching signal. A tenth switch for switching the connection between the gate of the fourth transistor and the gate sense line; When the fifth switch to the tenth switch are turned on, the switch comprising: an eleventh switch for switching the connection between the gates of the third and fourth transistors connected to each other and the drain of the first transistor by a constant switching signal; When the eleventh switch is off and the fifth to tenth switches are off, the eleventh switch is on, and the first and second drain force lines, the source force lines, and the gate force lines The first and second drain sense lines, the source sense line, the gate sense line, and the first data line are connected to different external terminals.

  (13) In the present invention, the current source is provided for each column of the evaluation cell array, and the sources of the first and second transistors of the evaluation cell belonging to the column of the evaluation cell array Are commonly connected to each other.

  (14) In the invention described in the above, the current source is provided for each of the evaluation cells, and is commonly connected to the sources of the first and second transistors of the evaluation cell. To do.

According to the present invention, in a large-scale DMA-TEG, by measuring the characteristics of a pair transistor or an amplifier, a defective transistor is detected without evaluating the characteristics of each transistor. Individual measurements.
Thereby, in a large-scale semiconductor device such as a DAM-TEG, it is possible to reduce the time required for detecting a defective transistor and measuring the defective transistor, and to improve the measurement accuracy of the characteristic value of the defective transistor.

It is a figure which shows the connection in the case of measuring the input offset voltage Voff of amplifier Amp used as a measuring object. It is a circuit diagram which shows the structural example of amplifier Amp used as a measuring object. 1 is a schematic block diagram illustrating a configuration of a semiconductor device 100 according to a first embodiment. FIG. 3 is a circuit diagram showing a configuration of an amplifier circuit 130 and an evaluation cell DUTmn in the same embodiment. It is a circuit diagram which shows the structure of switch SW1F-SW3F in the same embodiment, SW1S-SW3S. It is a schematic block diagram which shows the structure of the semiconductor device 200 in 2nd Embodiment. It is a circuit diagram which shows the structure of the amplifier circuit 130 and the evaluation cell DUTamn in the embodiment. It is a schematic block diagram which shows the structure of the semiconductor device 300 in 3rd Embodiment. FIG. 3 is a circuit diagram showing a configuration of an amplifier circuit 130 and an evaluation cell DUTmn in the same embodiment. It is a schematic block diagram which shows the structure of the semiconductor device 400 in 4th Embodiment. It is a circuit diagram which shows the structure of the evaluation cell DUTbmn in the same embodiment. It is a schematic block diagram which shows the structure of the semiconductor device 500 in 5th Embodiment. It is a circuit diagram which shows the structure of the evaluation cell DUTcmn in the same embodiment. It is a schematic block diagram which shows the structure of the semiconductor device 600 in 6th Embodiment. It is a circuit diagram which shows the structure of the evaluation cell DUTdmn of the same embodiment.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a connection when measuring an input offset voltage Voff of an amplifier Amp to be measured. As shown, the output of the amplifier is connected to the inverting input (-). Thereby, the input offset voltage Voff of the amplifier Amp is obtained by the difference (Vout−Vin) between the output voltage Vout and the input voltage Vin input to the non-inverting input (+).
Since the basic characteristics of the amplifier are determined by the input offset voltage Voff, it is important how the input offset voltage Voff can be reduced in process development. Further, the input offset Voff is affected by the characteristic difference (variation of threshold voltage) of the pair transistors constituting the amplifier. Therefore, by using DMA-TEG in process development, the characteristic difference of the pair transistors and the threshold values of the pair transistors are obtained. Measure the voltage.

FIG. 2 is a circuit diagram illustrating a configuration example of the amplifier Amp to be measured. FIG. 2A is a circuit diagram showing a configuration example of an amplifier Amp that uses an N-channel MOS transistor as an input transistor and applies an input signal to the gate of the input transistor.
The amplifier Amp includes an N-channel MOS transistor Tn1 (first transistor) and a transistor Tn2 (second transistor) forming a pair transistor, and a P-channel MOS transistor Tp3 (third transistor) and a transistor Tp4 (fourth transistor) forming a pair transistor. Transistor) and an N-channel MOS transistor Tn5 (fifth transistor) as a current source for controlling the current flowing through the transistors Tn1-2, Tp3, and Tp4.

The source of the transistor Tn1 is connected to the drain of the transistor Tn5, and the input voltage Vin + is applied to the gate. The source of the transistor Tn2 is connected to the drain of the transistor Tn5, and the reference voltage Vin− is applied to the gate. The transistor Tp3 has a source connected to a power supply terminal that supplies the power supply potential Vdd, a gate connected to the gate of the transistor Tp4 and the drain of the transistor, and a drain connected to the drain of the transistor Tn1.
The transistor Tp4 has a source connected to the power supply terminal, a gate connected to the gate of the transistor Tp3, and a drain connected to the drain of the transistor Tn2. The transistors Tp3 and Tp4 form a current mirror circuit. The transistor Tn5 has a drain connected to the sources of the transistors Tn1 and Tn2, a source grounded, and a bias voltage Vbias applied to the gate.

A connection point connecting the drain of the transistor Tn2 and the drain of the transistor Tp4 is connected to the output terminal Out, and the voltage at the connection point becomes the output voltage Vout.
In the amplifier configured as described above, variations in threshold voltages of the transistors Tn1 and Tn2 forming a pair transistor and variations in threshold voltages of the transistors Tp3 and Tp4 forming a pair transistor affect the input offset voltage Voff of the amplifier. .

  FIG. 2B is a circuit diagram showing a configuration example of an amplifier Amp that uses a P-channel MOS transistor as an input transistor and applies an input signal to the gate of the transistor. The amplifier Amp is a P-channel MOS transistor Tn11, Tn12 that forms a pair transistor, N-channel MOS transistors Tp13, Tp14 that form a pair transistor, and a current source that controls a current flowing through the transistors Tn11-12, Tp13-14. A P-channel MOS transistor Tp15.

The transistor Tn11 has a source grounded and a gate connected to the drain of the transistor Tn11 and the gate of the transistor Tn12. The source of the transistor Tn12 is grounded, and the gate is connected to the gate of the transistor Tn11. The transistors Tn11 and Tn12 form a current mirror circuit.
The transistor Tp13 has a source connected to the drain of the transistor Tp15, a drain connected to the drain of the transistor Tn11, and an input voltage Vin + applied to the gate. The transistor Tp14 has a source connected to the drain of the transistor Tp15, a drain connected to the drain of the transistor Tn12, and a reference voltage Vin− applied to the gate. The transistor Tp15 has a source connected to the power supply terminal, a drain connected to the sources of the transistors Tp13 and Tp14, and a bias voltage Vbias applied to the gate.

A connection point connecting the drain of the transistor Tn12 and the drain of the transistor Tp14 is connected to the output terminal Out, and the voltage at the connection point becomes the output voltage Vout.
In the amplifier configured as described above, variations in threshold voltages of the transistors Tn11 and Tn12 forming a pair transistor and variations in threshold voltages of the transistors Tp13 and Tp14 forming a pair transistor affect the input offset voltage Voff of the amplifier. .

  In the following, a semiconductor device capable of measuring the characteristic difference of the pair transistors constituting the amplifier Amp configured as described above and the threshold voltage of the transistors in the large-scale DMA-TEG will be described.

<First Embodiment>
FIG. 3 is a schematic block diagram illustrating the configuration of the semiconductor device 100 according to the first embodiment. As shown in the figure, the semiconductor device 100 has m × n evaluation cells DUT11 to DUTmn arranged in a matrix of m rows and n columns (n and m are positive integers), and is provided in the evaluation cell. This is a DMA-TEG that evaluates the difference in characteristics of the paired transistors (comparators).
The semiconductor device 100 includes an evaluation cell array 110, an evaluation cell selection unit 120, an amplifier circuit 130, a measurement switching signal input line VthM, data lines DR and DL, an input signal line Vin, and a reference signal line Vref. ing.

The semiconductor device 100 includes source sense lines SS1 to SSn, source force lines SF1 to SFn, drain sense lines DSL1 to DSLn, DSR1 to DSRn, drain force lines DFL1 to DFLn, which are provided for each column of the evaluation cell array 110. DFR1 to DFRn, column selection signal lines COL1 to COLn, column selection switches CG1L to CGnL, CG1R to CGnR, and data lines D1L to DnL, D1R to DnR are provided.
In addition, the semiconductor device 100 includes measurement switching signal output lines VthM1 to VthMm, VthMB1 to VthMBm, and row selection signal lines WL1 to WLm provided for each row of the evaluation cell array 110.
Source sense lines SS1 to SSn, source force lines SF1 to SFn, drain sense lines DSL1 to DSLn, DSR1 to DSRn, drain force lines DFL1 to DFLn, DFR1 to DFRn, measurement switching signal input line VthM, input signal line Vin, Each of the reference signal lines Vref is connected to a different external terminal.

The evaluation cells DUT11 to DUTm1 constituting the first column of the evaluation cell array 110 have data lines D1L and D1R, a source sense line SS1, a source force line SF1, a drain sense line DSL1, DSR1, The drain force lines DFL1 and DFR1 are connected.
Similarly to the evaluation cells DUT11 to DUTm1 constituting the first column, the evaluation cells constituting each of the second column to the nth column of the evaluation cell array 110 are provided corresponding to the data lines D2L and D2R. , ..., DnL, DnR, source sense lines SS2, ..., SSn, source force lines SF2, ..., SFn, drain sense lines DSL2, DSR2, ..., DSLn, DSRn, and drain force lines DFL2, DFR2, ..., DFLn , DFRn. The evaluation cells DUT11 to DUTmn are connected to the input signal line Vin and the reference signal line Vref.

  The evaluation cells DUT11 to DUT1n constituting the first row of the evaluation cell array 110 are connected to a row selection signal line WL1 and measurement switching signal output lines VthM1 and VthMB1 provided corresponding to the row. Similarly to the evaluation cells DUT11 to DUT1n constituting the first row, the evaluation cells constituting each of the second to mth rows of the evaluation cell array 110 are also provided corresponding to the row selection signal lines WL2 to WLm. , And measurement switching signal output lines VthM2, VthMB2,..., VthMm, VthMBm.

  The evaluation cell selection unit 120 includes a column decoder 121 and row decoders 122-1 to 122-m. The column decoder 121 is connected to the column selection signal lines COL1 to COLn, decodes the input column address, and sets any one of the column selection signal lines COL1 to COLn to the H (High) level that is the power supply potential Vdd. The other column selection signal lines are set to the L (Low) level which is the ground potential.

When the column selection signal line COL1 is at the H level, the column selection switch CG1L energizes the data line D1L and the data line DL corresponding to the switch, and when the column selection signal line COL1 is at the L level, The data line DL is turned off. Similarly to the column selection switch CG1L, the column selection switches CG2L to CGnL energize the data lines D2L to DnL and the data line DL corresponding to the switch when the column selection signal lines COL2 to COLn are at the H level. When the column selection signal lines COL2 to COLn are at the L level, the data lines D2L to DnL and the data lines DL corresponding to the switch are turned off.
Similarly to the column selection switches CG1L to CGnL, the column selection switches CG1R to CGnR energize the data lines D1R to DnR and the data line DR corresponding to the switch when the column selection signal lines COL1 to COLn are at the H level. When the column selection signal line COL1 is at the L level, the data lines D1R to DnR and the data line DL are turned off.

  Row decoders 122-1 to 122-m are provided corresponding to each row of evaluation cell array 110. The row decoder 122-1 is connected to the measurement switching signal input line VthM, the measurement switching signal output lines VthM 1 and VthMB 1 corresponding to the row of the evaluation cell array 110 corresponding to the row decoder, and the row selection signal line WL 1. ing. Similarly to the row decoder 122-1, the row decoders 122-2 to 122-m each have a measurement switching signal input line VthM and a measurement switching signal output line VthM2 corresponding to the row of the evaluation cell array 110 corresponding to the row decoder. To VthMm, VthMB2 to VthMBm, and row selection signal lines WL2 to WLm.

The row decoder 122-1 decodes the input row address to determine whether or not the first row of the corresponding evaluation cell array 110 is selected. If selected, the connected row selection signal line is selected. WL1 is set to the H level, and the measurement switching signal input from the measurement switching signal input line VthM and the inverted signal are output to the measurement switching signal output lines VthM1 and VthMB1, respectively.
Similarly to the row decoder 122-1, the row decoders 122-2 to 122m decode the input row address to determine whether or not the corresponding row of the evaluation cell array 110 has been selected. In this case, the connected row selection signal lines WL2 to n are set to the H level, and the measurement switching signal input from the measurement switching signal input line VthM and the inverted signal of the measurement switching signal output lines VthM2 to VthMm, Output to VthMB2 to VthMBm.
The row decoders 122-1 to 122-m set the connected row selection signal lines WL1 to WLm to the L level when the row of the evaluation cell array 110 corresponding to the decoder is not selected.

With the above-described configuration, the evaluation cell selection unit 120 sets any one of the column selection signal lines COL1 to COLn to the H level and the row selection signal lines WL1 to WLn according to the input column address and row address. Any one of the evaluation cells DUT11 to DUTmn included in the evaluation cell array 110 is selected by setting any one of these to H level.
The amplifier circuit 130 is connected to the data lines DL and DR, amplifies the potential difference between the data lines DL and DR, and outputs it to the output terminal OUT.

Hereinafter, the configuration of the evaluation cells DUT11 to DUTmn will be described with reference to FIGS.
FIG. 4 is a circuit diagram showing a configuration of the amplifier circuit 130 and the evaluation cell DUTmn in the same embodiment. Since the evaluation cells DUT11 to DUTmn have the same configuration, the configuration of the evaluation cell DUTmn will be described as a representative. Moreover, evaluation cells DUT1n to DUT (m−1) n (not shown) are arranged in the column in the same manner as DUTmn.
Here, a case will be described in which the evaluation target by DMA-TEG is the transistors Tn1 and Tn2 forming the pair transistors of the amplifier configured by the N-channel MOS transistor shown in FIG.

  As shown in FIG. 4, the amplifier circuit 130 includes transistors Tp3 and Tp4. The transistor Tp3 has a source connected to the power supply terminal that supplies the power supply potential Vdd, and a drain connected to the gate of the transistor, the gate of the transistor Tp4, and the data line DnL via the column selection switch CGnL. The transistor Tp4 has a source connected to the power supply terminal, a gate connected to the gate of the transistor Tp3, and a drain connected to the data line DnR via the column selection switch CGnR.

The evaluation cell DUTmn includes transistors Tn1, Tn2, and Tn5 and switches SW1F to SW3F, SW1S to SW3S, SW4, and SW5.
The transistor Tn1 has a drain connected to the switches SW1F, SW1S, SW4 via the connection point N1, a source connected to the switches SW3F, SW3S, and the drain of the transistor Tn5 via the connection point N3, and a gate connected to the input signal line. Connected to Vin. The transistor Tn2 has a drain connected to the switches SW2F, SW2S, SW5 via the connection point N2, a source connected to the switches SW3F, SW3S, and the drain of the transistor Tn5 via the connection point N3, and a gate connected to the reference signal line. Connected to Vref.
The drain of the transistor Tn5 is connected to the connection point N3 and the source of the transistor Tn2, the source is grounded, and the bias voltage Vbias is applied to the gate.

The switch SW1F is connected to the connection point N1 and the drain force line DFLn, and energization and non-energization between the connection point N1 and the drain force line DFLn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch. The switch SW1S is connected to the connection point N1 and the drain sense line DSLn, and energization and non-energization between the connection point N1 and the drain sense line DSLn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch.
The switch SW2F is connected to the connection point N2 and the drain force line DFRn, and energization and non-energization between the connection point N2 and the drain force line DFRn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch. The switch SW2S is connected to the connection point N2 and the drain sense line DSRn, and energization and non-energization between the connection point N2 and the drain sense line DSRn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch.

  The switch SW3F is connected to the connection point N3 and the source force line SFn, and energization and non-energization between the connection point N3 and the source force line SFn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch. The switch SW3S is connected to the connection point N3 and the source sense line SSn, and energization and non-energization between the connection point N3 and the source sense line SSn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch.

  FIG. 5 is a circuit diagram showing a configuration of the switches SW1F to SW3F and SW1S to SW3S in the same embodiment. As shown in the figure, this is a transfer gate using a P-channel MOS transistor and an N-channel MOS transistor. The measurement switching signal output line VthMBm is connected to the gate of the P-channel MOS transistor, and the measurement switching signal output line VthMm is connected to the gate of the N-channel MOS transistor. Thereby, between the drain and the source of each transistor, when the measurement switching signal output line VthMm is at the H level and the measurement switching signal output line VthMBm is at the L level, the transistors are energized and the measurement switching signal is output. When the line VthMm is at the L level and the measurement switching signal output line VthMBm is at the H level, the power is turned off.

Returning to FIG. 4, the switch SW4 is connected to the connection point N1 and the data line DnL. When the row selection signal input from the row selection signal line WLm is at the H level, the connection point N1 and the data line DnL are energized. When the row selection signal is at the L level, the connection point N1 and the data line DnL are turned off.
The switch SW5 is connected to the connection point N2 and the data line DnR. When the row selection signal input from the row selection signal line WLm is at the H level, the connection point N2 and the data line DnR are energized, and the row selection signal Is at the L level, the connection point N2 and the data line DnR are turned off.

  With the above-described configuration, the evaluation cell selected by the evaluation cell selection unit 120 has the drain of the transistor Tn1 connected to the data line DnL and the drain of the transistor Tn2 connected to the data line DnR by the row selection signal line WLm. The Further, the selected evaluation cell is connected to the data line DnL, DnR corresponding to the evaluation cell and the amplifier circuit 130 via the column selection signal line COLn, and the transistors Tn1, Tn2, Tp3 via the data lines DnL, DnR. , Tp4, Tn5 constitute the amplifier Amp shown in FIG.

  When an L level signal is input from the external terminal to the measurement switching signal input line VthM, the row decoders 122-1 to 122-m set the measurement switching signal output lines VthM1 to VthMm to the L level, and the measurement switching signal output line VthMB1. Set VthMBm to H level. This state is referred to as an amplifier evaluation mode, and the switches SW1F to SW3F and SW1S to SW3S are in a non-energized state. At this time, the evaluation cell selected by the row address and the column address outputs the output voltage Vout from the amplifier circuit 130 according to the voltage applied from the input signal line Vin and the reference signal line Vref.

  When an H level signal is input from the external terminal to the measurement switching signal input line VthM, the row decoders 122-1 to 122-m set the measurement switching signal output lines VthM1 to VthMm to the H level and output the measurement switching signal. Lines VthMB1 to VthMBm are set to L level. This state is called a transistor evaluation mode, and the switches SW1F to SW3F and SW1S to SW3S are energized. At this time, it is possible to measure characteristic values such as threshold voltages of the transistors Tn1 and Tn2 included in the evaluation cell selected by the row address and the column address.

  For example, when measuring a threshold voltage for flowing a current of 100 n [A] of the transistor Tn1 included in the evaluation cell DUTmn, a voltage of 1.0 [V] is applied to the drain force line DFLn, and 0 [V] is applied to the source force line SFn. ] Is applied, and the voltage applied to the gate via the input signal line Vin is changed to measure the threshold voltage at which a current of 100 n [A] flows through the transistor Tn1. Further, the static characteristics and the VG-ID characteristics of the transistor Tn1 are evaluated by measuring while changing the drain voltage and the gate voltage.

  Furthermore, since the semiconductor device 100 of this embodiment includes the drain sense lines DSLn and DSRn and the source sense line SSn, a voltage is applied to the drain and source of the transistors Tn1 and Tn2 to be measured, and the drain and source The voltage applied to the transistor Tn1 can be measured, and by measuring the characteristic values of the transistors Tn1 and Tn2 as follows, the accuracy of measuring the characteristic values can be improved.

For example, when measuring the transistor Tn1 included in the evaluation cell DUTmn, even if a voltage of 1.0 [V] is applied to the external terminal connected to the drain force line DFLn, a current flows through the drain force line DFLn, Due to a voltage drop due to resistance or the like, a voltage of 0.95 [V] is applied to the drain of the transistor Tn1.
In this case, the voltage applied to the transistor Tn1 via the drain sense line DSLn is measured, the voltage of the external terminal DFLn is adjusted to 1.05 [V], and 1.0 [V] is applied to the drain of the transistor Tn1. The accuracy of measurement can be improved by applying the above voltage. As for the voltage applied to the source of the transistor Tn1, as with the drain, the voltage applied to the source of the transistor Tn1 is measured via the source sense line SSn, and a desired voltage is applied to the source of the transistor Tn1. can do.

As described above, in the semiconductor device 100, the characteristic difference between the paired transistors Tn1 and Tn2 constituting the amplifier Amp can be measured in the amplifier evaluation mode, and the threshold values of the paired transistors Tn1 and Tn2 constituting the amplifier Amp in the transistor evaluation mode. You can measure voltage. Thereby, in the semiconductor device 100, by measuring the characteristics of the amplifier Amp in the amplifier evaluation mode, it is possible to shorten the time required for the measurement of the evaluation cell compared to the case where the transistors included in the evaluation cell are individually measured. . Further, for the amplifier Amp determined to be defective based on the measurement result, the threshold voltage of the paired transistors Tn1 and Tn2 constituting the amplifier Amp is measured in the transistor evaluation mode, thereby using the characteristic difference between the paired transistors. More detailed measurement can be performed than measurement.
By using the semiconductor device 100, detailed measurement of the paired transistors constituting the amplifier is performed on the amplifier Amp determined to be defective. Therefore, it is determined as defective without increasing the time required for measuring the entire evaluation cell array. Detailed measurements can be made on the fabricated transistors.
Note that when the voltage output from the amplifier circuit 130 is small, an amplifier having a high amplification factor may be provided at a subsequent stage of the amplifier circuit 130.

Second Embodiment
FIG. 6 is a schematic block diagram showing the configuration of the semiconductor device 200 according to the second embodiment. As illustrated, the semiconductor device 200 includes m × n evaluation cells DUTa11 to DUTamn arranged in a matrix of m rows and n columns (n and m are positive integers), and is provided in the evaluation cell. This is a DMA-TEG that evaluates the difference in characteristics of pair transistors (comparators).
The semiconductor device 200 includes an evaluation cell array 210, an evaluation cell selection unit 220, an amplifier circuit 130, a source sense line SS, a source force line SF, drain sense lines DSL and DSR, drain force lines DFL and DFR, A measurement switching signal input line VthM, data lines DR and DL, an input signal line Vin, and a reference signal line Vref are provided.

Further, the semiconductor device 200 includes column selection signal lines COL1 to COLn, column selection switches CG1L to CGnL, CG1R to CGnR, and data lines D1L to DnL and D1R to DnR provided for each column of the evaluation cell array 210. It has.
In addition, the semiconductor device 200 includes row selection signal lines WL1 to WLm provided for each row of the evaluation cell array 210.

  The source sense line SS, the source force line SF, the drain sense lines DSL and DSR, the drain force lines DFL and DFR, the measurement switching signal input line VthM, the input signal line Vin, and the reference signal line Vref Are connected to the evaluation cells DUTa11 to DUTamn, and are connected to different external terminals.

Evaluation cells DUTa11 to DUTam1 constituting the first column of the evaluation cell array 210 are connected to data lines D1L and D1R and a column selection signal line COL1 provided corresponding to the column. Similarly to the evaluation cells DUTa11 to DUTam1 constituting the first column, the evaluation cells constituting each of the second to nth columns of the evaluation cell array 210 also have data lines D2L and D2R provided corresponding to the respective columns. ,..., DnL, DnR and column selection signal lines COL2,.
The evaluation cells DUTa11 to DUTa1n constituting the first row of the evaluation cell array 210 are connected to a row selection signal line WL1 provided corresponding to the row. Similarly to the evaluation cells DUTa11 to DUTa1n constituting the first row, the evaluation cells constituting each of the second to mth rows of the evaluation cell array 210 are also connected to the row selection signal lines WL2 to WLm provided corresponding to the respective cells. It is connected.

  The evaluation cell selection unit 220 includes a column decoder 221 and row decoders 222-1 to 222-m. The column decoder 221 is connected to the column selection signal lines COL1 to COLn, decodes the input column address, sets one of the column selection signal lines COL1 to COLn to the H level that is the power supply potential Vdd, and the like. The column selection signal line is set to the L level which is the ground potential.

When the column selection signal line COL1 is at the H level, the column selection switch CG1L energizes the data line D1L and the data line DL corresponding to the switch, and when the column selection signal line COL1 is at the L level, The data line DL is turned off. Similarly to the column selection switch CG1L, the column selection switches CG2L to CGnL energize the data lines D2L to DnL and the data line DL corresponding to the switch when the column selection signal lines COL2 to COLn are at the H level. When the column selection signal lines COL2 to COLn are at the L level, the data lines D2L to DnL and the data lines DL corresponding to the switch are turned off.
Similarly to the column selection switches CG1L to CGnL, the column selection switches CG1R to CGnR energize the data lines D1R to DnR and the data line DR corresponding to the switch when the column selection signal lines COL1 to COLn are at the H level. When the column selection signal line COL1 is at the L level, the data lines D1R to DnR and the data line DL are turned off.

  Row decoders 222-1 to 222-m are provided corresponding to each row of evaluation cell array 210. The row decoder 222-1 is connected to a row selection signal line WL1 corresponding to the row of the evaluation cell array 210 corresponding to the row decoder. Similarly to the row decoder 122-1, the row decoders 222-2 to 222-m are connected to row selection signal lines WL2 to WLm corresponding to the rows of the evaluation cell array 210 to which the row decoder corresponds.

The row decoder 222-1 decodes the input row address to determine whether or not the first row of the corresponding evaluation cell array 210 is selected. If selected, the connected row selection signal line is selected. WL1 is set to H level. Similarly to the row decoder 222-1, the row decoders 222-2 to 222m decode the input row address to determine whether or not the corresponding row of the evaluation cell array 210 has been selected. In this case, the connected row selection signal lines WL2 to n are set to the H level.
The row decoders 222-1 to 222-m set the connected row selection signal lines WL1 to WLm to the L level when the row of the evaluation cell array 210 corresponding to the decoder is not selected.

With the above-described configuration, the evaluation cell selection unit 220 sets any one of the column selection signal lines COL1 to COLn to the H level and the row selection signal lines WL1 to WLn according to the input column address and row address. Any one of the evaluation cells DUTa11 to DUTamn included in the evaluation cell array 210 is selected by setting any one of these to H level.
The amplifier circuit 130 is connected to the data lines DL and DR, amplifies the potential difference between the data lines DL and DR, and outputs it to the output terminal OUT.

Hereinafter, the configuration of the evaluation cells DUTa11 to DUTmn will be described with reference to FIG.
FIG. 7 is a circuit diagram showing a configuration of the amplifier circuit 130 and the evaluation cell DUTamn in the same embodiment. Since the evaluation cells DUTa11 to DUTamn have the same configuration, the configuration of the evaluation cell DUTamn will be described as a representative. In addition, evaluation cells DUTa1n to DUTa (m−1) n (not shown) are arranged in the column in the same manner as DUTamn.
Here, a case will be described in which the evaluation target by DMA-TEG is the transistors Tn1 and Tn2 forming the pair transistors of the amplifier configured by the N-channel MOS transistor shown in FIG.

As shown in FIG. 7, the amplifier circuit 130 has the same configuration as the amplifier circuit 130 shown in FIG.
The evaluation cell DUTamn includes transistors Tn1, Tn2, and Tn5, switches SW1F to SW3F, SW1S to SW3S, SW4, and SW5, and a decoder circuit 20. As shown in FIG. 7, the evaluation cell DUTamn is provided with a decoder circuit 20, and the evaluation cell of the first embodiment shown in FIG. 4 except that the switches SW1F to SW3F and SW1S to SW3S are controlled by the output of the decoder circuit 20. Since it is the same structure as DUTmn, the corresponding code | symbol is attached | subjected to the applicable location and the description is abbreviate | omitted.

The decoder circuit 20 includes a 3-input NAND gate 21 and an inverter 22. The input of the NAND gate 21 is connected to the column selection signal line COLn, the measurement switching signal input line VthM, and the row selection signal line WLm. The output of the NAND gate 21 is connected to the inverter 22 and the switches SW1F to SW3F and SW1S to SW3S. The output of the inverter 22 is connected to the switches SW1F to SW3F and SW1S to SW3S.
Compared with the configuration of the DUTmn shown in FIG. 4, the switches SW1F to SW3F and SW1S to SW3S are connected to the output of the inverter 22 instead of the measurement switching signal output line VthMm, and are connected to the measurement switching signal output line VthMBm with a NAND gate. 21 outputs are connected.

For example, when the evaluation cell DUTamn is selected by the column address and the row address, and the measurement switching signal input line VthM is at the H level, the output of the NAND gate 21 becomes the L level and the output of the inverter 22 becomes the H level. As a result, the switches SW1F to SW3F and SW1S to SW3S are energized, and the transistor evaluation mode is selected.
Further, when the evaluation cell DUTamn is selected by the column address and the row address and the measurement switching signal input line VthM is at the L level, the output of the NAND gate 21 becomes the H level and the output of the inverter 22 becomes the L level. As a result, the switches SW1F to SW3F and SW1S to SW3S are deenergized, and the amplifier evaluation mode is selected.
As described above, the evaluation cell DUTamn can be switched between the amplifier evaluation mode and the transistor evaluation mode similarly to the evaluation cell DUmn of the first embodiment.

  As described above, since the evaluation cell includes the decoder circuit 20, the evaluation cell selected by the column address and the row address can be selected in the amplifier evaluation mode and the transistor evaluation mode by the signal of the measurement switching signal input line VthM. Switching can be done. As a result, the semiconductor device 200 according to the present embodiment does not need to be wired with the measurement switching signal output line VthMBm as compared with the semiconductor device 100 according to the first embodiment, and the mounting area of the semiconductor device 200 can be reduced.

<Third Embodiment>
FIG. 8 is a schematic block diagram showing the configuration of the semiconductor device 300 according to the third embodiment. As illustrated, the semiconductor device 300 includes m × n evaluation cells DUT11 to DUTmn arranged in a matrix of m rows and n columns (n and m are positive integers), and is provided in the evaluation cell. DMA-TEG for evaluating the input offset voltage of the amplifier (comparator).
The semiconductor device 300 is a modification of the semiconductor device 100 (FIG. 3) of the first embodiment, and measures the input offset voltage Voff of the amplifier Amp shown in FIG. Since the semiconductor device 300 has the same configuration except for the following points from the semiconductor device 100 of the first embodiment, the corresponding portions are denoted by the same reference numerals and description thereof is omitted. The difference is that instead of inputting the reference voltage from the reference signal line Vref to the evaluation cells DUT11 to DUTmn, the output signal of the amplifier circuit 130 is input to the evaluation cells DUT11 to DUTmn.

FIG. 9 is a circuit diagram showing a configuration of the amplifier circuit 130 and the evaluation cell DUTmn in the same embodiment. The configuration of the evaluation cell DUTmn in this embodiment is the same as that of the evaluation cell DUTmn in the first embodiment except that the gate of the transistor Tn2 is connected to the output of the amplifier circuit 130. The description is omitted.
Since the output of the amplifier circuit 130 is applied to the gate of the transistor Tn2, the input offset voltage of the amplifier constituted by the transistors Tn1, Tn2, Tp3, Tp4, and Tn5 can be measured.

<Fourth embodiment>
FIG. 10 is a schematic block diagram illustrating the configuration of the semiconductor device 400 according to the fourth embodiment. As illustrated, the semiconductor device 400 includes m × n evaluation cells DUTb11 to DUTbmn arranged in a matrix of m rows and n columns (n and m are positive integers), and is provided in the evaluation cell. This is a DMA-TEG for evaluating the difference in characteristics of the obtained amplifier (comparator).
The semiconductor device 400 includes an evaluation cell array 410, an evaluation cell selection unit 120, an amplifier circuit 430, a measurement switching signal input line VthM, data lines DR and DL, an input signal line Vin, and a reference signal line Vref. ing. Since the evaluation cell selection unit 120 has the same configuration as that of the semiconductor device 100 (FIG. 3) of the first embodiment, the same reference numerals are given and description thereof is omitted.

Further, the semiconductor device 400 includes source sense lines SS1 to SSn, source force lines SF1 to SFn, drain sense lines DSL1 to DSLn, DSR1 to DSRn, drain force lines DFL1 to DFLn, which are provided for each column of the evaluation cell array 410. DFR1 to DFRn, gate force lines GF1 to GFn, gate sense lines GS1 to GSn, column selection signal lines COL1 to COLn, column selection switches CG1L to CGnL, CG1R to CGnR, and data lines D1L to DnL, D1R to DnR It has.
The semiconductor device 400 includes measurement switching signal output lines VthM1 to VthMm, VthMB1 to VthMBm, and row selection signal lines WL1 to WLm provided for each row of the evaluation cell array 410.
Also, source sense lines SS1 to SSn, source force lines SF1 to SFn, drain sense lines DSL1 to DSLn, DSR1 to DSRn, drain force lines DFL1 to DFLn, DFR1 to DFRn, gate force lines GF1 to GFn, gate sense lines GS1 to GS1 The GSn, the measurement switching signal input line VthM, the input signal line Vin, and the reference signal line Vref are connected to different external terminals.

The evaluation cells DUTb11 to DUTbm1 constituting the first column of the evaluation cell array 410 have data lines D1L, D1R, source sense lines SS1, source force lines SF1, drain sense lines DSL1, DSR1, The drain force lines DFL1, DFR1, the gate force line GF1, and the gate sense line GS1 are connected.
Similarly to the evaluation cells DUTb11 to DUTbm1 constituting the first column, the evaluation cells constituting each of the second to nth columns of the evaluation cell array 410 are also provided with data lines D2L and D2R provided corresponding to the respective columns. , ..., DnL, DnR, source sense lines SS2, ..., SSn, source force lines SF2, ..., SFn, drain sense lines DSL2, DSR2, ..., DSLn, DSRn, drain force lines DFL2, DFR2, ..., DFLn, DFRn Are connected to the gate force lines GF2 to GFn and the gate sense lines GS2 to GSn. The evaluation cells DUTb11 to DUTbmn are connected to the input signal line Vin and the reference signal line Vref.

The evaluation cells DUTb11 to DUTb1n constituting the first row of the evaluation cell array 410 are connected to a row selection signal line WL1 and measurement switching signal output lines VthM1 and VthMB1 provided corresponding to the row. Similarly to the evaluation cells DUTb11 to DUTb1n constituting the first row, the evaluation cells constituting each of the second to mth rows of the evaluation cell array 410 are also provided corresponding to the row selection signal lines WL2 to WLm. , And measurement switching signal output lines VthM2, VthMB2,..., VthMm, VthMBm.
The amplifier circuit 430 is connected to the data lines DL and DR, amplifies the potential difference between the data lines DL and DR, and outputs it to the output terminal OUT.

FIG. 11 is a circuit diagram showing a configuration of the evaluation cell DUTbmn in the same embodiment. Since the evaluation cells DUTb11 to DUTbmn have the same configuration, the configuration of the evaluation cell DUTbmn will be described as a representative. In addition, evaluation cells DUTb1n to DUTb (m−1) n (not shown) are arranged in the column in the same manner as DUTbmn.
Here, a case will be described in which the evaluation object by the DMA-TEG is an amplifier composed of the N-channel MOS transistor shown in FIG. 2A, and the amplifier is included in the evaluation cell.

  The evaluation cell DUTbmn includes transistors Tn1, Tn2, Tp3, Tp4, and Tn5, and switches SW1F to SW3F, SW1S to SW3S, SW4, SW5, SW6F, SW6S, and SW7. As illustrated, the evaluation cell DUTbmn includes the amplifier Amp illustrated in FIG. 2A. The evaluation cell DUTbmn includes transistors Tp3 and Tp4 and switches SW6F and SW6S compared to the evaluation cell DUTmn of the first embodiment. , SW7 is added. Since the connections of the transistors Tn1, Tn2, and Tn5 and the switches SW1F to SW3F, SW1S to SW3S, SW4, and SW5 are the same, the description thereof is omitted.

  The transistor Tp3 has a source connected to the power supply terminal N5 that supplies the power supply potential Vdd, a drain connected to the drain of the transistor Tn1 via the connection point N1, and the switches SW1F, SW1S, SW4, and SW7, and a gate connected to the connection point N4. Through the switches SW6F, SW6S, SW7 and the gate of the transistor Tp4. The transistor Tp4 has a source connected to the power supply terminal N5 that supplies the power supply potential Vdd, a drain connected to the drain of the transistor Tn2 via the connection point N2, the switches SW2F, SW2S, and SW5, and a gate connected via the connection point N4. The switches SW6F, SW6S, SW7 and the gate of the transistor Tp3 are connected.

  The switch SW6F is connected to the connection point N4 and the gate force line GFn, and energization and non-energization between the connection point N4 and the gate force line GFn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch. The switch SW6S is connected to the connection point N4 and the gate sense line GSn, and energization and non-energization between the connection point N4 and the gate sense line GSn according to signals input from the measurement switching signal output lines VthMm and VthMBm. And switch. The switch SW7 switches between energization and non-energization between the connection point N4 and the connection point N1, in accordance with signals input from the measurement switching signal output lines VthMm and VthMBm.

  With the above-described configuration, the evaluation cell selected by the evaluation cell selection unit 120 has the drain of the transistor Tn1 connected to the data line DnL and the drain of the transistor Tn2 connected to the data line DnR by the row selection signal line WLm. The Further, the selected evaluation cell is connected to the data line DnL and DnR corresponding to the evaluation cell by the column selection signal line COLn and the amplifier circuit 430, and the amplifier included in the evaluation cell via the data line DnL and DnR. The potentials of the connection points N1 and N2 are output to the amplifier circuit 430.

  When an L level signal is input from the external terminal to the measurement switching signal input line VthM, the row decoders 122-1 to 122-m set the measurement switching signal output lines VthM1 to VthMm to the L level, and the measurement switching signal output line VthMB1. ˜VthMBm is set to H level, and the amplifier evaluation mode is selected. At this time, the switches SW1F to SW3F, SW1S to SW3S, SW6F, and SW6S are in a non-energized state. At this time, the evaluation cell selected by the row address and the column address outputs the voltages at the connection points N1 and N2 corresponding to the voltages applied from the input signal line Vin and the reference signal line Vref to the amplifier circuit 430.

  When an H level signal is input from the external terminal to the measurement switching signal input line VthM, the row decoders 122-1 to 122-m set the measurement switching signal output lines VthM1 to VthMm to the H level and output the measurement switching signal. The lines VthMB1 to VthMBm are set to L level, and the transistor evaluation mode is selected. At this time, the switches SW1F to SW3F, SW1S to SW3S, SW6F, and SW6S are energized. At this time, similarly to the first embodiment, the threshold voltages of the transistors Tn1 and Tn2 included in the evaluation cell selected by the row address and the column address can be measured. For example, when measuring the threshold voltage of the transistor Tp3, it is only necessary to input 1.0 [V] to the power supply terminal N5, 0 [V] to the drain force terminal DFLn, and the gate voltage to the gate force line GFn. Thus, by performing the measurement, the characteristic values such as the threshold voltages of the transistors Tp3 and Tp4 can be measured in the same manner as the transistors Tn1 and Tn2.

As described above, in the semiconductor device 400, the amplifier Amp included in the evaluation cell can be measured in the amplifier evaluation mode. In the transistor evaluation mode, the threshold voltages of the transistors Tn1, Tn2, Tp3, and Tp4 constituting the amplifier Amp are measured. Can be done. Thereby, in the semiconductor device 400, by measuring the characteristics of the amplifier Amp in the amplifier evaluation mode, it is possible to measure many evaluation cells in a shorter time than measuring the transistors included in the evaluation cell individually. The time required for detecting the transistor can be shortened. In addition, by measuring the threshold voltage of each of the transistors Tn1, Tn2, Tp3, and Tp4 constituting the amplifier Amp in the transistor evaluation mode with respect to the amplifier Amp determined to be defective based on the measurement result in the amplifier evaluation mode, Compared to the measurement using the characteristic difference of the transistor, detailed measurement can be performed.
Similarly to the connection points N1 to N4, the power supply terminal N5 may be provided with an external terminal for applying a voltage and an external terminal for measuring the applied voltage. Thereby, it is possible to improve the accuracy of measuring the characteristic values of the transistors Tp3 and Tp4 in the transistor evaluation mode.

<Fifth Embodiment>
FIG. 12 is a schematic block diagram showing the configuration of the semiconductor device 500 according to the fifth embodiment. As shown in the figure, a semiconductor device 500 has m × n evaluation cells DUTc11 to DUTcmn arranged in a matrix of m rows and n columns (n and m are positive integers), and is provided in the evaluation cell. It is a DMA-TEG that evaluates the obtained amplifier (comparator).
The semiconductor device 500 includes an evaluation cell array 510, an evaluation cell selection unit 220, an amplifier circuit 430, a source sense line SS, a source force line SF, drain sense lines DSL and DSR, drain force lines DFL and DFR, A gate force line GF, a gate sense line GS, a measurement switching signal input line VthM, data lines DR and DL, an input signal line Vin, and a reference signal line Vref are provided. Since the evaluation cell selection unit 220 has the same configuration as that of the semiconductor device 200 (FIG. 6) of the second embodiment, the same reference numerals are given and description thereof is omitted.

Further, the semiconductor device 500 includes column selection signal lines COL1 to COLn, column selection switches CG1L to CGnL, CG1R to CGnR, and data lines D1L to DnL and D1R to DnR provided for each column of the evaluation cell array 510. It has.
In addition, the semiconductor device 500 includes row selection signal lines WL1 to WLm provided for each row of the evaluation cell array 510.

  Further, the source sense line SS, the source force line SF, the drain sense lines DSL and DSR, the drain force lines DFL and DFR, the gate force line GF, the gate sense line GS, and the measurement switching signal input line VthM, The input signal line Vin and the reference signal line Vref are connected to the evaluation cells DUTc11 to DUTcmn and are connected to different external terminals.

Evaluation cells DUTc11 to DUTcm1 constituting the first column of evaluation cell array 510 are connected to data lines D1L and D1R and column selection signal line COL1 provided corresponding to the column. Similarly to the evaluation cells DUTc11 to DUTcm1 constituting the first column, the evaluation cells constituting each of the second to nth columns of the evaluation cell array 510 are also provided with data lines D2L and D2R provided corresponding to the respective columns. ,..., DnL, DnR and column selection signal lines COL2,.
The evaluation cells DUTc11 to DUTc1n constituting the first row of the evaluation cell array 510 are connected to a row selection signal line WL1 provided corresponding to the row. Similarly to the evaluation cells DUTc11 to DUTc1n constituting the first row, the evaluation cells constituting each of the second to mth rows of the evaluation cell array 510 are also connected to the row selection signal lines WL2 to WLm provided corresponding thereto. It is connected.

FIG. 13 is a circuit diagram showing a configuration of the evaluation cell DUTcmn in the same embodiment. Since the evaluation cells DUTc11 to DUTcmn have the same configuration, the configuration of the evaluation cell DUTcmn will be described as a representative. In addition, evaluation cells DUTc1n to DUTc (m−1) n (not shown) are arranged in the column in the same manner as DUTcmn.
Here, a case will be described in which the DMA-TEG evaluation target is an amplifier having an N-channel MOS transistor shown in FIG. 2A as an input transistor.

The evaluation cell DUTcmn includes transistors Tn1, Tn2, Tp3, Tp4, and Tn5, switches SW1F to SW3F, SW1S to SW3S, SW4, SW5, SW6F, SW6S, and SW7, and a decoder circuit 20.
As shown in FIG. 13, the evaluation cell DUTcmn is provided with a decoder circuit 20, and the switches SW1F to SW3F, SW1S to SW3S, SW6F, SW6S, and SW7 are controlled by the output of the decoder circuit 20, as shown in FIG. Since it is the same structure as evaluation cell DUTbmn of 4 embodiment, the same code | symbol is attached | subjected to a corresponding location and the description is abbreviate | omitted. The decoder circuit 20 has the same configuration as the decoder circuit 20 included in the evaluation cell DUTamn of the second embodiment shown in FIG.
The switches SW1F to SW3F, SW1S to SW3S, SW6F, SW6S, and SW7 are connected to the output of the inverter 22 instead of the measurement switching signal output line VthMm as compared with the configuration of the DUTbmn shown in FIG. The output of the NAND gate 21 is connected instead of VthMBm.

With the above-described configuration, the semiconductor device 500 does not output the measurement switching signal output lines VthMm and VthMBm from the row decoders 222-1 to 222-m for the evaluation cells DUTb11 to DUTbmn, and the amplifier evaluation mode and the transistor evaluation mode. And can be switched.
Further, as in the semiconductor device 200 of the second embodiment, the semiconductor device 500 includes the decoder circuit 20 so that the evaluation cell selected by the column address and the row address is the measurement switching signal input line. Switching between the amplifier evaluation mode and the transistor evaluation mode can be performed by the VthM signal. As a result, the semiconductor device 500 according to the present embodiment does not need to be wired with the measurement switching signal output line VthMBm as compared with the semiconductor device 400 according to the fourth embodiment, and the mounting area of the semiconductor device 500 can be reduced.

<Sixth Embodiment>
FIG. 14 is a schematic block diagram showing the configuration of the semiconductor device 600 according to the sixth embodiment. As illustrated, the semiconductor device 600 has m × n evaluation cells DUTd11 to DUTdmn arranged in a matrix of m rows and n columns (n and m are positive integers), and is provided in the evaluation cell. This is a DMA-TEG that evaluates the input offset voltage of the amplifier (comparator) and the transistors constituting the amplifier.
The semiconductor device 600 includes an evaluation cell array 610, an evaluation cell selection unit 120, an amplifier circuit 430, a measurement switching signal input line VthM, a data line DR, and an input signal line Vin. Since the evaluation cell selection unit 120 has the same configuration as the evaluation cell selection unit 120 (FIG. 3) of the first embodiment, the same reference numerals are given and description thereof is omitted.

The semiconductor device 600 includes source sense lines SS1 to SSn, source force lines SF1 to SFn, drain sense lines DSL1 to DSLn, DSR1 to DSRn, drain force lines DFL1 to DFLn, which are provided for each column of the evaluation cell array 610. DFR1 to DFRn, gate force lines GF1 to GFn, gate sense lines GS1 to GSn, column selection signal lines COL1 to COLn, column selection switches CG1R to CGnR, and data lines D1L to DnL, D1R to DnR are provided.
The semiconductor device 600 includes measurement switching signal output lines VthM1 to VthMm, VthMB1 to VthMBm, and row selection signal lines WL1 to WLm provided for each row of the evaluation cell array 610.
Also, source sense lines SS1 to SSn, source force lines SF1 to SFn, drain sense lines DSL1 to DSLn, DSR1 to DSRn, drain force lines DFL1 to DFLn, DFR1 to DFRn, gate force lines GF1 to GFn, gate sense lines GS1 to GS1 The GSn, the measurement switching signal input line VthM, and the input signal line Vin are connected to different external terminals.

The evaluation cells DUTd11 to DUTdm1 constituting the first column of the evaluation cell array 610 have data lines D1L and D1R, a source sense line SS1, a source force line SF1, a drain sense line DSL1, DSR1, The drain force lines DFL1, DFR1, the gate force line GF1, and the gate sense line GS1 are connected.
Similarly to the evaluation cells DUTd11 to DUTdm1 configuring the first column, the evaluation cells configuring each of the second to nth columns of the evaluation cell array 610 are also provided with data lines D2L and D2R provided corresponding to the respective columns. , ..., DnL, DnR, source sense lines SS2, ..., SSn, source force lines SF2, ..., SFn, drain sense lines DSL2, DSR2, ..., DSLn, DSRn, drain force lines DFL2, DFR2, ..., DFLn, DFRn Are connected to the gate force lines GF2 to GFn and the gate sense lines GS2 to GSn.

  The evaluation cells DUTd11 to DUTd1n constituting the first row of the evaluation cell array 610 are connected to a row selection signal line WL1 and measurement switching signal output lines VthM1 and VthMB1 provided corresponding to the row. Similarly to the evaluation cells DUTd11 to DUTd1n constituting the first row, the evaluation cells constituting each of the second to mth rows of the evaluation cell array 610 are also provided corresponding to the row selection signal lines WL2 to WLm. , And measurement switching signal output lines VthM2, VthMB2,..., VthMm, VthMBm.

When the column selection signal line COL1 is at the H level, the column selection switch CG1R turns on the data line D1R and the data line DR corresponding to the switch, and when the column selection signal line COL1 is at the L level, The data line DR is turned off. Similarly to the column selection switch CG1R, the column selection switches CG2R to CGnR energize the data lines D2R to DnR and the data line DR corresponding to the switch when the column selection signal lines COL2 to COLn are at the H level. When the column selection signal lines COL2 to COLn are at the L level, the data lines D2R to DnR and the data line DR corresponding to the switch are turned off.
The input signal line Vin is connected to the amplifier circuit 430 and the data lines D1L to DnL.
The amplifier circuit 430 amplifies the potential difference between the input signal line Vin and the data line DR and outputs the amplified signal to the output terminal OUT.

FIG. 15 is a circuit diagram showing a configuration of the evaluation cell DUTdmn of the same embodiment. Since the evaluation cells DUTd11 to DUTdmn have the same configuration, the configuration of the evaluation cell DUTdmn will be described as a representative. Further, in the column, evaluation cells DUTd1n to DUTd (m−1) n (not shown) are arranged in the same manner as DUTdmn.
Here, a case will be described in which the evaluation object by the DMA-TEG is an amplifier composed of the N-channel MOS transistor shown in FIG. 2A, and the amplifier is included in the evaluation cell.

The evaluation cell DUTdmn includes transistors Tn1, Tn2, Tp3, Tp4, and Tn5, and switches SW1F to SW3F, SW1S to SW3S, SW5, SW6F, SW6S, and SW7. As shown in the figure, the evaluation cell DUTdmn includes the amplifier Amp shown in FIG. 2A. Compared with the evaluation cell DUTbmn (FIG. 11) of the fourth embodiment, the following three points are provided. Except for the differences, the connections of the transistors Tn1, Tn2, Tp3, Tp4, and Tn5 and the switches SW1F to SW3F, SW1S to SW3S, SW5, SW6F, SW6S, and SW7 are the same and will not be described.
Three different points are that the evaluation cell DUTdmn does not include the switch SW4, the gate of the transistor Tn1 is connected to the input signal line Vin via the data line DnL, and the gate of the transistor Tn2 is connected to the data line DnR. It is a connected point.

By configuring the evaluation cell DUTdmn as described above, the amplifier output is applied to the gate of the transistor Tn2 in the amplifier formed by the transistors Tn1, Tn2, Tp3, Tp4, and Tn5. Therefore, the amplifier included in the evaluation cell DUTdmn The input offset voltage can be measured.
In the evaluation cell DUTdmn, the configuration in which the gate of the transistor Tn2 is connected to the data line DnR is shown, but it may be connected to the connection point N2.

  In the first to sixth embodiments, the evaluation cell includes the transistor Tn5. However, the transistor Tn5 in the semiconductor device is provided by connecting one transistor Tn5 for each column of the evaluation cell array. You may reduce the number of Thereby, the mounting area of the evaluation cell array can be reduced.

  In the first to sixth embodiments, the amplifier is configured to use the N-channel MOS transistor as the input transistor. However, the P-channel MOS transistor shown in FIG. You may make it measure the amplifier of the structure used as a transistor.

100, 200, 300, 400, 500, 600 ... Semiconductor device 110, 210, 410, 510, 610 ... Evaluation cell array 120, 220 ... Evaluation cell selector 121, 221 ... Column decoders 122-1, 122-2, 122- m ... row decoders 222-1, 222-2, 222-m ... row decoders 130, 430 ... amplifier circuits CG1L, CG2L, CGnL ... column selection switches CG1R, CG2R, CGnR ... column selection switches DUT11, DUTmn, DUTa11, DUTamn, DUTb11, DUTbmn, DUTc11, DUTcmn, DUTd11, DUTdmn ... Evaluation cell Tn1, Tn2, Tp3, Tp4, Tn5 ... Transistor Tn11, Tn12, Tp13, Tp14, Tp15 ... Transistor SW1F, SW1S, SW2F SW2S, SW3F, SW3S, SW4, SW5, SW6F, SW6S, SW7 ... Switch Vin ... Input signal line, Vref ... Reference signal line D1L, D2L, DnL, D1R, D2R, DnR, DL, DR ... Data lines DFL, DFL1, DFL2, DFLn, DFR, DFR1, DFR2, DFRn ... Drain force line DSL, DSL1, DSL2, DSLn, DSR, DSR1, DSR2, DSRn ... Drain sense line SS, SS1, SS2, SSn ... Source sense line SF, SF1, SF2 , SFn: Source force line GS, GS1, GS2, GSn ... Gate sense line GF, GF1, GF2, GFn ... Gate force line COL1, COL2, COLn ... Column selection signal line WL1, WL2, WLm ... Row selection signal line VthM ... Measurement switching signal input Force line VthM1, VthM2, VthMm ... Measurement switching signal output line VthMB1, VthMB2, VthMBm ... Measurement switching signal output line

Claims (14)

A semiconductor device for evaluating transistor characteristics,
An evaluation cell having a plurality of transistors for comparing the magnitude relationship between an input voltage and a reference voltage and having a comparator for outputting a comparison result from two output terminals arranged in a matrix in the row and column directions. An evaluation cell array in row n columns (m and n are positive integers);
A first data line and a second data line belonging to each column of the evaluation cell array;
An amplifier circuit for amplifying and outputting a potential difference between the first and second data lines;
A first switch and a second switch which are provided for each column of the evaluation cell array and which switch connection between the first and second data lines belonging to the column and the amplifier circuit;
Comprising
The evaluation cell is
A third switch for switching connection between one of the two output terminals of the comparator and the first data line; and a fourth switch for switching connection between the other of the two output terminals of the comparator and the second data line. And
The semiconductor device is
Among the evaluation cells included in the evaluation cell array, a column selection signal for switching on / off of the first and second switches and a row selection signal for switching on / off of the third and fourth switches are output. An evaluation cell selection unit that selects any one evaluation cell and inputs the output of the selected evaluation cell to the amplifier circuit;
A semiconductor device comprising: a plurality of external terminals connected to the sources, drains, and gates of the plurality of transistors included in the evaluation cell selected by the evaluation cell selection unit. The comparator is
A first transistor in which the input voltage is applied to a gate and a drain is connected to one of the two output terminals;
A second transistor having a source connected to the source of the first transistor, a gate to which the reference voltage is applied, and a drain connected to the other of the two output terminals,
The semiconductor device according to claim 1, wherein sources of the first and second transistors are connected to a current source. The comparator is
A third transistor having a drain and a gate connected to the drain of the first transistor;
A fourth transistor having a gate connected to the gate of the third transistor, a source connected to the source of the third transistor, and a drain connected to the drain of the second transistor;
The semiconductor device according to claim 2, comprising: A first and a second drain force line, a source force line, a first and a second drain sense line, which are provided for each column of the evaluation cell array and are commonly connected to the evaluation cells belonging to the column of the evaluation cell array; A source sense line;
An input signal line commonly connected to a gate of the first transistor included in the evaluation cell;
A reference signal line commonly connected to the gate of the second transistor of the evaluation cell;
Comprising
The evaluation cell is
A fifth switch for switching the connection between the drain of the first transistor and the first drain force line by a measurement switching signal for switching between the measurement of the comparator and the measurement of the transistor included in the comparator;
A sixth switch for switching connection between the drain of the first transistor and the first drain sense line according to the measurement switching signal;
A seventh switch for switching the connection between the drain of the second transistor and the second drain force line by the measurement switching signal;
An eighth switch for switching the connection between the drain of the second transistor and the second drain sense line according to the measurement switching signal;
A ninth switch for switching connection between the source of the first and second transistors and the source force line by the measurement switching signal;
A tenth switch for switching connection between the source of the first and second transistors and the source sense line in response to the measurement switching signal;
The first and second drain force lines, the source force lines, the first and second drain sense lines, the source sense lines, the input signal lines, and the reference signal lines are connected to different external terminals. The semiconductor device according to claim 2, wherein: A first and a second drain force line, a source force line, a first and a second drain sense line, and a source sense line that are commonly connected to the evaluation cell;
An input signal line commonly connected to a gate of the first transistor included in the evaluation cell;
A reference signal line commonly connected to the gate of the second transistor of the evaluation cell;
Comprising
The evaluation cell is
A fifth switch for switching a connection between the drain of the first transistor and the first drain force line;
A sixth switch for switching the connection between the drain of the first transistor and the first drain sense line;
A seventh switch for switching connection between the drain of the second transistor and the second drain force line;
An eighth switch for switching connection between the drain of the second transistor and the second drain sense line;
A ninth switch for switching connection between the sources of the first and second transistors and the source force line;
A tenth switch for switching connection between the sources of the first and second transistors and the source sense line;
When detecting that the own cell is selected according to the row selection signal and the column selection signal and measuring the comparator of the own cell, the fifth to tenth switches are turned off, The semiconductor device according to claim 2, further comprising: a decoder circuit that turns on the fifth to tenth switches when measuring a transistor included in the comparator. A first and second drain force line, a source force line, a gate force line, and a first and second line that are provided for each column of the evaluation cell array and are commonly connected to the evaluation cells belonging to the column of the evaluation cell array. A drain sense line, a source sense line, a gate sense line,
An input signal line commonly connected to a gate of the first transistor included in the evaluation cell;
A reference signal line commonly connected to the gate of the second transistor of the evaluation cell;
Comprising
The evaluation cell is
A fifth switch for switching the connection between the drain of the first transistor and the first drain force line by a measurement switching signal for switching between the measurement of the comparator and the measurement of the transistor included in the comparator;
A sixth switch for switching a connection between the drain of the first transistor and the drain sense line according to the measurement switching signal;
A seventh switch for switching the connection between the drain of the second transistor and the second drain force line by the measurement switching signal;
An eighth switch for switching the connection between the drain of the second transistor and the second drain sense line according to the measurement switching signal;
A ninth switch for switching connection between the source of the first and second transistors and the source force line by the measurement switching signal;
A tenth switch for switching the connection between the source of the first and second transistors and the source sense line by the measurement switching signal;
An eleventh switch for switching the connection between the gates of the third and fourth transistors and the gate force line according to the measurement switching signal;
A twelfth switch that switches connection between the gates of the third and fourth transistors and the gate sense line in response to the measurement switching signal;
A thirteenth switch that switches connection between the gates of the third and fourth transistors and the drain of the first transistor in response to the measurement switching signal;
When the fifth to twelfth switches are on, the thirteenth switch is off; when the fifth to twelfth switches are off, the thirteenth switch is on;
The first and second drain force lines, the source force lines, the gate force lines, the first and second drain sense lines, the source sense lines, the gate sense lines, the input signal lines, and the reference signal lines, respectively. The semiconductor device according to claim 3, wherein the semiconductor device is connected to the plurality of different external terminals. A first and a second drain force line, a source force line, a gate force line, a first and a second drain sense line, a source sense line, a gate sense line, which are commonly connected to the evaluation cell;
An input signal line commonly connected to a gate of the first transistor included in the evaluation cell;
A reference signal line commonly connected to the gate of the second transistor of the evaluation cell;
Comprising
The evaluation cell is
A fifth switch for switching a connection between the drain of the first transistor and the first drain force line;
A sixth switch for switching connection between the drain of the first transistor and the drain sense line;
A seventh switch for switching connection between the drain of the second transistor and the second drain force line;
An eighth switch for switching connection between the drain of the second transistor and the second drain sense line;
A ninth switch for switching connection between the sources of the first and second transistors and the source force line;
A tenth switch for switching connection between the sources of the first and second transistors and the source sense line;
An eleventh switch for switching connection between the gates of the third and fourth transistors and the gate force line;
A twelfth switch for switching connection between the gates of the third and fourth transistors and the gate sense line;
A thirteenth switch for switching connection between the gates of the third and fourth transistors and the drain of the third transistor;
When detecting that the own cell is selected according to the row selection signal and the column selection signal and measuring the comparator of the own cell, the fifth to twelfth switches are turned off and the first switch is turned off. And a decoder circuit that turns on the fifth to twelfth switches and turns off the thirteenth switch when measuring a transistor included in the comparator of the own cell. The semiconductor device according to claim 3. The semiconductor device according to claim 1, wherein an output of the amplifier circuit is used as the reference voltage. A first and a second drain force line, a source force line, a first and a second drain sense line, which are provided for each column of the evaluation cell array and are commonly connected to the evaluation cells belonging to the column of the evaluation cell array; A source sense line;
An input signal line commonly connected to a gate of the first transistor included in the evaluation cell;
Comprising
The evaluation cell is
A fifth switch for switching the connection between the drain of the first transistor and the first drain force line by a measurement switching signal for switching between the measurement of the comparator and the measurement of the transistor included in the comparator;
A sixth switch for switching connection between the drain of the first transistor and the first drain sense line according to the measurement switching signal;
A seventh switch for switching the connection between the drain of the second transistor and the second drain force line by the measurement switching signal;
An eighth switch for switching the connection between the drain of the second transistor and the second drain sense line according to the measurement switching signal;
A ninth switch for switching connection between the source of the first and second transistors and the source force line by the measurement switching signal;
A tenth switch for switching connection between the source of the first and second transistors and the source sense line in response to the measurement switching signal;
The output of the amplifier circuit is applied to the gate of the second transistor of the evaluation cell,
The first and second drain force lines, the source force lines, the first and second drain sense lines, the source sense lines, and the input signal lines are connected to different external terminals. The semiconductor device according to claim 2. An evaluation cell having a plurality of transistors for comparing the magnitude relationship between an input voltage and a reference voltage and having a comparator that outputs a comparison result from one output terminal is arranged in a matrix in the row and column directions. An evaluation cell array in row n columns (m and n are positive integers);
A first data line and a second data line belonging to each column of the evaluation cell array;
An amplifier circuit for amplifying and outputting a potential difference between the first and second data lines;
A first switch which is provided for each column of the evaluation cell array and which switches connection between the first data line belonging to the column and the amplifier circuit;
The evaluation cell is
A second switch for switching the connection between the one output terminal of the comparator and the second data line;
The semiconductor device is
A column selection signal for switching on and off of the first switch and a row selection signal for switching on and off of the second switch are output, and any one of the evaluation cells included in the evaluation cell array is output. An evaluation cell selection unit that selects an evaluation cell and inputs an output of the selected evaluation cell to the amplifier circuit; and sources, drains, and gates of the plurality of transistors included in the evaluation cell selected by the evaluation cell selection unit A plurality of external terminals for measuring or applying each voltage, and
The semiconductor device, wherein the input voltage is applied via the first data line, and the reference voltage is a comparison result output from the comparator included in the evaluation cell. The comparator is
A first transistor having a gate connected to the first data line;
A second transistor having a source connected to the source of the first transistor, a gate connected to the second data line, and a drain connected to the one output terminal;
A third transistor having a drain and a gate connected to the drain of the first transistor;
A fourth transistor having a drain connected to the drain of the second transistor and a source connected to the source of the third transistor;
With
The semiconductor device according to claim 9, wherein sources of the first and second transistors are connected to a current source. A first and second drain force line, a source force line, a gate force line, and a first and second line that are provided for each column of the evaluation cell array and are commonly connected to the evaluation cells belonging to the column of the evaluation cell array. A drain sense line, a source sense line, a gate sense line,
Comprising
The evaluation cell is
A third switch for switching connection between the drain of the first transistor and the first drain force line by a measurement switching signal for switching between measurement of the comparator and measurement of the transistor included in the comparator;
A fourth switch that switches connection between the drain of the first transistor and the first drain sense line in response to the measurement switching signal;
A fifth switch for switching a connection between the drain of the second transistor and the second drain force line by the measurement switching signal;
A sixth switch for switching the connection between the drain of the second transistor and the second drain sense line according to the measurement switching signal;
A seventh switch for switching connection between the source of the first and second transistors and the source force line by the measurement switching signal;
An eighth switch for switching the connection between the source of the first and second transistors and the source sense line according to the measurement switching signal;
A ninth switch for switching the connection between the gates of the third and fourth transistors and the gate force line according to the measurement switching signal;
A tenth switch for switching the connection between the gates of the third and fourth transistors and the gate sense line according to the measurement switching signal;
An eleventh switch for switching the connection between the gates of the third and fourth transistors connected to each other and the drain of the first transistor according to the measurement switching signal;
With
When the fifth to tenth switches are on, the eleventh switch is off; when the fifth to tenth switches are off, the eleventh switch is on;
The first and second drain force lines, the source force lines, the gate force lines, the first and second drain sense lines, the source sense lines, the gate sense lines, and the first data lines are different from each other. The semiconductor device according to claim 11, wherein the semiconductor device is connected to a plurality of external terminals. The current source is
A common connection is provided for each column of the evaluation cell array and is commonly connected to the sources of the first and second transistors of the evaluation cells belonging to the column of the evaluation cell array, and The semiconductor device according to claim 12. The current source is
It is provided for each of the evaluation cells and is commonly connected to the sources of the first and second transistors of the evaluation cell. The semiconductor device described.

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