JP4880942B2 - Semiconductor integrated chip and semiconductor integrated device - Google Patents

Description

  The present invention relates to a semiconductor integrated chip, and is particularly suitable for a semiconductor integrated chip having a process monitor.

When creating a pattern on a wafer in a semiconductor process, a process monitor for examining a transistor, a capacitance value, or a resistance value in order to monitor variations in element characteristics in each wafer or lot in the wafer surface. It is important to place
Generally, a semiconductor process monitor is arranged in a different area from a semiconductor integrated chip (hereinafter referred to as an LSI chip) in which a large number of semiconductor integrated circuits (hereinafter referred to as LSI (Large Scale Integration) circuits) are integrated into one chip.
For example, as shown in FIG. 5, it is arranged in the scribe line 101 surrounding the LSI chip 100, or the process monitor chip 102 is arranged in the same wafer as the LSI chip 100 as shown in FIG.
However, when the process monitor is arranged on the scribe line 101 as shown in FIG. 5, it is necessary to create a cell dedicated to the monitor by wiring in the elongated area. Will shift. Further, since the scribe line 101 has a small area, it is difficult to route a long wiring. Further, the scribe line 101 may be used for other purposes, and there is a problem that it is difficult to arrange the process monitor evenly in the wafer surface.
On the other hand, when the LSI chip 100 and the process monitor chip 102 are mixedly mounted on the wafer as shown in FIG. 6, since there is a dedicated process monitor area, the wiring can be designed in a state close to the actual wiring. Further, since the area is uniformly formed in the wafer, the in-plane distribution can be measured. However, in this case, since the area of the LSI chip 100 on the wafer is reduced, there is a drawback that the chip cost is increased.
Therefore, for example, it is conceivable to form a process monitor cell (PMC) in the LSI chip. When the PMC is built in the LSI chip, the number of pads is slightly increased. However, as shown in FIG. 6, the number of LSI chips is greatly increased as in the case where the process monitor chip 102 is provided separately from the LSI chip 100. There is no decrease. Further, it can be arranged uniformly in the wafer surface.

By the way, in general, an LSI chip is automatically created by using an automatic placement / wiring tool that can perform cell placement and wiring, so that a process monitor is built in an LSI chip. There is a method of creating and arranging a process monitor as one process monitor cell (hereinafter referred to as “PMC”). In this case, in order to prevent a short circuit between the metal used in the cell automatically placed by the automatic placement / wiring tool and the automatically routed metal, it is necessary to provide a cover for the metal block so that the wiring does not enter the cell. There is. For example, when up to three layers of metal are used in the PMC, by providing a cover in the PMC that blocks up to three layers of metal, the automatic wiring cannot pass through the upper part of the PMC unless it is more than four layers of metal. That is, as the number of metal layers used in the PMC increases, the number of metal layers that cannot pass over the PMC increases.
FIG. 7 is a diagram showing the overall configuration of a conventional LSI chip.
In this case, a large number of I / O cells 11 and PADs 12 are arranged on the outer periphery of the LSI chip 110. Inside the I / O cell 11, a plurality of LSI circuits 13, 13... And one PMC 2 are arranged. The LSI circuit 13 and the PMC 2 are connected to the I / O cell 11 by wiring. In this case, since the PMC 2 has a cover for blocking the upper wiring, the LSI circuit 13 and the I / O cell 11 are connected. Among the wirings connecting the two, the wiring 14 indicated by a one-dot chain line is routed so as to bypass the PMC 2.
In addition, as a prior art document, there is a semiconductor characteristic evaluation apparatus that has a plurality of measurement units arranged in a grid pattern on a chip, and electrically evaluates the elements of each unit by selecting the unit (Patent Document 1). ).
Japanese Patent No. 3592316

However, as shown in FIG. 7, when a part of the wiring connecting the LSI circuit 13 and the I / O cell 11 is routed so as to bypass the PMC 2, the wiring restrictions are remarkably increased. There is a possibility that the cell arrangement by the tool and the wiring itself may not converge.
Therefore, the present invention has been made in view of such points, and provides an LSI chip that can perform automatic wiring using an automatic placement / wiring tool even when a PMC is placed in the LSI chip. For the purpose.

In order to achieve the above object, an invention according to claim 1 is a semiconductor integrated chip including input / output cells and pads, and includes a semiconductor integrated circuit and a process monitor for measuring the capacitance of metal wiring. The metal wiring is wired between a first cell having a process monitor circuit of the process monitor and a second cell having a termination portion for designating a termination of the metal wiring, and the first cell and the second cell A cell having a terminal for designating a passing point of the metal wiring is arranged between and.
According to a second aspect of the present invention, in the semiconductor integrated chip according to the first aspect, the process monitor is uniformly arranged in the semiconductor chip .
According to a third aspect of the present invention, there is provided a semiconductor integrated device comprising input / output cells and pads, comprising a semiconductor integrated circuit and a process monitor for measuring the capacitance of the metal wiring, The second cell is wired between a first cell having a process monitor circuit of the process monitor and a second cell having a termination portion for designating a termination of the metal wiring, and the second cell is an empty cell. Features .

According to the present invention, wiring by an automatic placement / wiring tool is possible even when a process monitor is incorporated in a semiconductor integrated chip.
In addition , it is possible to create a wiring portion to be subjected to the capacity measurement of the process monitor using a placement / wiring tool.
In addition , it is possible to adjust the length of the wiring portion to be subjected to the capacity measurement of the process monitor using the placement / wiring tool.

Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a diagram showing the overall configuration of an LSI chip according to an embodiment of the present invention.
A large number of I / O cells (input / output cells) 11 and a PAD 12 are arranged on the outer periphery of the LSI chip 1 shown in FIG. Inside the I / O cell 11, a plurality of LSI circuits 13, 13... And two process monitor cells (PMC) 2a, 2b constituting a process monitor are provided. The plurality of LSI circuits 13, 13... And the PMC (first cell) 2a and PMC (second cell) 2b constituting the process monitor are automatically arranged by an automatic arrangement / wiring tool. Further, in addition to the wiring 14 connecting the LSI circuits 13 and 13 and the wiring 14 connecting the I / O cell 11 and the LSI circuit 13, the metal wiring 3 used for the capacity measurement in the process monitor is used by the automatic placement / wiring tool. Wiring is done.
In this way, the wirings 14 for connecting the LSI circuits 13 or between the LSI circuits 13 and the I / O cells 11 can straddle the metal wiring 3 between the PMC 2a and the PMC 2b. That is, in the conventional LSI chip 110 shown in FIG. 7, the metal wiring used for the capacitance measurement in the process monitor is formed in the PMC 2, so that the size of the PMC 2 increases and the LSI circuit 13 and the I / O It was necessary to route a part of the wiring connecting the cell 11 so as to bypass the PMC 2. On the other hand, in the LSI chip of the present embodiment, the metal wiring 3 used for capacitance measurement in the process monitor is wired by an automatic placement / wiring tool, so that the PMCs 2a and 2b constituting the process monitor can be reduced in size. In addition, the wiring 14 connecting the LSI circuit 13 and the I / O cell 11 can be wired so as to straddle the metal wiring 3. Thereby, even when a process monitor is incorporated in a semiconductor integrated chip, wiring by an automatic placement / wiring tool becomes possible.
Here, a configuration example of a process monitor for measuring metal wiring capacitance will be described. In the present embodiment, a known CBCM (Charge-Based Capacitance Measurement) method for evaluating the capacitance of an element will be described as an example.

FIG. 2 is a diagram showing a configuration example of the process monitor.
The process monitor shown in FIG. 2 includes two PMCs (process monitor cells) 2a and 2b. The PMC 2a includes two Pch transistors MP1 and MP2 and two Nch transistors MN1 and MN2.
The Pch transistor MP1 has a substrate connected to the power supply VCC, a source connected to the power supply VDD1, a drain connected to the node Q1, and a gate connected to the input terminal GP. The Pch transistor MP2 has a substrate connected to the power supply VCC, a source connected to the power supply VDD2, a drain connected to the node Q2, and a gate connected to the input terminal GP. The Nch transistor MN1 has a substrate connected to GND, a source connected to GND, a drain connected to the node Q1, and a gate connected to the input terminal GN. The Nch transistor MN2 has a substrate connected to GND, a source connected to GND, a drain connected to the node Q2, and a gate connected to the input terminal GN.
The power supply VCC, the power supply VDD1, and the power supply VDD2 are power supplies having the same potential. Node Q1 is connected to metal R1. Node Q2 is connected to metal R2. The metal R1 and the metal R2 have the same shape and configuration, and the capacitance between the metal R1 and GND and the capacitance between the metal R2 and GND are both Cref.
The metal R2 of the PMC 2a is connected to the metal R3 outside the PMC 2a. The metal R3 is a part that is automatically wired by the tool, and is a part that is subjected to capacity evaluation by the CBCM method. The capacity of the evaluation target portion is Cmet between R3 and GND.
PMC 2b is a cell for determining the end E of the automatic wiring and does not contain an actual element. This is because it is necessary to designate two points on the circuit in order to perform wiring by the automatic placement / wiring tool. Therefore, by arranging PMC2b, which is an empty cell having a terminal E, on the circuit, the metal of PMC2a It is possible to automatically wire between R2 and the end E of the PMC 2b. The PMC 2a is desirably made as one cell.
In addition, since the automatic wiring portion can be designated as a specific metal, for example, the metal R3 can be only a four-layer metal. In that case, the connection position of the metal R2 with the metal R3 may be a four-layer metal, and the shape of the metal R1 may be matched to the metal R2.

The capacitance Cmet of the metal R3 can be evaluated by inputting the signals GP and GN having the waveform as shown in FIG. 3 to the process monitor having the configuration as shown in FIG.
In the period T0 shown in FIG. 3, since the Pch transistors MP1 and MP2 are turned off and the Nch transistors MN1 and MN2 are turned on, the nodes Q1 and Q2 are discharged. Along with this, the metals R1, R2, and R3 are also discharged.
Further, since the Nch transistors MN1 and MN2 are turned off in the period T1, the discharge ends. In the period T2, the Pch transistors MP1 and MP2 are turned on and the Nch transistors MN1 and MN2 are kept off, so that the nodes Q1 and Q2 are charged. Along with this, the metals R1, R2, and R3 are also charged. That is, the capacitor Cref of the metal R1, the capacitor Cref of the metal R2, and the capacitor Cmet of the metal R3 are charged.
In the period T3, the charging ends because the Pch transistors MP1 and MP2 are turned off.
In the period T4, the Pch transistors MP1 and MP2 are kept OFF and the Nch transistors MN1 and MN2 are turned ON, so that the nodes Q1 and Q2 are discharged again. The cycle from the period T0 to T4 is continuously performed, the current flowing from the power supply VDD1 to the node Q1 and the current flowing from the power supply VDD2 to the node Q2 are measured, and the difference is obtained to subtract the common capacitance Cref. The capacity Cmet can be evaluated.
As described above, in this embodiment, by automatically placing / wiring the PMC with a tool, it is possible to create a process monitor without degrading the performance of the LSI circuit by avoiding the detour of the wiring of the LSI chip, It is also possible to arrange the process monitor uniformly in the wafer.

FIG. 4 is a diagram showing an overall configuration of an LSI chip according to the second embodiment of the present invention. In FIG. 4, the LSI circuit and the wiring that connects the LSI circuit and the I / O cell are omitted, and only the PMC and the wiring connected thereto are shown.
In the LSI chip shown in FIG. 4, a method for extending the wiring length between PMCs corresponding to R3 in FIG. 2 is shown. In addition to the PMC 2a and PMC 2b described above, PMC2c and PMC2d are arranged.
PMC2c and PMC2d have terminals M1 and M2, respectively, and have no elements inside like PMC2b.
By setting these PMCs 2c and 2d on the circuit and arranging them in the LSI chip, wiring is performed from the metal R2 (see FIG. 2) of the PMC 2a to the terminal M1 on the PMC 2c, and from this terminal M1 to the terminal M2 on the PMC 2d. And is further wired from the terminal M2 to the terminal E on the PMC 2b. As described above, when the length of the wiring 3 created by the automatic placement / wiring tool is increased, the capacitance Cmet can be increased.

1 is a diagram showing an overall configuration of an LSI chip according to a first embodiment of the present invention. It is the figure which showed the structural example of the process monitor. It is the figure which showed the signal waveform input into a process monitor. It is the figure which showed the whole structure of the LSI chip which concerns on 2nd Embodiment of this invention. It is the figure which showed the LSI chip and scribe line on a wafer. It is the figure which showed the case where the LSI chip and the process monitor chip are mixedly mounted on the wafer. It is the figure which showed the whole structure of the conventional LSI chip.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... LSI chip, 11 ... I / O cell, 110 ... LSI chip, 12 ... PAD, 13 ... LSI circuit, 2 ... PMC, 3 ... Wiring

Claims (3)

A semiconductor integrated chip comprising input / output cells and pads,
A semiconductor integrated circuit and a process monitor for measuring the capacitance of the metal wiring;
The metal wiring is wired between a first cell having a process monitor circuit of the process monitor and a second cell having a termination portion for designating a termination of the metal wiring,
A semiconductor integrated chip, wherein a cell having a terminal for designating a passing point of the metal wiring is disposed between the first cell and the second cell . 2. The semiconductor integrated chip according to claim 1, wherein the process monitor is uniformly arranged in the semiconductor chip. A semiconductor integrated device comprising an input / output cell and a pad,
  A semiconductor integrated circuit and a process monitor for measuring the capacitance of the metal wiring;
  The metal wiring is wired between a first cell having a process monitor circuit of the process monitor and a second cell having a termination portion for designating a termination of the metal wiring,
  The semiconductor integrated device, wherein the second cell is an empty cell.

Images