CN213042667U

CN213042667U - Chip fuse device

Info

Publication number: CN213042667U
Application number: CN202022301602.4U
Authority: CN
Inventors: 张建伟
Original assignee: Shanghai Mingsi Microelectronics Co ltd
Current assignee: Shanghai Mingsi Microelectronics Co ltd
Priority date: 2020-10-16
Filing date: 2020-10-16
Publication date: 2021-04-23
Anticipated expiration: 2030-10-16

Abstract

The utility model provides a chip fuse device contains: the test circuit comprises an EEPROM, a test code reading circuit, a test code comparing circuit, a metal layer selecting circuit and a test enabling output circuit. Use the beneficial effects of the utility model are that, can replace the traditional fuse circuit that needs placed in the chip cutting way, can effectively reduce the width of chip cutting way, promote the chip output on a slice wafer, also can be when the chip in use through the production test goes wrong, through once simple focused ion beam analysis (FIB) can reentrant test pattern, the convenience is fixed a position the problem.

Description

Chip fuse device

Technical Field

The utility model belongs to the technical field of integrated circuit.

Background

Typically, there will be several chips on an integrated circuit wafer. After the wafer is produced, each chip should enter a test mode to facilitate the production test of the chip, and after the production test is passed, the wafer is scribed, and the chip passing the production test is picked up and packaged.

In order to enable each chip to be successfully subjected to production test after the wafer is produced, a fuse is used when designing the chip. In general, when the fuse is in a connection state, the test enable signal value is 1, and the chip can enter a test mode for production test; when the fuse is in an open state, the test enable signal is 0, and the chip cannot enter the test mode. Specifically, in the semiconductor production test process, when the wafer is just produced, the fuse of each chip is kept in a connection state, and the chip can enter a test mode to perform production test. And after the production test is passed, the wafer is diced, the fuse wire is cut off in the dicing process, and the chip cut by the fuse wire can not enter a test mode.

The fuse wire of each chip needs to be placed in a cutting channel on the periphery of the chip, so that the size of the cutting channel cannot be too small, otherwise, the work of the fuse wire is influenced, and the production test flow of the chip is influenced. As the feature size of a chip becomes smaller, the area of the chip becomes smaller, which means that more chips can be produced on a wafer of the same area. However, the width of the scribe line cannot be reduced with the reduction of the chip area due to the need of placing fuses, which affects the chip yield on a wafer. Especially for the laser scribing scheme, a fuse cannot be placed in the cutting path, and if the traditional fuse scheme is adopted, the scribing scheme selection of a plurality of chips is limited, so that the overall cost and area of the chips are influenced.

Another disadvantage of the above fuse scheme is that once the fuse is cut, the chip can no longer enter test mode. When a problem occurs in use of a chip that passes production testing, the chip cannot enter a test mode, and the problem is difficult to locate.

Disclosure of Invention

In order to solve the above two problems, the present invention provides a chip fuse device, which is characterized in that, as shown in fig. 1, the device comprises an EEPROM, a test code reading circuit, a test code comparing circuit, a metal layer selecting circuit and a test enable output circuit.

The EEPROM is characterized in that an input signal of the EEPROM is an ee _ rd _ en signal and is connected to the output of the test code reading circuit, and an output signal of the EEPROM is ee _ data and is connected to the input end of the test code reading circuit. The EEPROM has the functions of storing test codes, still storing the values of the stored test codes when the chip is powered on next time, and reading the stored test codes from the chip when the chip is powered on next time.

The test code reading circuit is characterized in that the test code reading circuit internally comprises a control state machine and a control logic, an input signal of the test code reading circuit is ee _ data, and the test code reading circuit is connected to an output signal ee _ data of the EEPROM; the test code reading circuit comprises 1 output signal rd _ out connected to the input end of the test code comparison circuit; the test code reading circuit comprises 1 input signal ee _ rd _ en connected to the EEPROM, and the output signal ee _ rd _ en is 1. The test code reading circuit has the function that after the chip is powered on, the control logic can generate a read control signal ee _ rd _ en of the EEPROM under the control of the control state machine, automatically reads the test codes stored in the EEPROM, gives the read test codes to an rd _ out signal and sends the rd _ out signal to the test code comparison circuit.

The test code comparison circuit is characterized by comprising a comparator, wherein the width of the comparator is the same as that of a test code, the input of the test code comparison circuit is rd _ out, and the test code comparison circuit is connected to an output rd _ out signal of the test code reading circuit; the output of the test code comparison circuit is test _ en1, the bit width is 1bit, and the test code comparison circuit is connected to the test enable output circuit. The function of the test code comparison circuit is to receive the output data rd _ out of the test code reading circuit, compare the value of rd _ out with the specific code value preset by the chip, and then send the comparison result test _ en1 to the test enable output circuit, where a test _ en1 is 1 to indicate that rd _ out and the specific code preset by the chip are equal, and a test _ en1 is 0 to indicate that rd _ out and the specific code preset by the chip are not equal.

The Metal layer selection circuit is characterized in that the Metal layer selection circuit is positioned at the top layer Metal and comprises a buffer, an input signal of the Metal layer selection circuit is Metal _ in, VDD and VSS are respectively arranged at two sides of the Metal _ in, and an output signal of the Metal layer selection circuit is test _ en2 and is connected to an input end of the test enabling output circuit. The metal layer selection circuit has the functions that when metal _ in is connected with VDD, test _ en2 outputs 1, when metal _ in is connected with VSS, test _ en2 outputs 0, when a chip leaves a factory, metal _ in is connected with VSS, when the chip is in use, the connection between input and VSS can be cut off through FIB, and metal _ in can be connected with VDD.

The test enabling output circuit is characterized by comprising an OR gate, wherein the input signal of the test enabling circuit has two paths, one path is test _ en1 and is connected to the test code comparison circuit, and the other path is test _ en2 and is connected to the metal layer selection circuit; the output signal of the test enabling output circuit is test _ en, namely the output signal of the device. The test enabling output circuit has the function of performing logical OR operation on the output signal test _ en1 of the test code comparison circuit and the output signal test _ en2 of the metal layer selection circuit, wherein the output signal test _ en after the logical OR operation is the output signal of the device. It can be seen that when either test _ en1 or test _ en2 is 1, the test _ en signal is 1, and the chip can enter the test mode.

Use the beneficial effects of the utility model are that, avoid using the fuse that needs to place in the cutting street, can effectively reduce the width of chip cutting street. Meanwhile, the device also comprises a circuit capable of entering the test mode, when the chip passing the production test has problems in use, the device can enable the chip passing the production test to enter the test mode again through a simple focused ion beam analysis (FIB), and the problems are conveniently positioned. The device can replace the original fuse device, reduce the width of the chip cutting channel and provide a mode for the chip to enter the test mode again.

Drawings

Fig. 1 is a structural diagram of a chip fuse device according to the present invention;

FIG. 2 is a schematic diagram of the EEPROM of the present invention;

FIG. 3 is a schematic diagram of the code reading circuit of the present invention;

FIG. 4 is a schematic diagram of a code comparison circuit according to the present invention;

FIG. 5 is a schematic diagram of a metal layer selection circuit according to the present invention;

fig. 6 is a schematic diagram of the test enable output circuit of the present invention.

Detailed Description

Preferred embodiments of the present apparatus will be described in detail below with reference to the accompanying drawings.

The utility model provides a chip fuse device, its characterized in that, as shown in fig. 1, including EEPROM, test code reading circuit, test code comparison circuit, metal level selection circuit and test enable output circuit.

As shown in fig. 2, the EEPROM has an input of ee _ rd _ en signal and is connected to an output of the test code reading circuit, and an output signal of the EEPROM is ee _ data and is connected to an input terminal of the test code reading circuit. The EEPROM has the functions of storing test codes, still storing the values of the stored test codes when the chip is powered on next time, and reading the stored test codes from the chip when the chip is powered on next time.

As shown in fig. 3, the test code reading circuit is characterized in that the test code reading circuit internally comprises a control state machine and a control logic, an input signal ee _ data of the test code reading circuit is connected to an output signal ee _ data of the EEPROM; the test code reading circuit comprises 1 output signal rd _ out connected to the input end of the test code comparison circuit; the test code reading circuit comprises 1 input signal ee _ rd _ en connected to the EEPROM, and the output signal ee _ rd _ en is 1. The test code reading circuit has the function that after the chip is powered on, the control logic can generate a read control signal ee _ rd _ en of the EEPROM under the control of the control state machine, automatically reads the test codes stored in the EEPROM, gives the read test codes to an rd _ out signal and sends the rd _ out signal to the test code comparison circuit.

As shown in fig. 4, the test code comparing circuit is characterized in that the test code comparing circuit internally comprises a comparator, the width of the comparator is the same as that of the test code, the input of the test code comparing circuit is rd _ out, and the test code comparing circuit is connected to the output rd _ out signal of the test code reading circuit; the output of the test code comparison circuit is test _ en1, the bit width is 1bit, and the test code comparison circuit is connected to the test enable output circuit. The function of the test code comparison circuit is to receive the output data rd _ out of the test code reading circuit, compare the value of rd _ out with the specific code value preset by the chip, and then send the comparison result test _ en1 to the test enable output circuit, where a test _ en1 is 1 to indicate that rd _ out and the specific code preset by the chip are equal, and a test _ en1 is 0 to indicate that rd _ out and the specific code preset by the chip are not equal.

As shown in fig. 5, the Metal layer selection circuit is located in the top Metal layer, and includes a buffer, the input signal of the Metal layer selection circuit is Metal _ in, VDD and VSS are respectively disposed at two sides of Metal _ in, and the output signal of the Metal layer selection circuit is test _ en2, which is connected to the input terminal of the test enable output circuit. The metal layer selection circuit has the functions that when metal _ in is connected with VDD, test _ en2 outputs 1, when metal _ in is connected with VSS, test _ en2 outputs 0, when a chip leaves a factory, metal _ in is connected with VSS, when the chip is in use, the connection between input and VSS can be cut off through FIB, and metal _ in can be connected with VDD.

As shown in fig. 6, the test enable output circuit includes an or gate, and the input signal of the test enable circuit has two paths, one path is test _ en1 and is connected to the test code comparing circuit, and the other path is test _ en2 and is connected to the metal layer selecting circuit; the output signal of the test enabling output circuit is test _ en, namely the output signal of the device. The test enabling output circuit has the function of performing logical OR operation on the output signal test _ en1 of the test code comparison circuit and the output signal test _ en2 of the metal layer selection circuit, wherein the output signal test _ en after the logical OR operation is the output signal of the device. It can be seen that when either test _ en1 or test _ en2 is 1, the test _ en signal is 1, and the chip can enter the test mode.

The device can replace the original fuse device, reduce the width of the chip cutting channel and provide a mode for the chip to enter the test mode again.

Although the present invention has been described in detail with respect to the preferred embodiments, various modifications and alterations will become apparent to those skilled in the art upon reading the foregoing description. The above description and drawings are only examples of the practice of the invention, and it should be understood that the above description should not be taken as limiting the invention.

Claims

1. A chip fuse apparatus, comprising: the test circuit comprises an EEPROM, a test code reading circuit, a test code comparing circuit, a metal layer selecting circuit and a test enabling output circuit; the input of the EEPROM is an ee _ rd _ en signal, the EEPROM is connected to the output of the test code reading circuit, the output signal of the EEPROM is ee _ data, the EEPROM is connected to the input end of the test code reading circuit, the EEPROM has the function of storing test codes, the values of the stored test codes can be still stored when the chip is powered on next time, and the stored test codes can be read from the EEPROM when the chip is powered on next time; the test code reading circuit internally comprises a control state machine and a control logic, an input signal ee _ data of the test code reading circuit is connected to an output signal ee _ data of the EEPROM, the test code reading circuit comprises 1 output signal rd _ out which is connected to an input end of the test code comparing circuit, and the test code reading circuit also comprises 1 output signal ee _ rd _ en which is connected to an input signal ee _ rd _ en of the EEPROM; the test code comparison circuit internally comprises a comparator, the width of the comparator is the same as that of the test code, the input of the test code comparison circuit is rd _ out, the test code comparison circuit is connected to an output rd _ out signal of the test code reading circuit, the output of the test code comparison circuit is test _ en1, the bit width is 1bit, and the test code comparison circuit is connected to the test enabling output circuit; the Metal layer selection circuit is positioned in the top Metal and comprises a buffer, an input signal of the Metal layer selection circuit is Metal _ in, VDD and VSS are respectively arranged at two sides of the Metal _ in, and an output signal of the Metal layer selection circuit is test _ en2 and is connected to an input end of the test enable output circuit; the test enabling output circuit comprises an OR gate, the input signal of the test enabling circuit comprises two paths, one path is test _ en1 and is connected to the test code comparison circuit, the other path is test _ en2 and is connected to the metal layer selection circuit, and the output signal of the test enabling output circuit is test _ en which is the output signal of the device.