CN203708222U - Clock feedthrough compensation circuit of bootstrapped clock sampling switch - Google Patents
Clock feedthrough compensation circuit of bootstrapped clock sampling switch Download PDFInfo
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- CN203708222U CN203708222U CN201420024259.5U CN201420024259U CN203708222U CN 203708222 U CN203708222 U CN 203708222U CN 201420024259 U CN201420024259 U CN 201420024259U CN 203708222 U CN203708222 U CN 203708222U
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Abstract
The utility model provides a clock feedthrough compensation circuit of a bootstrapped clock sampling switch. A new pseudo switch is added to a sampling output node and the grid electrode of the new pseudo switch is biased to a clock output terminal of a complementary grid-voltage bootstrapping circuit, so that error amounts that are generated by coupling of the new pseudo switch and the original pseudo switch to the terminal Vout by the Cgd unit can be offset each other. According to the clock feedthrough compensation circuit, a group of pseudo switches in an off state are introduced. At the sampling holding state, the complementary input signals are respectively coupled to the Vout by a parasitic Cds capacitor; and because the input signals are complementary, the crosstalks generated by the Cds can offset each other. With the clock feedthrough compensation circuit, the influence on signal sampling by a clock feedthrough effect can be reduced; the linearity of field effect tube sampling can be improved; the harmonic distortion of the sampling circuit can be reduced; and the sampling speed and the sampling precision can be enhanced.
Description
Technical field
The utility model relates to a kind of circuit, relates in particular to a kind of clock feedthrough compensated circuit of the clock sampling switch of booting.
Background technology
At ADC(Analog to Digital Converter; A-D converter) in Circuits System; usually can use sampling hold circuit (sample and hold); its effect is to gather analog input voltage instantaneous value at a time; and analog to digital converter carry out the transition period keep output voltage constant, for analog-to-digital conversion.Switch closure when high level, input signal is followed in output, and when low level, switch disconnects, and keeps electric capacity to keep output voltage constant.
In actual circuit, the sampling error causing due to switching device parasitic capacitance and charge injection effect mainly comprises: 1. error 2. that what parasitic source drain capacitance caused the crosstalk error of crosstalking that clock feedthrough causes by grid leak parasitic capacitance of booting.
The error of crosstalking causing by grid leak parasitic capacitance for bootstrapping clock feedthrough, eliminates by Bootstrap switch the error of crosstalking conventionally, and the grid voltage of sampling switch and the grid voltage of pseudo-switch are all provided by Bootstrap switch; The limitation of the method is: the pseudo-switch of introducing is in maintenance phase process, and grid voltage is biased to Vin+Vdd, because Vin changes, so the grid voltage changing equally can be by parasitic Cgd capacitive coupling interference sample value.
Utility model content
Main purpose of the present utility model is to provide a kind of clock feedthrough compensated circuit of the clock sampling switch of booting, and can eliminate the error of crosstalking that bootstrapping clock feedthrough causes by grid leak parasitic capacitance, keeps the constant of sampled value.
Secondary objective of the present utility model is to provide a kind of clock feedthrough compensated circuit of the clock sampling switch of booting, and can eliminate the error of crosstalking that parasitic source drain capacitance causes.
In order to solve above-mentioned technical problem, the utility model provides a kind of clock feedthrough compensated circuit of the clock sampling switch of booting, and comprising:
The first sampling transistor M1, the grid of described the first sampling transistor M1 is connected with the output terminal of clock of the first grid voltage boostrap circuit I1, the source electrode of described the first sampling transistor M1 is connected with the first differential complement signals INP, and drain electrode the first output OUTP of described the first sampling transistor M1 connects;
The first pseudo-switching transistor M2, the grid of described the first pseudo-switching transistor M2 is connected with the output terminal of clock of the second grid voltage boostrap circuit I2;
First keeps capacitor C 1, and described first keeps one end of capacitor C 1 to be connected with described the first output OUTP; Described first keeps the other end of capacitor C 1 to be connected with GND;
The second sampling transistor M3, the grid of described the second sampling transistor M3 is connected with the output terminal of clock of the 3rd Bootstrap circuit I 3, the source electrode of described the second sampling transistor M3 is connected with the second differential complement signals INN, and described the second sampling transistor M3 drain electrode is connected with the second output OUTN;
The second pseudo-switching transistor M4, the grid of described the second pseudo-switching transistor M4 is connected with the output terminal of clock of the 4th Bootstrap circuit I 4;
Second keeps capacitor C 2, and described second keeps one end of capacitor C 2 to be connected with described the first output OUTP; Described second keeps the other end of capacitor C 2 to be connected with GND;
The input of described the first grid voltage boostrap circuit I1, the second grid voltage boostrap circuit I2 is connected with described the first differential complement signals INP respectively; The input of described the 3rd Bootstrap circuit I 3, the 4th Bootstrap circuit I 4 is connected with described the second differential complement signals INN respectively;
The first input end of clock of described the first grid voltage boostrap circuit I1, the 3rd Bootstrap circuit I 3 is connected with the first complementary sampling clock PHY1, and the second clock input of the first grid voltage boostrap circuit I1, the 3rd Bootstrap circuit I 3 is connected with the second complementary sampling clock PHY2; The first input end of clock of described the second grid voltage boostrap circuit I2, the 4th Bootstrap circuit I 4 is connected with the second complementary sampling clock PHY2, and the second clock input of the second grid voltage boostrap circuit I2, the 4th Bootstrap circuit I 4 is connected with the first complementary sampling clock PHY1;
It is characterized in that: also comprise the 3rd pseudo-switching transistor M5 and the 4th pseudo-switching transistor M6;
The source electrode of described the 3rd pseudo-switching transistor M5 is connected with drain electrode, the first output OUTP of described the first sampling transistor M1, the grid of described the 3rd pseudo-switching transistor M5 is connected with the output terminal of clock of described the 4th Bootstrap circuit I 4, and the drain electrode of described the 3rd pseudo-switching transistor M5 is connected with the source electrode of described the first pseudo-switching transistor M2;
The source electrode of described the 4th pseudo-switching transistor M6 is connected with drain electrode, the second output OUTN of described the second sampling transistor M3, the grid of described the 4th pseudo-switching transistor M6 is connected with the output terminal of clock of described the second grid voltage boostrap circuit I2, and the drain electrode of described the 4th pseudo-switching transistor M6 is connected with the source electrode of described the second pseudo-switching transistor M4;
As preferably: also comprise the 5th pseudo-switching transistor M7 and the 6th pseudo-switching transistor M8;
The source electrode of described the 5th pseudo-switching transistor M7 is connected with drain electrode, the second output OUTN of described the second sampling transistor M2; The drain electrode of described the 5th pseudo-switching transistor M7 is connected with source electrode, the first difference complementary input signal INP of described the first sampling transistor M1;
The drain electrode of described the 6th pseudo-switching transistor M8 is connected with drain electrode, the first output OUTP of described the first sampling transistor M1; The source electrode of described the 6th pseudo-switching transistor M8 is connected with source electrode, the first difference complementary input signal INP of described the second sampling transistor M3;
The grid of described the 5th pseudo-switching transistor M7 is connected with grid, the GND end of described the 6th pseudo-switching transistor M8.
As preferably: described the 5th pseudo-switching transistor M7 and the 6th pseudo-switching transistor M8 state in turn-off always.
As preferably: described sampling transistor M1, M3, pseudo-switching transistor M2, M4, M5, M6, M7, M8 are nmos pass transistor.
As preferably: described Bootstrap circuit comprises:
Main switch M9 is pmos transistor; The drain electrode of described main switch M9 is connected with output terminal of clock;
The first auxiliary switch M10 is pmos transistor; The source electrode of described the first auxiliary switch M10 is connected with the source electrode of described main switch M9; The grid of described the first auxiliary switch M10 is connected with output terminal of clock; The drain electrode of described the first auxiliary switch is connected with input signal SUP;
The first complementary switch M11 and M12, described M11 is nmos transistor, described M12 is pmos transistor; The drain electrode of described M11 is connected with the source electrode of described M12; The source electrode of described M11 is connected with the drain electrode of described M12; The grid of described M11 is connected with the first complementary sampling clock PHY1; The grid of described M12 is connected with the second complementary sampling clock PHY2;
The second complementary switch M13 and M14, described M13 is pmos transistor, described M14 is nmos transistor; The drain electrode of described M13 is connected with the source electrode of described M14; The source electrode of described M13 is connected with the drain electrode of described M14, input signal IN; The grid of described M13 is connected with the grid of described M12, the second complementary sampling clock PHY2; The grid of described M14 is connected with the first complementary sampling clock PHY1;
The second auxiliary switch M15, described the second auxiliary switch M15 is nmos transistor; The grid of described the second auxiliary switch M15 is connected with the second complementary sampling clock PHY2, and the source electrode of described the second auxiliary switch is connected with GND;
The 3rd auxiliary switch M16, described the 3rd auxiliary switch M16 is nmos transistor; The source electrode of described the 3rd auxiliary switch M16 is connected with GND, and the grid of described the 3rd auxiliary switch is connected with the second complementary sampling clock PHY2;
Bootstrap capacitor C3, one end of described bootstrap capacitor C3 is connected with the drain electrode of described the second auxiliary switch M15, and the other end of described bootstrap capacitor C3 is connected with the source electrode of described the first auxiliary switch M10.
As preferably, described Bootstrap circuit also comprises:
The first protection switch M17, described the first protection switch M17 is pmos transistor; The grid of described the first protection switch M17 is connected with the first complementary sampling clock PHY1, and the source electrode of described the first protection switch M17 is connected with input signal SUP, and the drain electrode of described the first protection switch M17 is connected with the grid of described main switch M9;
The second protection switch M18, described the second protection switch M18 is nmos transistor; The grid of described the second protection switch M18 is connected with input signal SUP, and the drain electrode of described the second protection switch M18 is connected with the drain electrode of described main switch M9; The source electrode of described the second protection switch M18 is connected with the drain electrode of described the 3rd auxiliary switch M16.
The beneficial effects of the utility model:
1. by adding again the 3rd pseudo-switching transistor M5 and the 4th pseudo-switching transistor M6 at sampling output node, the grid of described the 3rd pseudo-switching transistor M5 and the 4th pseudo-switching transistor M6 is biased in respectively complementary boostrap circuit I2 and the output terminal of clock of I4, obtain the margin of error and cancel out each other so be coupled to output by Cgd, thereby keep sampled value constant.
2. by introducing one group of the 5th pseudo-switching transistor M7 and the 6th pseudo-switching transistor M8 in off state, at sampling switch in the maintenance stage be, complementary input signal is to being respectively capacitively coupled to sampling output by parasitic Cds, because input signal is complementary signal, therefore crosstalking of its generation can be cancelled out each other.
Brief description of the drawings
Fig. 1 is the circuit diagram of the utility model preferred embodiment;
Fig. 2 is the circuit diagram of Bootstrap circuit in the utility model preferred embodiment.
Embodiment
Below in conjunction with the accompanying drawings and embodiments the utility model is described further.
With reference to figure 1, a kind of clock feedthrough compensated circuit of the clock sampling switch of booting, comprising:
The first sampling transistor M1, the grid of described the first sampling transistor M1 is connected with the output terminal of clock of the first grid voltage boostrap circuit I1, the source electrode of described the first sampling transistor M1 is connected with the first differential complement signals INP, described the first sampling transistor M1 drain first output OUTP connect;
The first pseudo-switching transistor M2, the grid of described the first pseudo-switching transistor M2 is connected with the output terminal of clock of the second grid voltage boostrap circuit I2;
First keeps capacitor C 1, and described first keeps one end of capacitor C 1 to be connected with described the first output OUTP; Described first keeps the other end of capacitor C 1 to be connected with GND;
The second sampling transistor M3, the grid of described the second sampling transistor M3 is connected with the output terminal of clock of the 3rd Bootstrap circuit I 3, the source electrode of described the second sampling transistor M3 is connected with the second differential complement signals INN, and described the second sampling transistor M3 drain electrode is connected with the second output OUTN;
The second pseudo-switching transistor M4, the grid of described the second pseudo-switching transistor M4 is connected with the output terminal of clock of the 4th Bootstrap circuit I 4;
Second keeps capacitor C 2, and described second keeps one end of capacitor C 2 to be connected with described the first output OUTP; Described second keeps the other end of capacitor C 2 to be connected with GND;
The input of described the first grid voltage boostrap circuit I1, the second grid voltage boostrap circuit I2 is connected with described the first differential complement signals INP respectively; The input of described the 3rd Bootstrap circuit I 3, the 4th Bootstrap circuit I 4 is connected with described the second differential complement signals INN respectively;
The first input end of clock of described the first grid voltage boostrap circuit I1, the 3rd Bootstrap circuit I 3 is connected with the first complementary sampling clock PHY1, and the second clock input of the first grid voltage boostrap circuit I1, the 3rd Bootstrap circuit I 3 is connected with the second complementary sampling clock PHY2; The first input end of clock of described the second grid voltage boostrap circuit I2, the 4th Bootstrap circuit I 4 is connected with the second complementary sampling clock PHY2, and the second clock input of the second grid voltage boostrap circuit I2, the 4th Bootstrap circuit I 4 is connected with the first complementary sampling clock PHY1;
Also comprise the 3rd pseudo-switching transistor M5 and the 4th pseudo-switching transistor M6;
The source electrode of described the 3rd pseudo-switching transistor M5 is connected with drain electrode, the first output OUTP of described the first sampling transistor M1, the grid of described the 3rd pseudo-switching transistor M5 is connected with the output terminal of clock of described the 4th Bootstrap circuit I 4, and the drain electrode of described the 3rd pseudo-switching transistor M5 is connected with the source electrode of described the first pseudo-switching transistor;
The source electrode of described the 4th pseudo-switching transistor M6 is connected with drain electrode, the second output OUTN of described the second sampling transistor M3, the grid of described the 4th pseudo-switching transistor M6 is connected with the output terminal of clock of described the second grid voltage boostrap circuit I2, and the drain electrode of described the 4th pseudo-switching transistor M6 is connected with the source electrode of described the second pseudo-switching transistor M4;
Be switched to the moment in maintenance stage from sample phase at the first sampling transistor M1, because the grid of the first sampling transistor M1 and the first pseudo-switching transistor M2 is biased in respectively Bootstrap circuit I 1, the I2 of input clock complementation, so the margin of error that described the first sampling transistor M1 introduces by parasitic Cgd capacitive coupling can be offset by the first pseudo-switching transistor M2.
Be switched to the moment in maintenance stage from sample phase at the second sampling transistor M3, because the grid of the second sampling transistor M3 and the second pseudo-switching transistor M4 is biased in respectively Bootstrap circuit I 3, the I4 of input clock complementation, so the margin of error that described the second sampling transistor M3 introduces by parasitic Cgd capacitive coupling can be offset by the second pseudo-switching transistor M4.
In the sampling maintenance stage, for the first pseudo-switching transistor M2, its grid voltage is the clock output voltage V inp+Vdd of the second grid voltage boostrap circuit, because Vinp changes, so the first pseudo-switching transistor M2 introduces the new margin of error by parasitic Cgd capacitive coupling; For the 3rd pseudo-switching transistor M5, its grid voltage is the clock output voltage V inn+Vdd of the 4th Bootstrap circuit.Because Vinn and Vinp are complementary differential input signals, thus the margin of error that the first pseudo-switching transistor M2 and the 3rd pseudo-switching transistor M5 are coupled on Vout by Cgd will cancel each other, thereby keep sampled value constant.
For the second pseudo-switching transistor M4, its grid voltage is the clock output voltage V inp+Vdd of the 4th Bootstrap circuit, because Vinp changes, so the second pseudo-switching transistor M4 introduces the new margin of error by parasitic Cgd capacitive coupling; For the 4th pseudo-switching transistor M6, its grid voltage is the clock output voltage V inn+Vdd of the second grid voltage boostrap circuit.Because Vinn and Vinp are complementary differential input signals, thus the margin of error that the second pseudo-switching transistor M4 and the 4th pseudo-switching transistor M6 are coupled on Vout by Cgd will cancel each other, thereby keep sampled value constant.
In the present embodiment, a kind of clock feedthrough compensated circuit of the clock sampling switch of booting also comprises:
The 5th pseudo-switching transistor M7 in off-state and always the 6th pseudo-switching transistor M8 in off-state always;
The source electrode of described the 5th pseudo-switching transistor M7 is connected with drain electrode, the second output OUTN of described the second sampling transistor M2; The drain electrode of described the 5th pseudo-switching transistor M7 is connected with source electrode, the first difference complementary input signal INP of described the first sampling transistor M1;
The drain electrode of described the 6th pseudo-switching transistor M8 is connected with drain electrode, the first output OUTP of described the first sampling transistor M1; The source electrode of described the 6th pseudo-switching transistor M8 is connected with source electrode, the first difference complementary input signal INP of described the second sampling transistor M3;
The grid of described the 5th pseudo-switching transistor M7 is connected with grid, the GND end of described the 6th pseudo-switching transistor M8.
In the sampling maintenance stage, Vinp and Vinn sample output to the first sampling transistor M1 and the parasitic Cds capacitive coupling of the second sampling transistor M3 respectively, because Vinp and Vinn are complementary signal, and therefore the crosstalking and can cancel out each other of generation.
Above-mentioned sampling transistor M1, M3, pseudo-switching transistor M2, M4, M5, M6, M7, M8 are nmos pass transistor.
With reference to figure 2, in the present embodiment, described Bootstrap circuit comprises
Main switch M9 is pmos transistor; The drain electrode of described main switch M9 is connected with output terminal of clock;
The first auxiliary switch M10 is pmos transistor; The source electrode of described the first auxiliary switch M10 is connected with the source electrode of described main switch M9; The grid of described the first auxiliary switch M10 is connected with output terminal of clock; The drain electrode of described the first auxiliary switch is connected with input signal SUP;
The first complementary switch M11 and M12, described M11 is nmos transistor, described M12 is pmos transistor; The drain electrode of described M11 is connected with the source electrode of described M12; The source electrode of described M11 is connected with the drain electrode of described M12; The grid of described M11 is connected with the first complementary sampling clock PHY1; The grid of described M12 is connected with the second complementary sampling clock PHY2;
The second complementary switch M13 and M14, described M13 is pmos transistor, described M14 is nmos transistor; The drain electrode of described M13 is connected with the source electrode of described M14; The source electrode of described M13 is connected with the drain electrode of described M14, input signal IN; The grid of described M13 is connected with the grid of described M12, the second complementary sampling clock PHY2; The grid of described M14 is connected with the first complementary sampling clock PHY1;
The second auxiliary switch M15, described the second auxiliary switch M15 is nmos transistor; The grid of described the second auxiliary switch M15 is connected with the second complementary sampling clock PHY2, and the source electrode of described the second auxiliary switch is connected with GND;
The 3rd auxiliary switch M16, described the 3rd auxiliary switch M16 is nmos transistor; The source electrode of described the 3rd auxiliary switch M16 is connected with GND, and the grid of described the 3rd auxiliary switch is connected with the second complementary sampling clock PHY2;
Bootstrap capacitor C3, one end of described bootstrap capacitor C3 is connected with the drain electrode of described the second auxiliary switch M15, and the other end of described bootstrap capacitor C3 is connected with the source electrode of described the first auxiliary switch M10.
Described Bootstrap circuit also comprises:
The first protection switch M17, described the first protection switch M17 is pmos transistor; The grid of described the first protection switch M17 is connected with the first complementary sampling clock PHY1, and the source electrode of described the first protection switch M17 is connected with input signal SUP, and the drain electrode of described the first protection switch M17 is connected with the grid of described main switch M9;
The second protection switch M18, described the second protection switch M18 is nmos transistor; The grid of described the second protection switch M18 is connected with input signal SUP, and the drain electrode of described the second protection switch M18 is connected with the drain electrode of described main switch M9; The source electrode of described the second protection switch M18 is connected with the drain electrode of described the 3rd auxiliary switch M16.
When PHY1 is low level, when PHY2 is high level, described the second complementary switch M13, M14 end disconnection, described main switch M9 cut-off disconnects, the first auxiliary switch M10, the second auxiliary switch M15, the 3rd auxiliary switch M16 conducting, bootstrap capacitor C3 is charged to Vdd level in advance, and output clock level is 0; When PHY1 is high level, when PHY2 is low level, described the second complementary switch M13, M14 conducting, described main switch M9 conducting, the first auxiliary switch M10, the second auxiliary switch M15, the 3rd auxiliary switch M16 cut-off disconnect, bootstrap capacitor C3 mono-end is received input Vin, and the other end is received output terminal of clock, and output clock level is Vin+Vdd;
The above, it is only the utility model preferred embodiment, therefore can not limit according to this scope that the utility model is implemented, the equivalence of doing according to the utility model the scope of the claims and description changes and modifies, and all should still belong in the scope that the utility model contains.
Claims (6)
1. the boot clock feedthrough compensated circuit of clock sampling switch, comprising:
The first sampling transistor M1, the grid of described the first sampling transistor M1 is connected with the output terminal of clock of the first grid voltage boostrap circuit I1, the source electrode of described the first sampling transistor M1 is connected with the first differential complement signals INP, and drain electrode the first output OUTP of described the first sampling transistor M1 connects;
The first pseudo-switching transistor M2, the grid of described the first pseudo-switching transistor M2 is connected with the output terminal of clock of the second grid voltage boostrap circuit I2;
First keeps capacitor C 1, and described first keeps one end of capacitor C 1 to be connected with described the first output OUTP; Described first keeps the other end of capacitor C 1 to be connected with GND;
The second sampling transistor M3, the grid of described the second sampling transistor M3 is connected with the output terminal of clock of the 3rd Bootstrap circuit I 3, the source electrode of described the second sampling transistor M3 is connected with the second differential complement signals INN, and described the second sampling transistor M3 drain electrode is connected with the second output OUTN;
The second pseudo-switching transistor M4, the grid of described the second pseudo-switching transistor M4 is connected with the output terminal of clock of the 4th Bootstrap circuit I 4;
Second keeps capacitor C 2, and described second keeps one end of capacitor C 2 to be connected with described the first output OUTP; Described second keeps the other end of capacitor C 2 to be connected with GND;
The input of described the first grid voltage boostrap circuit I1, the second grid voltage boostrap circuit I2 is connected with described the first differential complement signals INP respectively; The input of described the 3rd Bootstrap circuit I 3, the 4th Bootstrap circuit I 4 is connected with described the second differential complement signals INN respectively;
The first input end of clock of described the first grid voltage boostrap circuit I1, the 3rd Bootstrap circuit I 3 is connected with the first complementary sampling clock PHY1, and the second clock input of the first grid voltage boostrap circuit I1, the 3rd Bootstrap circuit I 3 is connected with the second complementary sampling clock PHY2; The first input end of clock of described the second grid voltage boostrap circuit I2, the 4th Bootstrap circuit I 4 is connected with the second complementary sampling clock PHY2, and the second clock input of the second grid voltage boostrap circuit I2, the 4th Bootstrap circuit I 4 is connected with the first complementary sampling clock PHY1;
It is characterized in that: also comprise the 3rd pseudo-switching transistor M5 and the 4th pseudo-switching transistor M6;
The source electrode of described the 3rd pseudo-switching transistor M5 is connected with drain electrode, the first output OUTP of described the first sampling transistor M1, the grid of described the 3rd pseudo-switching transistor M5 is connected with the output terminal of clock of described the 4th Bootstrap circuit I 4, and the drain electrode of described the 3rd pseudo-switching transistor M5 is connected with the source electrode of described the first pseudo-switching transistor M2;
The source electrode of described the 4th pseudo-switching transistor M6 is connected with drain electrode, the second output OUTN of described the second sampling transistor M3, the grid of described the 4th pseudo-switching transistor M6 is connected with the output terminal of clock of described the second grid voltage boostrap circuit I2, and the drain electrode of described the 4th pseudo-switching transistor M6 is connected with the source electrode of described the second pseudo-switching transistor M4.
2. the clock feedthrough compensated circuit of a kind of clock sampling switch of booting according to claim 1, is characterized in that: also comprise the 5th pseudo-switching transistor M7 and the 6th pseudo-switching transistor M8;
The source electrode of described the 5th pseudo-switching transistor M7 is connected with drain electrode, the second output OUTN of described the second sampling transistor M2; The drain electrode of described the 5th pseudo-switching transistor M7 is connected with source electrode, the first difference complementary input signal INP of described the first sampling transistor M1;
The drain electrode of described the 6th pseudo-switching transistor M8 is connected with drain electrode, the first output OUTP of described the first sampling transistor M1; The source electrode of described the 6th pseudo-switching transistor M8 is connected with source electrode, the first difference complementary input signal INP of described the second sampling transistor M3;
The grid of described the 5th pseudo-switching transistor M7 is connected with grid, the GND end of described the 6th pseudo-switching transistor M8.
3. the clock feedthrough compensated circuit of a kind of clock sampling switch of booting according to claim 2, is characterized in that: described the 5th pseudo-switching transistor M7 and the 6th pseudo-switching transistor M8 state in turn-off always.
4. the clock feedthrough compensated circuit of a kind of clock sampling switch of booting according to claim 1, is characterized in that: described sampling transistor M1, M3, pseudo-switching transistor M2, M4, M5, M6, M7, M8 are nmos pass transistor.
5. the clock feedthrough compensated circuit of a kind of clock sampling switch of booting according to claim 1, is characterized in that: described Bootstrap circuit comprises:
Main switch M9 is pmos transistor; The drain electrode of described main switch M9 is connected with output terminal of clock;
The first auxiliary switch M10 is pmos transistor; The source electrode of described the first auxiliary switch M10 is connected with the source electrode of described main switch M9; The grid of described the first auxiliary switch M10 is connected with output terminal of clock; The drain electrode of described the first auxiliary switch is connected with input signal SUP;
The first complementary switch M11 and M12, described M11 is nmos transistor, described M12 is pmos transistor; The drain electrode of described M11 is connected with the source electrode of described M12; The source electrode of described M11 is connected with the drain electrode of described M12; The grid of described M11 is connected with the first complementary sampling clock PHY1; The grid of described M12 is connected with the second complementary sampling clock PHY2;
The second complementary switch M13 and M14, described M13 is pmos transistor, described M14 is nmos transistor; The drain electrode of described M13 is connected with the source electrode of described M14; The source electrode of described M13 is connected with the drain electrode of described M14, input signal IN; The grid of described M13 is connected with the grid of described M12, the second complementary sampling clock PHY2; The grid of described M14 is connected with the first complementary sampling clock PHY1;
The second auxiliary switch M15, described the second auxiliary switch M15 is nmos transistor; The grid of described the second auxiliary switch M15 is connected with the second complementary sampling clock PHY2, and the source electrode of described the second auxiliary switch is connected with GND;
The 3rd auxiliary switch M16, described the 3rd auxiliary switch M16 is nmos transistor; The source electrode of described the 3rd auxiliary switch M16 is connected with GND, and the grid of described the 3rd auxiliary switch is connected with the second complementary sampling clock PHY2;
Bootstrap capacitor C3, one end of described bootstrap capacitor C3 is connected with the drain electrode of described the second auxiliary switch M15, and the other end of described bootstrap capacitor C3 is connected with the source electrode of described the first auxiliary switch M10.
6. the clock feedthrough compensated circuit of a kind of clock sampling switch of booting according to claim 5, is characterized in that: described Bootstrap circuit also comprises:
The first protection switch M17, described the first protection switch M17 is pmos transistor; The grid of described the first protection switch M17 is connected with the first complementary sampling clock PHY1, and the source electrode of described the first protection switch M17 is connected with input signal SUP, and the drain electrode of described the first protection switch M17 is connected with the grid of described main switch M9;
The second protection switch M18, described the second protection switch M18 is nmos transistor; The grid of described the second protection switch M18 is connected with input signal SUP, and the drain electrode of described the second protection switch M18 is connected with the drain electrode of described main switch M9; The source electrode of described the second protection switch M18 is connected with the drain electrode of described the 3rd auxiliary switch M16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420024259.5U CN203708222U (en) | 2014-01-15 | 2014-01-15 | Clock feedthrough compensation circuit of bootstrapped clock sampling switch |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420024259.5U CN203708222U (en) | 2014-01-15 | 2014-01-15 | Clock feedthrough compensation circuit of bootstrapped clock sampling switch |
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| CN203708222U true CN203708222U (en) | 2014-07-09 |
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| CN201420024259.5U Withdrawn - After Issue CN203708222U (en) | 2014-01-15 | 2014-01-15 | Clock feedthrough compensation circuit of bootstrapped clock sampling switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103825616B (en) * | 2014-01-15 | 2017-05-31 | 厦门优迅高速芯片有限公司 | A kind of clock feedthrough compensated circuit of bootstrapped clock sampling switch |
| CN110635791A (en) * | 2019-09-06 | 2019-12-31 | 重庆邮电大学 | Grid voltage bootstrap sampling switch circuit adopting mirror image structure |
| CN110943726A (en) * | 2019-12-12 | 2020-03-31 | 西安电子科技大学 | Multi-channel multi-stage parallel ultra-high-speed sample hold circuit |
| CN113225078A (en) * | 2021-05-07 | 2021-08-06 | 西安博瑞集信电子科技有限公司 | Anti high frequency interference differential switch unit |
-
2014
- 2014-01-15 CN CN201420024259.5U patent/CN203708222U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103825616B (en) * | 2014-01-15 | 2017-05-31 | 厦门优迅高速芯片有限公司 | A kind of clock feedthrough compensated circuit of bootstrapped clock sampling switch |
| CN110635791A (en) * | 2019-09-06 | 2019-12-31 | 重庆邮电大学 | Grid voltage bootstrap sampling switch circuit adopting mirror image structure |
| CN110943726A (en) * | 2019-12-12 | 2020-03-31 | 西安电子科技大学 | Multi-channel multi-stage parallel ultra-high-speed sample hold circuit |
| CN113225078A (en) * | 2021-05-07 | 2021-08-06 | 西安博瑞集信电子科技有限公司 | Anti high frequency interference differential switch unit |
| CN113225078B (en) * | 2021-05-07 | 2022-10-04 | 西安博瑞集信电子科技有限公司 | Anti high frequency interference differential switch unit |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20140709 Effective date of abandoning: 20170531 |
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