CN112671407A - Grid voltage bootstrap switch circuit applied to ultra-low power consumption analog-to-digital converter - Google Patents

Abstract

The invention discloses a grid voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter, which adopts a single-phase clock SP, and sets the grid voltage of a sampling MOS tube MS to be Vin +2VDD through a first stage bootstrap circuit and an auxiliary stage bootstrap circuit during sampling, so that the grid-source voltage difference of the sampling MOS tube MS is constantly 2VDD in the sampling stage, the on-resistance of the sampling tube is further reduced, the linearity is improved, and the precision of the sampling switch circuit is also improved; based on the proposed two-stage bootstrap circuit, the sixth NMOS transistor M6 and the seventh NMOS transistor M7 are serially connected to serve as a substrate switch of the sampling MOS transistor MS, when the sampling MOS transistor MS is in a sampling mode, the grid potential and the substrate potential of the sampling MOS transistor MS are kept consistent, the substrate bias effect of the sampling MOS transistor MS is reduced, and harmonic distortion is reduced.

Description

Grid voltage bootstrap switch circuit applied to ultra-low power consumption analog-to-digital converter

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a grid voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter.

Background

The sampling switch is the front-end circuit of the ultra-low power consumption analog-to-digital converter, has the functions of sampling and holding, and can realize the precision and the linearity which influence the system performance of the whole analog-to-digital converter, so the design of the sampling switch circuit is particularly important. The sampling switches in the sample-and-hold circuit are divided into three types: the CMOS transmission gate and the gate voltage bootstrap switch circuit are formed by a single NMOS tube or a single PMOS tube. The three switches have advantages, wherein a gate voltage bootstrapped Switch Circuit (Bootstrap Switch Circuit) has the advantages of minimum on-resistance, large input range and high linearity although the structure is complex, and thus the Bootstrap Switch Circuit is suitable for an Ultra Low Power Analog to Digital Converter (Ultra Low Power Analog to Digital Converter) to realize the sampling and holding functions of an input Analog signal.

The structure of a traditional gate voltage bootstrap switch circuit is shown in fig. 1, and the traditional gate voltage bootstrap switch circuit is composed of a sampling switch tube and a gate voltage bootstrap circuit, wherein MS is a sampling tube, and C1 and M1-MT form the gate voltage bootstrap circuit. It is well known that the on-resistance of a switching transistor is inversely proportional to the gate-source overdrive voltage and depends to a large extent on the input signal level and the supply voltage, which reduces the linearity of the circuit, especially in ultra-low voltage operation. In a conventional gate voltage bootstrapped switch circuit, since the gate-source overdrive voltage is still low, 1 time of VDD bootstrap is not enough to reduce the on-resistance and body effect of the switch transistor, and may cause non-linearity problem.

Disclosure of Invention

The invention aims to solve the problem that the existing grid voltage bootstrap switch circuit is low in linearity, and provides a grid voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter.

In order to solve the problems, the invention is realized by the following technical scheme:

the gate voltage bootstrap switch circuit applied to the ultra-low power consumption analog-to-digital converter consists of an input phase inverter, a first stage bootstrap circuit, an auxiliary stage bootstrap circuit, a substrate switch and a sampling circuit; the input inverter comprises a MOS transistor M1 and a MOS transistor M2; the first stage bootstrap circuit comprises a MOS tube M3a, a MOS tube M3b, a MOS tube M3C, a MOS tube M3d and a capacitor C1; the auxiliary bootstrap circuit comprises a MOS transistor M4a, a MOS transistor M4b, a MOS transistor M4C, a MOS transistor M4d, a MOS transistor M5 and a capacitor C2; the substrate switch comprises a MOS transistor M6 and a MOS transistor M7; the sampling circuit comprises a sampling MOS tube MS.

The source electrode of the MOS transistor M1, the source electrode of the MOS transistor M3a and the source electrode of the MOS transistor M4a are connected with a working voltage VDD; the source electrode of the MOS transistor M2, the source electrode of the MOS transistor M3c, the source electrode of the MOS transistor M4c, the source electrode of the MOS transistor M4d and the source electrode of the MOS transistor M7 are grounded; the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M2 are simultaneously connected with a single-phase clock SP; the upper polar plate of the capacitor C1 is connected with the drain electrode of the MOS transistor M3a and the source electrode of the MOS transistor M3 b; the lower polar plate of the capacitor C1 is connected with the drain electrode of the MOS transistor M3C and the source electrode of the MOS transistor M3 d; the grid electrode of the MOS transistor M3a, the drain electrode of the MOS transistor M3b and the grid electrode of the MOS transistor M3d are connected; the grid electrode of the MOS transistor M3b, the drain electrode of the MOS transistor M3d and the grid electrode of the MOS transistor M3c are connected with the drain electrode of the MOS transistor M2; the upper polar plate of the capacitor C2 is connected with the drain electrode of the MOS transistor M4a and the source electrode of the MOS transistor M4 b; the lower plate of the capacitor C2 and the drain electrode of the MOS transistor M4C are connected with the gate electrode of the MOS transistor M3 d; the grid electrode of the MOS transistor M4a, the drain electrode of the MOS transistor M4b, the drain electrode of the MOS transistor M4d and the grid electrode of the MOS transistor M5 are connected; the gate of the MOS transistor M4b is connected with the gate of the MOS transistor M3 b; the gate of the MOS transistor M4c and the gate of the MOS transistor M4d are connected with the gate of the MOS transistor M3 c; the source electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M3 d; the drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M6; the grid electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M4 b; the source electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M7; the gate of the MOS transistor M7 is connected with the gate of the MOS transistor M4 d; the grid electrode of the sampling MOS tube MS is connected with the grid electrode of the MOS tube M5, the source electrode of the sampling MOS tube MS and the drain electrode of the MOS tube M6 are connected with an input signal Vin, the drain electrode of the sampling MOS tube MS is connected with an output signal Vout, and the substrate of the sampling MOS tube MS is connected with the drain electrode of the MOS tube M7.

As an improvement, the sampling circuit further comprises a sampling capacitor CS; the upper polar plate of the sampling capacitor CS is connected with the drain electrode of the sampling MOS tube MS; the lower plate of the sampling capacitor CS is grounded.

In the scheme, the MOS transistor M1, the MOS transistor M3a, the MOS transistor M3b, the MOS transistor M4a and the MOS transistor M4b are PMOS transistors; MOS transistor M2, MOS transistor M3c, MOS transistor M3d, MOS transistor M4c, MOS transistor M4d, MOS transistor M5, MOS transistor M6, MOS transistor M7 and sampling MOS transistor MS are NMOS transistors.

As an improvement, the substrate of the MOS transistor M3a is connected with the drain electrode of the MOS transistor M3 a; the substrate of the MOS transistor M4a is connected with the drain electrode of the MOS transistor M4 a; the substrate of the MOS transistor M3b is connected with the source of the MOS transistor M3 b.

Compared with the prior art, the invention has the following characteristics:

1. the single-phase clock SP is adopted, and the grid voltage of the sampling MOS tube MS is set to be Vin +2VDD through the first-stage bootstrap circuit and the auxiliary-stage bootstrap circuit during sampling, so that the grid-source voltage difference of the sampling MOS tube MS is constantly 2VDD in the sampling stage;

2. based on the proposed bootstrap circuit structure, an NMOS tube M6 and an NMOS tube M7 are serially connected to serve as a substrate switch of a sampling MOS tube MS, when the sampling MOS tube MS is in a sampling mode, the grid potential and the substrate potential of the sampling MOS tube MS are kept consistent, the substrate bias effect of the sampling MOS tube MS is reduced, and harmonic distortion is reduced.

Drawings

Fig. 1 is a schematic diagram of a conventional gate voltage bootstrapped switch circuit.

Fig. 2 is a schematic diagram of a gate voltage bootstrapped switch circuit of the present invention.

Fig. 3 is a comparative waveform diagram of a single-phase clock signal, an input signal and an output signal in a gate-voltage bootstrapped switch according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to specific examples.

A gate voltage bootstrap switch circuit applied to an ultra-low power consumption analog-to-digital converter is shown in fig. 2 and comprises an input inverter, a first stage bootstrap circuit, an auxiliary stage bootstrap circuit, a substrate switch and a sampling circuit. The input inverter comprises a MOS transistor M1 and a MOS transistor M2. The first stage bootstrap circuit comprises a MOS transistor M3a, a MOS transistor M3b, a MOS transistor M3C, a MOS transistor M3d and a capacitor C1. The auxiliary stage bootstrap circuit comprises a MOS transistor M4a, a MOS transistor M4b, a MOS transistor M4C, a MOS transistor M4d, a MOS transistor M5 and a capacitor C2. The substrate switch comprises a MOS transistor M6 and a MOS transistor M7. The sampling circuit comprises a sampling MOS tube MS and a sampling capacitor CS.

The source electrode of the MOS transistor M1, the source electrode of the MOS transistor M3a and the source electrode of the MOS transistor M4a are connected with a working voltage VDD; the source electrode of the MOS transistor M2, the source electrode of the MOS transistor M3c, the source electrode of the MOS transistor M4c, the source electrode of the MOS transistor M4d and the source electrode of the MOS transistor M7 are grounded; the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M2 are simultaneously connected with a single-phase clock SP; the upper polar plate of the capacitor C1 is connected with the drain electrode of the MOS transistor M3a and the source electrode of the MOS transistor M3 b; the lower polar plate of the capacitor C1 is connected with the drain electrode of the MOS transistor M3C and the source electrode of the MOS transistor M3 d; the grid electrode of the MOS transistor M3a, the drain electrode of the MOS transistor M3b and the grid electrode of the MOS transistor M3d are connected; the grid electrode of the MOS transistor M3b, the drain electrode of the MOS transistor M3d and the grid electrode of the MOS transistor M3c are connected with the drain electrode of the MOS transistor M2; the upper polar plate of the capacitor C2 is connected with the drain electrode of the MOS transistor M4a and the source electrode of the MOS transistor M4 b; the lower plate of the capacitor C2 and the drain electrode of the MOS transistor M4C are connected with the gate electrode of the MOS transistor M3 d; the grid electrode of the MOS transistor M4a, the drain electrode of the MOS transistor M4b, the drain electrode of the MOS transistor M4d and the grid electrode of the MOS transistor M5 are connected; the gate of the MOS transistor M4b is connected with the gate of the MOS transistor M3 b; the gate of the MOS transistor M4c and the gate of the MOS transistor M4d are connected with the gate of the MOS transistor M3 c; the source electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M3 d; the drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M6; the grid electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M4 b; the source electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M7; the gate of the MOS transistor M7 is connected with the gate of the MOS transistor M4 d; the grid electrode of the sampling MOS tube MS is connected with the grid electrode of the MOS tube M5, the source electrode of the sampling MOS tube MS and the drain electrode of the MOS tube M6 are connected with an input signal Vin, the drain electrode of the sampling MOS tube MS and the upper electrode plate of the sampling capacitor CS are connected with an output signal Vout, the substrate of the sampling MOS tube MS is connected with the drain electrode of the MOS tube M7, and the lower electrode plate of the sampling capacitor CS is grounded.

MOS transistor M1, MOS transistor M3a, MOS transistor M3b, MOS transistor M4a and MOS transistor M4b are PMOS transistors, and the substrates of all the PMOS transistors are connected with the working voltage VDD. MOS transistor M2, MOS transistor M3c, MOS transistor M3d, MOS transistor M4c, MOS transistor M4d, MOS transistor M5, MOS transistor M6, MOS transistor M7 and sampling MOS transistor MS are NMOS transistors, and the substrates of all the NMOS transistors are grounded. In order to improve the stability of the circuit, in the preferred embodiment of the invention, the substrate of the MOS transistor M3a is connected to the drain of the MOS transistor M3 a; the substrate of the MOS transistor M4a is connected with the drain electrode of the MOS transistor M4 a; the substrate of the MOS transistor M3b is connected with the source electrode of the MOS transistor M3b, the substrates of the rest PMOS transistors are connected with the working voltage VDD by a conventional method, and the substrates of the rest NMOS transistors are grounded by a conventional method.

The working process of the invention is as follows:

1) when the single-phase clock SP is at a low level, the first-stage bootstrap circuit and the auxiliary-stage bootstrap circuit are both in a hold mode, the PMOS transistor M1 is turned on, so that the drain level of the PMOS transistor M1 is set to a high level, so that the NMOS transistor M3C, the NMOS transistor M4C, the NMOS transistor M4d and the NMOS transistor M7 are turned on, the lower plate of the capacitor C1 is connected to the ground through the NMOS transistor M3C, the lower plate of the capacitor C2 is connected to the ground through the NMOS transistor M4C, the gate of the PMOS transistor M3a is connected to the ground through the NMOS transistor M4C, so that the PMOS transistor M3a is turned on, the upper plate of the capacitor C1 is set to VDD, the gate of the PMOS transistor M4a is connected to the ground through the NMOS transistor M4d, so that the PMOS transistor M4. Because PMOS pipe M4b cuts off, capacitor C2 and sampling MOS pipe MS separate, and sampling MOS pipe MS grid is connected to ground through NMOS pipe M4d to make sampling MOS pipe MS break, sampling MOS pipe MS substrate passes through NMOS pipe M7 ground connection.

2) When the single-phase clock SP is at high level, the first stage bootstrap circuit and the auxiliary stage bootstrap circuit both work in the sampling mode, the NMOS tube M2 is conducted, so that the drain of the NMOS tube M2 is connected with low level, therefore, the NMOS transistor M3c, the NMOS transistor M4c, the NMOS transistor M4d and the NMOS transistor M7 are cut off, the grid electrode of the PMOS transistor M4b is connected to the ground through the NMOS transistor M2, thereby leading the PMOS transistor M4b to be conducted, raising the grid voltage of the NMOS transistor M5, the sampling MOS transistor MS and the NMOS transistor M6, since the NMOS transistor M5 is turned on, the lower plate of the capacitor C1 is connected to the input signal Vin, i.e. the lower plate level of the capacitor C1 is Vin, the gate of the PMOS transistor M3b is connected to ground through the NMOS transistor M2, therefore, the PMOS transistor M3b is turned on, the capacitor C1 and the capacitor C2 (the capacitor C1 and the capacitor C2 are both pre-charged to VDD in the hold mode) are connected in series, the gate voltage of the sampling MOS transistor MS is Vin +2VDD, the NMOS transistor M6 is turned on, therefore, the substrate of the sampling MOS tube MS is connected with the input signal Vin, and the grid potential of the sampling MOS tube MS is consistent with the substrate potential.

Fig. 3 is a comparative waveform diagram of a single-phase clock signal, an input signal and an output signal in a gate-voltage bootstrapped switch according to an embodiment of the present invention. According to the sampling circuit, a single-phase clock SP is adopted, and the grid voltage of a sampling MOS tube MS is set to be Vin +2VDD through a first-stage bootstrap circuit and an auxiliary-stage bootstrap circuit during sampling, so that the grid-source voltage difference of the sampling MOS tube MS is constantly 2VDD in the sampling stage, the on-resistance of the sampling tube is further reduced, the linearity is improved, and the precision of a sampling switch circuit is also improved; based on the proposed two-stage bootstrap circuit, the NMOS transistor M6 and the NMOS transistor M7 are serially connected to serve as a substrate switch of the sampling MOS transistor MS, when the sampling MOS transistor MS is in a sampling mode, the grid potential and the substrate potential of the sampling MOS transistor MS are kept consistent, the substrate bias effect of the sampling MOS transistor MS is reduced, and harmonic distortion is reduced.

It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.

Claims (4)

1. The grid voltage bootstrap switch circuit applied to the ultra-low power consumption analog-to-digital converter is characterized by comprising an input phase inverter, a first stage bootstrap circuit, an auxiliary stage bootstrap circuit, a substrate switch and a sampling circuit; the input inverter comprises a MOS transistor M1 and a MOS transistor M2; the first stage bootstrap circuit comprises a MOS tube M3a, a MOS tube M3b, a MOS tube M3C, a MOS tube M3d and a capacitor C1; the auxiliary bootstrap circuit comprises a MOS transistor M4a, a MOS transistor M4b, a MOS transistor M4C, a MOS transistor M4d, a MOS transistor M5 and a capacitor C2; the substrate switch comprises a MOS transistor M6 and a MOS transistor M7; the sampling circuit comprises a sampling MOS tube MS;

the source electrode of the MOS transistor M1, the source electrode of the MOS transistor M3a and the source electrode of the MOS transistor M4a are connected with a working voltage VDD; the source electrode of the MOS transistor M2, the source electrode of the MOS transistor M3c, the source electrode of the MOS transistor M4c, the source electrode of the MOS transistor M4d and the source electrode of the MOS transistor M7 are grounded; the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M2 are simultaneously connected with a single-phase clock SP; the upper polar plate of the capacitor C1 is connected with the drain electrode of the MOS transistor M3a and the source electrode of the MOS transistor M3 b; the lower polar plate of the capacitor C1 is connected with the drain electrode of the MOS transistor M3C and the source electrode of the MOS transistor M3 d; the grid electrode of the MOS transistor M3a, the drain electrode of the MOS transistor M3b and the grid electrode of the MOS transistor M3d are connected; the grid electrode of the MOS transistor M3b, the drain electrode of the MOS transistor M3d and the grid electrode of the MOS transistor M3c are connected with the drain electrode of the MOS transistor M2; the upper polar plate of the capacitor C2 is connected with the drain electrode of the MOS transistor M4a and the source electrode of the MOS transistor M4 b; the lower plate of the capacitor C2 and the drain electrode of the MOS transistor M4C are connected with the gate electrode of the MOS transistor M3 d; the grid electrode of the MOS transistor M4a, the drain electrode of the MOS transistor M4b, the drain electrode of the MOS transistor M4d and the grid electrode of the MOS transistor M5 are connected; the gate of the MOS transistor M4b is connected with the gate of the MOS transistor M3 b; the gate of the MOS transistor M4c and the gate of the MOS transistor M4d are connected with the gate of the MOS transistor M3 c; the source electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M3 d; the drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M6; the grid electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M4 b; the source electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M7; the gate of the MOS transistor M7 is connected with the gate of the MOS transistor M4 d; the grid electrode of the sampling MOS tube MS is connected with the grid electrode of the MOS tube M5, the source electrode of the sampling MOS tube MS and the drain electrode of the MOS tube M6 are connected with an input signal Vin, the drain electrode of the sampling MOS tube MS is connected with an output signal Vout, and the substrate of the sampling MOS tube MS is connected with the drain electrode of the MOS tube M7.

2. The gate voltage bootstrap switch circuit applied to ultra-low power consumption analog-to-digital converter as claimed in claim 1, characterized in that the sampling circuit further comprises a sampling capacitor CS; the upper polar plate of the sampling capacitor CS is connected with the drain electrode of the sampling MOS tube MS; the lower plate of the sampling capacitor CS is grounded.

3. The gate voltage bootstrap switch circuit applied to ultra-low power consumption analog-to-digital converter of claim 1, wherein MOS transistor M1, MOS transistor M3a, MOS transistor M3b, MOS transistor M4a and MOS transistor M4b are PMOS transistors; MOS transistor M2, MOS transistor M3c, MOS transistor M3d, MOS transistor M4c, MOS transistor M4d, MOS transistor M5, MOS transistor M6, MOS transistor M7 and sampling MOS transistor MS are NMOS transistors.

4. The gate voltage bootstrap switch circuit applied to ultra-low power consumption analog-to-digital converter as claimed in claim 1, wherein the substrate of MOS transistor M3a is connected to the drain of MOS transistor M3 a; the substrate of the MOS transistor M4a is connected with the drain electrode of the MOS transistor M4 a; the substrate of the MOS transistor M3b is connected with the source of the MOS transistor M3 b.

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