CN203747799U - Sampling and holding switch circuit - Google Patents

Abstract

The utility model discloses a sampling and holding switch circuit. The sampling and holding switch circuit comprises a clock generating sub circuit, a grid voltage bootstrap unit, a sampling field-effect transistor and a holding capacitor, and further comprises a substrate selection sub circuit which is respectively connected with a signal input end, a signal output end and a substrate of the sampling field-effect transistor. The substrate selection sub circuit is used for selecting the signal input end or the signal output end to be connected with the substrate of the sampling field-effect transistor according to the voltage values of an input analog signal and an output analog signal to eliminate the bulk effect of the sampling field-effect transistor. According to the sampling and holding switch circuit, the nonlinearity, produced when the grid source voltage changes along with the input signal, of the sampling field-effect transistor is reduced, the bulk effect of the sampling field-effect transistor is eliminated, the linearity of the sampling field-effect transistor is further improved, and the dynamic range of the sampling and holding switch circuit is enlarged.

Description

Sampling maintained switch circuit

Technical field

The utility model relates to integrated circuit fields, relates more specifically to a kind of sampling maintained switch circuit to analog signal sampling.

Background technology

The ADC(Analog-to-Digital Converter of high-speed, high precision now, A-D converter) in circuit, sampling maintained switch circuit is the bottleneck of whole converter design, and sampling field effect transistor is part indispensable in sample circuit, the speed of sampling field effect transistor and precision have determined the overall performance of sampling maintained switch circuit to a great extent.Under deep submicron process condition, the sampling field effect transistor that connects input signal is connected with the structure of gate voltage bootstrapping, to reduce the conducting resistance of sampling field effect transistor, and reduces the non-linear of sampling field effect transistor and expands input reference signal.But along with increasing of sample frequency, the linearity of the sampling field effect transistor of traditional structure constantly declines, restrict the dynamic range of sampling maintained switch circuit, cannot meet at a high speed the requirement of high-performance analog to digital converter to sampled signal dynamic property.

Therefore, be necessary to provide a kind of improved sampling maintained switch circuit to overcome above-mentioned defect.

Utility model content

The purpose of this utility model is to provide a kind of sampling maintained switch circuit, this sampling maintained switch circuit has reduced sampling field effect transistor because gate source voltage changes with input signal produce non-linear, eliminated the bulk effect of sampling field effect transistor simultaneously, further improve the linearity of sampling field effect transistor, improved the dynamic range of sampling maintained switch circuit.

For achieving the above object, the utility model provides a kind of sampling maintained switch circuit, it comprises clock generating electronic circuit, Bootstrap unit, sampling field effect transistor and maintenance electric capacity, described clock generating electronic circuit has the first output and the second output that are connected with described Bootstrap unit respectively, and described the first output and two complementary clock pulse of the second output output, described Bootstrap unit is also connected with external power source and sampling field effect transistor respectively, two outputs of described Bootstrap unit are connected with grid and a leakage/source electrode of sampling field effect transistor respectively, think that described sampling field effect transistor provides fixing gate source voltage, signal input part is connected with a leakage/source electrode of described sampling field effect transistor, with extremely described sampling field effect transistor of input external analog signal, another leakage/source electrode of described sampling field effect transistor is connected with signal output part, with the analog signal after output sampling, described maintenance electric capacity one end is connected with signal output part, other end ground connection, to keep the analog signal after sampling, wherein, described sampling maintained switch circuit also comprises substrate chooser circuit, described substrate chooser circuit is connected with the substrate of described signal input part, signal output part and sampling field effect transistor respectively, described substrate chooser circuit is connected the substrate of described sampling field effect transistor according to the size selection signal input part of input analog signal and the magnitude of voltage of outputting analog signal or signal output part, to eliminate the bulk effect of sampling field effect transistor.

Preferably, described substrate chooser circuit comprises comparator, follower, reverser, the first switch and second switch; The inverting input of described comparator is connected with described signal input part, and its normal phase input end is connected with described signal output part, and its output is connected with the input of described follower and inverter; One end of described the first switch is connected with signal input part, and one end of described second switch is connected with signal output part, and described the first switch is all connected with the substrate of described sampling field effect transistor with the other end of second switch; And the output of described follower is connected with the control end of described the first switch, the output of described reverser is connected with the control end of described second switch.

Preferably, described the first switch and second switch be closure in the time that the voltage of its control end is high level all, and control end voltage disconnects while being low level.

Preferably, described sampling field effect transistor is N-type field effect transistor.

Preferably, described Bootstrap unit comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and bootstrap capacitor, described the first output is connected with the grid of described the second field effect transistor and described the 3rd field effect transistor, and described the second output is connected with the grid of described the first field effect transistor and described the 8th field effect transistor, one end of described bootstrap capacitor is connected with the drain electrode of described the first field effect transistor and the source electrode of described the second field effect transistor respectively, the drain electrode of the other end of described bootstrap capacitor and described the 4th field effect transistor and the source electrode of described the 5th field effect transistor are connected, the drain electrode of described the 5th field effect transistor is by described anti-leak electronic circuit and the 8th field effect transistor ground connection, the source electrode of external power source and described the 3rd field effect transistor and the source electrode of the 4th field effect transistor are connected, the source electrode of the drain electrode of the 6th field effect transistor and the 7th field effect transistor is connected with a leakage/source electrode of described sampling field effect transistor, the grid of described sampling field effect transistor is connected with the drain electrode of described the 5th field effect transistor and the grid of described the 4th field effect transistor respectively.

Preferably, described Bootstrap unit also comprises anti-leak electronic circuit, described anti-leak electronic circuit is connected between described bootstrap capacitor and ground, and described anti-leak electronic circuit is connected with clock generating electronic circuit and external power source, in the time that described sampling guarantor switching circuit switches to sampling by maintenance, described anti-leak electronic circuit cuts off the connection between described bootstrap capacitor and ground.

Preferably, described anti-leak electronic circuit comprises the 9th field effect transistor and the tenth field effect transistor, and the source electrode of the grid of described the 9th field effect transistor and described the tenth field effect transistor is all connected with external power source, the source electrode of described the 9th field effect transistor is connected with the drain electrode of described the 5th field effect transistor, its drain electrode is connected with the source electrode of described the 8th field effect transistor, described the second output is connected with the grid of described the tenth field effect transistor, and the drain electrode of described the tenth field effect transistor is connected with the source electrode of described the 8th field effect transistor.

Preferably, described Bootstrap unit also comprises the 11 field effect transistor, the source electrode of the grid of the grid of described the 11 field effect transistor and described the 4th field effect transistor, the drain electrode of the 5th field effect transistor and described the 9th field effect transistor is connected, its drain electrode is connected with the drain electrode of the drain electrode of described the 3rd field effect transistor, described the second field effect transistor and the grid of described the 5th field effect transistor, and one end of its source electrode and bootstrap capacitor is connected.

Preferably, described the 6th field effect transistor and the 7th field effect transistor form a transmission gate, and described the first output is connected with the grid of described the 6th field effect transistor, and the second output is connected with the grid of described the 7th field effect transistor.

Compared with prior art, sampling maintained switch circuit of the present utility model due to described substrate chooser circuit respectively with described signal input part, the substrate of signal output part and sampling field effect transistor connects, make to be connected with the substrate of described sampling field effect transistor by described substrate chooser circuit selection signal input or signal output part, when the PN junction that ensures described sampling field effect transistor is reverse-biased, and then the conducting resistance that has ensured described sampling field effect transistor is a constant relevant to technique and outer power voltage, improve the linearity of sampling field effect transistor, improve the sampling performance of sampling maintained switch circuit.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Brief description of the drawings

Fig. 1 is the circuit structure diagram of the utility model sampling maintained switch circuit.

Embodiment

With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of sampling maintained switch circuit, this sampling maintained switch circuit has reduced sampling field effect transistor because gate source voltage changes with input signal produce non-linear, eliminated the bulk effect of sampling field effect transistor simultaneously, further improve the linearity of sampling field effect transistor, improved the dynamic range of sampling maintained switch circuit.

Please refer to Fig. 1, Fig. 1 is the circuit structure diagram of the utility model sampling maintained switch circuit.Sampling maintained switch circuit of the present utility model comprises clock generating electronic circuit, Bootstrap unit, sampling field effect transistor MS, keeps capacitor C S and substrate chooser circuit.Described clock generating electronic circuit has the first output K1 and the second output K2 that are connected with described Bootstrap unit respectively, and described the first output K1 and two complementary clock pulse of the second output K2 output, that is to say, in the time that described the first output K1 is output as high level, described the second output K2 output low level; And the saltus step of described the first output K1 and the second output K2 output level is also contrary, in the time that the level of described the first output K1 output is low level by high level saltus step, now the level of described the second output K2 output is high level by low transition.Described Bootstrap unit is also connected with external power source VDD and sampling field effect transistor MS respectively, (sampling field effect transistor MS of the present utility model is regardless of source electrode and drain electrode with the grid of sampling field effect transistor MS and a leakage/source electrode respectively for two outputs of described Bootstrap unit, be that its source electrode is interchangeable with drain electrode) be connected, think that described sampling field effect transistor MS provides fixing gate source voltage, thereby the gate source voltage of described sampling field effect transistor is not changed with input signal, reduced gate source voltage and changed with input signal produce non-linear; Signal input part VIN is connected with a leakage/source electrode of described sampling field effect transistor MS, with extremely described sampling field effect transistor MS of input external analog signal Vin, another leakage/source electrode of described sampling field effect transistor MS is connected with signal output part VOUT, to export the analog signal Vout after sampling; And one end of described maintenance capacitor C S is connected with signal output part VOUT, other end ground connection, thereby described maintenance capacitor C S can keep the analog signal Vout of output after described sampling field effect transistor MS sampling, so that the further processing of subsequent conditioning circuit to analog signal Vout.Described substrate chooser circuit is connected with the substrate of described signal input part VIN, signal output part VOUT and sampling field effect transistor MS respectively, described substrate chooser circuit selects signal input part VIN or signal output part VOUT to be connected the substrate of described sampling field effect transistor MS according to input analog signal Vin and the magnitude of voltage of outputting analog signal Vout, to eliminate the bulk effect of the field effect transistor MS that samples.

Particularly, please again in conjunction with reference to figure 1.

Described Bootstrap unit comprises the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8, bootstrap capacitor C and anti-leak electronic circuit; The second output K2 of the grid of described the first field effect transistor M1 and described clock generating electronic circuit is connected, its source ground, one end of its drain electrode and described bootstrap capacitor C, the drain electrode of the source electrode of the second field effect transistor M2, the source electrode of the 6th field effect transistor M6 and the 7th field effect transistor M7 connects jointly, and forms node n2; The grid of described the second field effect transistor M2 is connected with the first output K1, and its drain electrode is connected jointly with the drain electrode of described the 3rd field effect transistor M3 and the grid of the 5th field effect transistor M5, and forms node n1; The grid of described the 3rd field effect transistor M3 is connected with described the first output K1, and its source electrode is connected with external power source VDD; The source electrode of described the 4th field effect transistor M4 is connected with external power source VDD, drain electrode, anti-leak electronic circuit and the sampling field effect transistor MS of its grid and the 5th field effect transistor M5 are connected jointly, and form node n4, the source electrode of the drain electrode of described the 4th field effect transistor M4 and described the 5th field effect transistor M5 and the other end of described bootstrap capacitor C are connected, and form node n3; The grid of described the 6th field effect transistor M6 is connected with described the first output K1, and its source electrode is connected with the drain electrode of described the 7th field effect transistor M7, and its drain electrode is connected with source electrode and the sampling field effect transistor MS of described the 7th field effect transistor M7 respectively; The grid of described the 7th field effect transistor M7 is connected with the second output K2, and described the 6th field effect transistor M6 and the common formation of the 7th field effect transistor M7 one transmission gate; The grid of described the 8th field effect transistor M8 is connected with the second output K2, and its source electrode is connected with node n4 by described anti-leak electronic circuit, its grounded drain.

The grid of described sampling field effect transistor MS is connected with node n4, and drain electrode and the signal input part VIN of one source/drain electrode and the 6th field effect transistor M6 are connected, thereby described bootstrap capacitor C provides gate source voltage through described node n4 and described transmission gate for described sampling field effect transistor MS; Wherein, another source/drain signal output VOUT of described sampling field effect transistor MS connects, thereby under the control of the clock pulse that described sampling field effect transistor MS produces at described clock generating electronic circuit, the analog signal Vin of signal input part VIN output is sampled, and the analog signal Vout that sampling is obtained is by described signal output part VOUT output; And in preferred implementation of the present utility model, described sampling field effect transistor is N-type field effect transistor.As previously mentioned, between another leakage/source electrode of described sampling field effect transistor MS and signal output part VOUT, be connected with described maintenance capacitor C S, thereby in the time that described sampling field effect transistor MS stops the sampling to analog signal Vin, the analog signal Vout after described maintenance capacitor C S obtains sampling preserves thereon.

Described anti-leak electronic circuit comprises the 9th field effect transistor M9 and the tenth field effect transistor M10, and the source electrode of the grid of described the 9th field effect transistor M9 and the tenth field effect transistor M10 is all connected with external power source VDD, the source electrode of described the 9th field effect transistor M9 is connected with the drain electrode of the 5th field effect transistor M5, its drain electrode is connected with the source electrode of the 8th field effect transistor M8, the second output K2 is connected with the grid of described the tenth field effect transistor M10, and the drain electrode of described the tenth field effect transistor M10 is connected with the source electrode of the 8th field effect transistor M8; And described the 8th field effect transistor M8 is identical with the architectural feature of the 9th field effect transistor M9, thereby can make the drain-source voltage of described the 8th field effect transistor M8 be less than outer power voltage VDD, avoid described the 8th effect pipe M8 to have withstand voltage problem.

Described substrate chooser circuit comprises comparator, follower FOL, reverser INV, the first switch S 1 and second switch S2; The inverting input of described comparator is connected with described signal input part VIN, and its normal phase input end is connected with described signal output part VOUT, and its output is connected with the input of described follower FOL and inverter INV; One end of described the first switch S 1 is connected with signal input part VIN, and one end of described second switch S2 is connected with signal output part VOUT, and described the first switch S 1 is all connected with the substrate of described sampling field effect transistor MS with the other end of second switch S2; And the output of described follower FOL is connected with the control end of described the first switch S 1, the output of described reverser INV is connected with the control end of described second switch S2, thereby the first switch S 1 closed or disconnect described in the voltage control of described follower FOL output, second switch S2 closed or disconnect described in the voltage control of described reverser INV output.And in preferred implementation of the present utility model, described first opens S1 closes and all closures in the time that the voltage of its control end is high level of second switch S2, and control end voltage disconnects while being low level; Thereby in the time of described comparator output high level, described the first switch S 1 closure, described second switch S2 disconnects, thus the substrate of described sampling field effect transistor MS is connected with described signal input part VIN; And in the time of described comparator output low level, described the first switch S 1 disconnects, described second switch S2 closure, the substrate of described sampling field effect transistor MS is connected with described signal output part VOUT.

In preferred implementation of the present utility model, described Bootstrap unit also comprises the 11 field effect transistor M11, and the grid of described the 11 field effect transistor M11 is connected with node n4, and its source electrode is connected with node n2, and its drain electrode is connected with node n1; Can prevent that by described the tenth field effect transistor M11 described the 5th field effect transistor M5 from existing withstand voltage problem, make sampling maintained switch circuit operation of the present utility model more reliable.

Below in conjunction with reference to figure 1, operation principle of the present utility model is described:

Described sampling maintained switch circuit is in the time of hold mode, and the first output K1 is output as low level, and the second output K2 is output as high level; Now the first field effect transistor M1 conducting, the transmission gate cut-off of the 6th field effect transistor M6 and the 7th field effect transistor M7 composition, disconnects node n2 and signal input part VIN, and the voltage of node n2 is connected to ground by the first field effect transistor M1 of conducting; Node n1 is high level simultaneously, the 5th field effect transistor M5 cut-off.Because the second output K2 is output as high level, so the 9th field effect transistor M9 and the 8th field effect transistor M8 conducting, the tenth field effect transistor M10 cut-off, thereby node n4's is low level, make described sampling field effect transistor MS cut-off, the 11 field effect transistor M11 cut-off, the 4th field effect transistor M4 conducting, outer power voltage VDD charges to VDD-|VDS4|-VDS1 by the 4th field effect transistor M4 and the first field effect transistor M1 of conducting to capacitor C, and wherein VDS4, VDS1 are the drain-source voltage of the 4th field effect transistor M4 and the first field effect transistor M1.In the time of described sampling maintained switch circuit sampling, when described the first output K1 is output as high level, the second output K2 is output as low level, described the first field effect transistor M1 cut-off, the transmission gate conducting that the 6th field effect transistor M6 forms with the 7th field effect transistor M7 is also connected signal input part VIN, and the voltage of node n2 is VIN+VDS6.Because the second output K2 is output as high level, therefore the 8th field effect transistor M8 cut-off, the tenth field effect transistor M10 conducting, thereby the instantaneous cut-off of the 9th field effect transistor M9, and node n1 is now low level, make the 5th field effect transistor M5 conducting, because the voltage of described bootstrap capacitor C can not instantaneous mutation, so now the voltage of node n4 is

Vn4＝VIN+VDS6+VDD－|VDS4|－VDS1 （1）

Thereby the gate source voltage VGS of sampling field effect transistor MS is

VGS＝Vn4－VIN＝VDS6+VDD－|VDS4|－VDS1≈VDD （2）

Because the each field effect transistor in circuit is all switching tube, drain-source voltage when conducting is very little, so (2) formula is about VDD, the gate source voltage of the field effect transistor of sampling MS is permanent in the time of sampling is VDD, the conducting resistance R of the field effect transistor of sampling MS in the time of sampling _sfor

$R_S=\frac{1}{k{(W/L)}_S(\mathrm{VDD}-\mathrm{VTH})}---\left(3\right)$

In formula (3), k is the constant relevant to technique, (W/L) _sfor the breadth length ratio of sampling field effect transistor MS, VTH is the threshold voltage of sampling field effect transistor MS, can find out R by formula (1) _simpedance be the value irrelevant with input signal Vin, and gate source voltage is supply voltage VDD, compared with traditional structure, greatly reduces equiva lent impedance, improved the linearity of sample rate and sampling field effect transistor MS, thereby improved the sampling precision of adc circuit.

In formula (3), the threshold voltage of MS is

$\mathrm{VTH}=\mathrm{VTH}0+\mathrm{\γ}(\sqrt{\left|{2\mathrm{\Φ}}_F{V}_{\mathrm{SB}}\right|}-\sqrt{\left|{2\mathrm{\Φ}}_F\right|})---\left(4\right)$

VTH0 in formula is a constant relevant to technological parameter, and γ is body-effect coefficient, Ф _ffor semiconductor electrostatic balance potential barrier (Fermi level), V _sBfor the electrical potential difference between sampling field effect transistor MS source electrode and substrate.And in the utility model, the source of described sampling field effect transistor MS, drain electrode can be exchanged; In the time of Vin<Vout, the source electrode for sampling field effect transistor MS being connected with described signal input part VIN, the drain electrode for sampling field effect transistor MS being connected with described signal output part VOUT; In the time of Vin>Vout, the drain electrode for sampling field effect transistor MS being connected with described signal input part VIN, the source electrode for sampling field effect transistor MS being connected with described signal output part VOUT.When actual samples to signal while constantly changing, its source electrode cannot be determined, in order to ensure to sample, field effect transistor MS normally works, need PN junction reverse-biased, the substrate of the NMOS sampling field effect transistor of traditional structure is received potential minimum, be ground connection, thereby in the situation that source leakage can be exchanged, still can ensure the normal work of metal-oxide-semiconductor even if ensured.But this kind of circuit structure, V _sBbe the amount of a variation, in conjunction with (3) formula, find out, in the situation that using Bootstrap unit, the conducting resistance of the MOS sampling switch MS of traditional structure in the time of sampling still changes with the difference of input signal.But add after substrate chooser circuit:

When the voltage relationship of input analog signal Vin and outputting analog signal Vout is: when Vin<Vout, the result of described comparator comparison is high level, be output as high level, now described follower FOL is output as high level, the first switch S 1 closure, described inverter INV is output as low level, and second switch S2 disconnects, and the substrate of described sampling field effect transistor MS is connected to signal input part VIN; When the voltage relationship of input analog signal Vin and outputting analog signal Vout is: when Vin>Vout, the result of comparator comparison is low level, be output as low level, now follower FOL is output as low level, the first switch S 1 disconnects, inverter INV is output as high level, second switch S2 closure, and the substrate of described sampling field effect transistor MS is connected to signal output part VOUT.Therefore, no matter when, the substrate of described sampling field effect transistor MS can be connected on input analog signal Vin and the lower level of outputting analog signal Vout, has ensured that PN junction is reverse-biased.In the utility model, use NMOS pipe as sampling field effect transistor MS, compared with the magnitude of voltage of analog signal Vin and Vout, one end of lower voltage is as the source electrode of sampling field effect transistor MS, and make it to be connected with substrate, make to add the electrical potential difference VSB=0 between source electrode and the substrate of NMOS sampling field effect transistor of substrate chooser circuit, therefore (4) formula is adding after substrate chooser circuit, the threshold voltage value of sampling field effect transistor MS is a constant relevant to technological parameter, thereby the conducting resistance that has also ensured the sampling switch of (3) formulas is a constant relevant with supply voltage VDD to technological parameter, therefore further improved the linearity of switch, improve the performance of sampling maintained switch circuit.

In conjunction with most preferred embodiment, the utility model is described above, but the utility model is not limited to the embodiment of above announcement, and should contains the various amendments of carrying out according to essence of the present utility model, equivalent combinations.

Claims (9)

1. a sampling maintained switch circuit, comprise clock generating electronic circuit, Bootstrap unit, sampling field effect transistor and maintenance electric capacity, described clock generating electronic circuit has the first output and the second output that are connected with described Bootstrap unit respectively, and described the first output and two complementary clock pulse of the second output output, described Bootstrap unit is also connected with external power source and sampling field effect transistor respectively, two outputs of described Bootstrap unit are connected with grid and a leakage/source electrode of sampling field effect transistor respectively, think that described sampling field effect transistor provides fixing gate source voltage, signal input part is connected with a leakage/source electrode of described sampling field effect transistor, with extremely described sampling field effect transistor of input external analog signal, another leakage/source electrode of described sampling field effect transistor is connected with signal output part, with the analog signal after output sampling, described maintenance electric capacity one end is connected with signal output part, other end ground connection, to keep the analog signal after sampling, it is characterized in that, also comprise substrate chooser circuit, described substrate chooser circuit is connected with the substrate of described signal input part, signal output part and sampling field effect transistor respectively, described substrate chooser circuit is connected the substrate of described sampling field effect transistor according to the size selection signal input part of input analog signal and the magnitude of voltage of outputting analog signal or signal output part, to eliminate the bulk effect of sampling field effect transistor.

2. sampling maintained switch circuit as claimed in claim 1, is characterized in that, described substrate chooser circuit comprises comparator, follower, reverser, the first switch and second switch; The inverting input of described comparator is connected with described signal input part, and its normal phase input end is connected with described signal output part, and its output is connected with the input of described follower and inverter; One end of described the first switch is connected with signal input part, and one end of described second switch is connected with signal output part, and described the first switch is all connected with the substrate of described sampling field effect transistor with the other end of second switch; And the output of described follower is connected with the control end of described the first switch, the output of described reverser is connected with the control end of described second switch.

3. sampling maintained switch circuit as claimed in claim 2, is characterized in that, described the first switch and second switch be closure in the time that the voltage of its control end is high level all, and control end voltage disconnects while being low level.

4. sampling maintained switch circuit as claimed in claim 2, is characterized in that, described sampling field effect transistor is N-type field effect transistor.

5. sampling maintained switch circuit as claimed in claim 4, it is characterized in that, described Bootstrap unit comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and bootstrap capacitor, described the first output is connected with the grid of described the second field effect transistor and described the 3rd field effect transistor, and described the second output is connected with the grid of described the first field effect transistor and described the 8th field effect transistor, one end of described bootstrap capacitor is connected with the drain electrode of described the first field effect transistor and the source electrode of described the second field effect transistor respectively, the drain electrode of the other end of described bootstrap capacitor and described the 4th field effect transistor and the source electrode of described the 5th field effect transistor are connected, the drain electrode of described the 5th field effect transistor is by anti-leak electronic circuit and the 8th field effect transistor ground connection, the source electrode of external power source and described the 3rd field effect transistor and the source electrode of the 4th field effect transistor are connected, the source electrode of the drain electrode of the 6th field effect transistor and the 7th field effect transistor is connected with a leakage/source electrode of described sampling field effect transistor, the grid of described sampling field effect transistor is connected with the drain electrode of described the 5th field effect transistor and the grid of described the 4th field effect transistor respectively.

6. sampling maintained switch circuit as claimed in claim 5, it is characterized in that, described Bootstrap unit also comprises anti-leak electronic circuit, described anti-leak electronic circuit is connected between described bootstrap capacitor and ground, and described anti-leak electronic circuit is connected with clock generating electronic circuit and external power source, in the time that described sampling guarantor switching circuit switches to sampling by maintenance, described anti-leak electronic circuit cuts off the connection between described bootstrap capacitor and ground.

7. sampling maintained switch circuit as claimed in claim 6, it is characterized in that, described anti-leak electronic circuit comprises the 9th field effect transistor and the tenth field effect transistor, and the source electrode of the grid of described the 9th field effect transistor and described the tenth field effect transistor is all connected with external power source, the source electrode of described the 9th field effect transistor is connected with the drain electrode of described the 5th field effect transistor, its drain electrode is connected with the source electrode of described the 8th field effect transistor, described the second output is connected with the grid of described the tenth field effect transistor, and the drain electrode of described the tenth field effect transistor is connected with the source electrode of described the 8th field effect transistor.

8. sampling maintained switch circuit as claimed in claim 7, it is characterized in that, described Bootstrap unit also comprises the 11 field effect transistor, the source electrode of the grid of the grid of described the 11 field effect transistor and described the 4th field effect transistor, the drain electrode of the 5th field effect transistor and described the 9th field effect transistor is connected, its drain electrode is connected with the drain electrode of the drain electrode of described the 3rd field effect transistor, described the second field effect transistor and the grid of described the 5th field effect transistor, and one end of its source electrode and bootstrap capacitor is connected.

9. sampling maintained switch circuit as claimed in claim 7, it is characterized in that, described the 6th field effect transistor and the 7th field effect transistor form a transmission gate, and described the first output is connected with the grid of described the 6th field effect transistor, and the second output is connected with the grid of described the 7th field effect transistor.