CN203027252U - Sampling holding circuit - Google Patents

Abstract

The utility model discloses a sampling holding circuit, comprising a clock generating sub-circuit, a grid voltage bootstrap unit and a sampling holding sub-circuit, wherein the clock generating sub-circuit comprises a first output end and a second output end which are respectively connected with the grid voltage bootstrap unit; the sampling holding sub-circuit comprises a sampling switch and a holding capacitor; the grid voltage bootstrap unit is also connected with an external power supply and the sampling switch respectively; the sampling holding circuit also comprises a leakage-preventing sub-circuit which connects a bootstrap capacitor of the grid voltage bootstrap unit and the ground, and is also connected with the clock generating sub-circuit and the external power supply; and when the sampling holding sub-circuit is converted to sampling from holding, the leakage-preventing sub-circuit disconnects the bootstrap capacitor and the ground. By virtue of the sampling holding circuit provided by the utility model, the leakage of charges on the bootstrap capacitor during a conversion process of sampling and holding can be effectively prevented, the reduction of bootstrap voltage is stopped, and the linearity of the sampling switch is ensured.

Description

Sampling hold circuit

Technical field

The utility model relates to integrated circuit fields, relates more specifically to a kind of sampling hold circuit.

Background technology

The ADC(Analog-to-Digital Converter of high-speed, high precision now, A-D converter) in circuit, sampling hold circuit is the bottleneck of whole converter design, and sampling switch is part indispensable in sample circuit, and the speed of sampling switch and precision have determined the overall performance of sampling hold circuit to a great extent.Under the deep submicron process condition, the sampling switch that connects input signal is connected with the structure of gate voltage bootstrapping, with the conducting resistance of reduction sampling switch, and reduces the non-linear of sampling switch and enlarges input reference signal.Traditional sampling hold circuit is by the bootstrap capacitor in the Bootstrap structure, can realize the function of sampling switch gate voltage bootstrapping, but (namely in the handoff procedure that keeps and sample) but is accompanied by the leakage of electric charge on bootstrap capacitor in the bootstrapping process, thereby bootstrap voltage mode is descended, introduced nonlinear distortion in sampled signal thereby make.

Therefore, be necessary to provide a kind of improved sampling hold circuit to overcome defects.

The utility model content

The purpose of this utility model is to provide a kind of sampling hold circuit, and this sampling hold circuit can effectively prevent the leakage of electric charge on bootstrap capacitor in the handoff procedure that keeps and sample, and has stoped the decline of bootstrap voltage mode, has guaranteed the linearity of sampling switch.

for achieving the above object, the utility model provides a kind of sampling hold circuit, it comprises the clock generating electronic circuit, Bootstrap unit and sampling keep electronic circuit, described clock generating electronic circuit has respectively and is connected the first output and the second output that the Bootstrap unit connects, and described the first output and complementary two clock pulse of the second output output, described sampling keeps electronic circuit to comprise sampling switch and keeps electric capacity, described sampling switch is sampled to external signal, described maintenance electric capacity is preserved the signal that sampling obtains, described Bootstrap unit also connects with external power source and sampling switch respectively, described Bootstrap unit comprises bootstrap capacitor, described bootstrap capacitor provides fixing gate source voltage for described sampling switch, described sampling switch is controlled to the sampling of external signal by the clock pulse of described clock generating electronic circuit output in described Bootstrap unit, wherein, described sampling hold circuit also comprises the anti-leak electronic circuit, described anti-leak electronic circuit is connected between the bootstrap capacitor and ground of described Bootstrap unit, and described anti-leak electronic circuit connects with clock generating electronic circuit and external power source, when described sampling keeps electronic circuit to switch to sampling by maintenance, described anti-leak electronic circuit cuts off the connection between described bootstrap capacitor and ground.

Preferably, described sampling switch is field effect transistor.

preferably, described Bootstrap unit comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and bootstrap capacitor, described the first output be connected the grid of the second field effect transistor and described the 3rd field effect transistor and connect, described the second output be connected the grid of the first field effect transistor and described the 8th field effect transistor and connect, one end of described bootstrap capacitor respectively be connected the source electrode of the drain electrode of the first field effect transistor and described the second field effect transistor and connect, the other end of described bootstrap capacitor be connected the source electrode of the drain electrode of the 4th field effect transistor and described the 5th field effect transistor and connect, the drain electrode of described the 5th field effect transistor is by described anti-leak electronic circuit and the 8th field effect transistor ground connection, external power source be connected the source electrode of the source electrode of the 3rd field effect transistor and the 4th field effect transistor and connect, the source electrode of the drain electrode of the 6th field effect transistor and the 7th field effect transistor is connected with the source electrode of described sampling switch, the grid of described sampling switch respectively be connected the grid of the drain electrode of the 5th field effect transistor and described the 4th field effect transistor and connect.

Preferably, described anti-leak electronic circuit comprises the 9th field effect transistor and the tenth field effect transistor, and the source electrode of the grid of described the 9th field effect transistor and described the tenth field effect transistor all is connected with external power source, the source electrode of described the 9th field effect transistor be connected the drain electrode of the 5th field effect transistor and connect, its drain electrode and the source electrode connection of the 8th field effect transistor of being connected, described the second output be connected the grid of the tenth field effect transistor and connect, the drain electrode of described the tenth field effect transistor be connected the source electrode of the 8th field effect transistor and connect.

Preferably, the architectural feature of described the 8th field effect transistor and the 9th field effect transistor is identical.

Preferably, described Bootstrap unit also comprises the 11 field effect transistor, the grid of described the 11 field effect transistor be connected the drain electrode of grid, the 5th field effect transistor of the 4th field effect transistor and the source electrode of described the 9th field effect transistor and connect, its drain electrode and the grid of the drain electrode of the drain electrode of the 3rd field effect transistor, described the second field effect transistor and described the 5th field effect transistor of being connected connect, and its source electrode is connected an end connection with bootstrap capacitor.

Preferably, described the 6th field effect transistor and the 7th field effect transistor consist of a transmission gate, and described the first output be connected the grid of the 6th field effect transistor and connect, the second output be connected the grid of the 7th field effect transistor and connect.

Compared to the prior art, sampling hold circuit of the present utility model is owing to also comprising the anti-leak electronic circuit, described anti-leak electronic circuit is connected between the bootstrap capacitor and ground of described Bootstrap unit, and described anti-leak electronic circuit connects with clock generating electronic circuit and external power source, when described sampling kept electronic circuit to switch to sampling by maintenance, described anti-leak electronic circuit cut off the connection between described bootstrap capacitor and ground; Thereby because the connection between described bootstrap capacitor and ground is cut off, cause the electric charge on it can not leak in the handoff procedure that keeps and sample, even the bootstrap voltage mode of sampling switch can not descend, therefore improved the linearity and the sample rate of sampling switch yet.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Description of drawings

Fig. 1 is the structured flowchart of the utility model sampling hold circuit.

Fig. 2 is the circuit theory diagrams of the utility model sampling hold circuit.

Embodiment

With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similar element numbers represents similar element.As mentioned above, the utility model provides a kind of sampling hold circuit, and this sampling hold circuit can effectively prevent the leakage of electric charge on bootstrap capacitor in the handoff procedure that keeps and sample, and has stoped the decline of bootstrap voltage mode, has guaranteed the linearity of sampling switch.

Please refer to Fig. 1, Fig. 1 is the structured flowchart of the utility model sampling hold circuit.As shown in the figure, sampling hold circuit of the present utility model comprises that clock generating electronic circuit, Bootstrap unit, sampling keep electronic circuit and anti-leak electronic circuit; Described clock generating electronic circuit has respectively and is connected the first output and the second output that the Bootstrap unit connects, and described the first output and complementary two clock pulse of the second output output, described clock generating electronic circuit and two clock pulse that will produce offer the unit use of described Bootstrap; Described Bootstrap unit also keeps electronic circuit to connect with external power source and described sampling, described Bootstrap unit provides work required voltage for described sampling keeps electronic circuit, and controls the work that described sampling keeps electronic circuit under the control of the clock that described clock generating electronic circuit produces; Described sampling keeps electronic circuit that external signal is sampled, and the signal after sampling is preserved; Described anti-leak electronic circuit is connected between the bootstrap capacitor and ground of described Bootstrap unit, and described anti-leak electronic circuit connects with clock generating electronic circuit and external power source, when described sampling kept electronic circuit to switch to sampling by maintenance, described anti-leak electronic circuit cut off the connection between described bootstrap capacitor and ground.

Particularly, please again in conjunction with reference to figure 2.

The described clock generating electronic circuit of stating has the first output K1 and the second output K2, and described the first output K1 and the complementary clock pulse of the second output K2 output; That is to say, when described the first output K1 is output as high level, described the second output K2 output low level; And the saltus step of two output level is also opposite, and namely when the level of described the first output K1 output was low level by the high level saltus step, this moment, the level of described the second output K2 output was high level by low transition.

Described Bootstrap unit comprises the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8 and bootstrap capacitor C; The grid of described the first field effect transistor M1 be connected the second output K2 of clock generating electronic circuit and connect, its source ground, the end of its drain electrode and described bootstrap capacitor C, the drain electrode of the source electrode of the source electrode of the second field effect transistor M2, the 6th field effect transistor M6 and the 7th field effect transistor M7 connects jointly, and forms node n2; The grid of described the second field effect transistor M2 be connected output K1 and connect, its drain electrode and be connected the drain electrode of the 3rd field effect transistor M3 and the grid of the 5th field effect transistor M5 and jointly connect, and formation node n1; The grid of described the 3rd field effect transistor M3 be connected the first output K1 and connect, its source electrode is connected with external power source; The source electrode of described the 4th field effect transistor M4 is connected with external power source, the drain electrode of its grid and the 5th field effect transistor M5, anti-leak electronic circuit, and sampling keep electronic circuit jointly to connect, and formation node n4, the drain electrode of described the 4th field effect transistor M4 be connected the other end of the source electrode of the 5th field effect transistor M5 and described bootstrap capacitor C and connect, and form node n3; The grid of described the 6th field effect transistor M6 be connected the first output K1 and connect, its source electrode be connected the drain electrode of the 7th field effect transistor M7 and connect, its drain electrode respectively be connected source electrode and the sampling of the 7th field effect transistor M7 and keep electronic circuit to connect; The grid of described the 7th field effect transistor M7 be connected output K2 and connect, and described the 6th field effect transistor M6 and the 7th field effect transistor M7 is common consists of a transmission gate; The grid of described the 8th field effect transistor M8 be connected output K2 and connect, its source electrode is connected with node n4 by described anti-leak electronic circuit, its grounded drain.

Described sampling keeps electronic circuit comprise sampling switch MS and keep capacitor C S, and in preferred implementation of the present utility model, described sampling switch MS is field effect transistor; Wherein, the grid of described sampling switch MS is connected with node n4, and the drain electrode of its source electrode and the 6th field effect transistor M6 connection, thereby described bootstrap capacitor C provides gate source voltage through described node n4 and described transmission gate for described sampling switch MS; Wherein, the source electrode of described sampling switch MS also be connected output and connect, thereby described sampling switch MS samples to the external signal VIN of outside output output under the control of the clock pulse that described clock generating electronic circuit produces; The drain electrode of described sampling switch MS be connected capacitor C S to connect, the signal VS after can sampling by the drain electrode output of described sampling switch MS; The end ground connection of described maintenance capacitor C S, thus when described sampling switch MS stops sampling to external signal VIN, described maintenance capacitor C S will sample obtain and signal VS preservation thereon.

Described anti-leak electronic circuit comprises the 9th field effect transistor M9 and the tenth field effect transistor M10, and the source electrode of the grid of described the 9th field effect transistor M9 and the tenth field effect transistor M10 all is connected with external power source, the drain electrode of the source electrode of described the 9th field effect transistor M9 and the 5th field effect transistor M5 connects, the source electrode of its drain electrode and the 8th field effect transistor M8 connects, output K2 be connected the grid of the tenth field effect transistor M10 and connect, the source electrode of the drain electrode of described the tenth field effect transistor M10 and the 8th field effect transistor M8 connects; And the architectural feature of described the 8th field effect transistor M8 and the 9th field effect transistor M9 is identical, thereby the drain-source voltage that can make described the 8th field effect transistor M8 avoids described the 8th effect pipe M8 to have withstand voltage problem less than outer power voltage VDD.

In preferred implementation of the present utility model, described Bootstrap unit also comprises the 11 field effect transistor M11, and the grid of described the 11 field effect transistor M11 is connected with node n4, and its source electrode is connected with node n2, and its drain electrode is connected with node n1; Can prevent that by described the tenth field effect transistor M11 from there is withstand voltage problem in described the 5th field effect transistor M5, make sampling hold circuit operation of the present utility model more reliable.

In the utility model, by above-mentioned explanation as can be known, when the clock pulse of described the first output K1 output was high level, described sampling switch MS sampled to external signal VIN; After the clock pulse of described the first output K1 output was low level by the high level saltus step, described sampling switch MS cut-off stop the sampling to external signal VIN, and described maintenance capacitor C S preserved to the signal VS that sampling obtains; And when the clock pulse of described the first output K1 output after high level is returned in saltus step again, described sampling switch MS continues external signal VIN is sampled; Thereby the saltus step along with clock pulse on two outputs of described clock generating electronic circuit, described sampling keeps electronic circuit to switch between sampling and hold mode, is also that described clock generating electronic circuit keeps the sampling of electronic circuit and keeps action by the described sampling of described Bootstrap unit controls.and in the utility model, when sampling keeps electronic circuit to switch to sampling by maintenance, when namely the clock pulse of the second output K2 output is transformed into low level by high level, the 7th field effect transistor M7 of described anti-leak electronic circuit gets final product instantaneous conducting, thereby described the 6th field effect transistor M6 is ended simultaneously, path between described bootstrap capacitor C and ground is disconnected, node n4 is further strengthened to the impedance on ground, eliminated the negative effect that the upper parasitic capacitance of node n5 produces, stoped the charge leakage on described bootstrap capacitor C, namely stoped the decline of sampling switch MS gate source voltage (being also bootstrap voltage mode), thereby the linearity and the sample rate of sampling switch MS have been improved, also namely guaranteed the linearity of sampling picked up signal VS.

Below in conjunction with Fig. 1 and Fig. 2, operation principle and the course of work of the utility model sampling hold circuit described.

As shown in Figure 2, sampling switch MS is in when sampling, its equiva lent impedance R _MSFor

$R_{\mathrm{MS}}=\frac{1}{k{(W/L)}_{\mathrm{MS}}(\mathrm{VGS}-\mathrm{VTH})}=\frac{1}{k{(W/L)}_{\mathrm{MS}}(\mathrm{VG}-\mathrm{VIN}-\mathrm{VTH})}---\left(1\right)$

Wherein k is the constant relevant with technique, (W/L) _MSBe the breadth length ratio of sampling switch MS, VTH is the threshold voltage of sampling switch MS, and is a less amount of variation relatively, and VGS is the gate source voltage of sampling switch MS, and VG is the voltage of the grid of sampling switch MS; And in (1) formula, k, (W/L _{) M}S, VTH are relatively-stationary amount, and the linearity and sample rate in order to improve sampling switch MS require R _MSAs far as possible little, and be worth constant.Need thus VG-VIN large as far as possible, and value is invariable constant.

When the clock pulse of the first output K1 output of described clock generating electronic circuit is low level, the clock pulse of the second output K2 output is high level, described the first field effect transistor M1 conducting this moment, the transmission gate cut-off that the 6th field effect transistor M6 and the 7th field effect transistor M7 form, node n2 and external signal VIN are disconnected, and the voltage of node n2 is connected to ground by the first field effect transistor M1 of conducting; Node n1 is high level simultaneously, and makes the 5th field effect transistor M5 cut-off; So because the clock pulse of the second output K2 output is high level the 9th field effect transistor M9, the 8th field effect transistor M8 conducting, and the tenth field effect transistor M10 cut-off, so node n4 is low level; Thereby make sampling switch MS cut-off, i.e. described sampling keeps electronic circuit to be in hold mode; In said process, described the 11 field effect transistor M11 cut-off, the 4th field effect transistor M4 conducting, external power source charges to outer power voltage VDD by the 4th field effect transistor M4 and the first field effect transistor M1 of conducting to bootstrap capacitor C, is the magnitude of voltage of node n3.When the clock pulse of the first output K1 output of described clock generating electronic circuit is high level, the clock pulse of the second output K2 output is low level, described the first field effect transistor M1 cut-off, the transmission gate conducting of the 6th field effect transistor M6 and the 7th field effect transistor M7 composition also connects external signal VIN, and the voltage of node n2 is VIN.Because the clock pulse of the second output K2 output is low level, therefore the 8th field effect transistor M8 cut-off, the tenth field effect transistor M10 conducting, thereby the 9th instantaneous cut-off of field effect transistor M9, and the node n1 of this moment is low level, make the 5th field effect transistor M5 conducting, because the voltage of described bootstrap capacitor C can not instantaneous mutation, thus this moment node n3 and the voltage of n4 equate, and the magnitude of voltage of node n3 is defined as Vn3, the magnitude of voltage of node n4 is defined as Vn4, namely

Vn3=Vn4＝VIN+VDD （2）

Thereby the gate source voltage VGS of sampling switch MS is

VGS＝Vn4－VIN＝VDD （3）

Can be drawn gate source voltage permanent VDD of being when sampling of sampling switch MS by (3) formula, (1) formula is

$R_{\mathrm{MS}}=\frac{1}{k{(W/L)}_{\mathrm{MS}}(\mathrm{VG}-\mathrm{VIN}-\mathrm{VTH})}=\frac{1}{k{(W/L)}_{\mathrm{MS}}(\mathrm{VDD}-\mathrm{VTH})}---\left(4\right)$

By (4) formula as can be known, sampling hold circuit of the present utility model, in sampling process, the equiva lent impedance R of sampling switch MS _MSBe constant value, reduced its conducting resistance, and VG-VIN is constant outer power voltage VDD, thereby guaranteed the linearity of sampling switch MS, and improved sample rate.

In addition, in order to guarantee the reliability of sampling hold circuit, need to avoid field effect transistor to have problem of withstand voltage, i.e. the absolute value of the gate source voltage of field effect transistor | VGS|, the drain-to-gate voltage absolute value | VGD|, the absolute value of drain-source voltage | VDS| is less than or equal to outer power voltage VDD.in sampling hold circuit of the present utility model, when sampling, when the clock pulse of the first output K1 output of described clock generating electronic circuit is high level, the clock pulse of the second output K2 output is low level, this moment, the voltage of node n3 was above-mentioned (2) formula, the transmission gate conducting of the 6th field effect transistor M6 and the 7th field effect transistor M7 composition at this moment also connects external signal VIN, the grid voltage of the 11 field effect transistor M11 is the voltage of node n4, be VIN+VDD, its source voltage is VIN, this moment, the gate source voltage of the 11 field effect transistor M11 was VDD, thereby make described the 11 field effect transistor M11 conducting, the grid voltage that makes the 5th field effect transistor M5 is VIN.The absolute value of the 5th field effect transistor M5 gate source voltage is VDD, and the problem of withstand voltage of having avoided the 5th field effect transistor M5 to exist has guaranteed reliability.Because the voltage of node n4 is VIN+VDD, this moment, the 9th field effect transistor M9 and the 8th field effect transistor M8 were cut-off state, therefore the voltage of node n4 arrives ground by the 9th field effect transistor M9 and the 8th field effect transistor M8 that disconnects, because the architectural feature of described the 9th field effect transistor M9 and the 8th field effect transistor M8 is identical, the 9th field effect transistor M9 is identical with the equiva lent impedance of the 8th field effect transistor M8, after dividing potential drop, the voltage of node n5 is (VIN+VDD)/2, and it is worth less than outer power voltage VDD; Therefore by the 9th effect pipe M9, the absolute value of the drain-source voltage of described the 8th effect pipe M8 is (VIN+VDD)/2, less than outer power voltage VDD, has avoided the 8th effect pipe M8 to have withstand voltage problem, has guaranteed the reliability of sampling hold circuit.

in above-mentioned sampling keep-process, when sampling keeps electronic circuit to switch to sampling by maintenance, the level of node n4 by low transition to the high level shown in (2) formula, although this process is moment, but because the gate voltage of the 9th effect pipe M9 is VDD, in node n4 voltage transitions process, the 9th M9 has experienced the process of ending after a first conducting, there is Partial charge can leak by the 8th effect pipe M8 of the 9th effect pipe M9 and cut-off the decline of the gate source voltage that causes sampling switch MS on said bootstrap capacitor C, simultaneously also can make the part voltage transfer in the parasitic capacitance of node n5, and then the gate source voltage of adopting switch MS is further descended, it is larger non-linear that the decline of the gate source voltage of sampling switch MS can make sampling switch MS introduce, but when sampling keeps electronic circuit to switch to sampling by maintenance, the 7th field effect transistor M7 of described anti-leak electronic circuit gets final product instantaneous conducting, thereby described the 6th field effect transistor M6 is ended simultaneously, path between described bootstrap capacitor C and ground is disconnected, node n4 is further strengthened to the impedance on ground, eliminated the negative effect that parasitic capacitance produces, stoped the charge leakage on described bootstrap capacitor C, namely stop the decline of sampling switch MS gate source voltage, thereby improved the linearity of sampling switch MS.

Abovely in conjunction with most preferred embodiment, the utility model is described, but the utility model is not limited to the embodiment of above announcement, and should contains various modification, equivalent combinations of carrying out according to essence of the present utility model.

Claims (7)

1. sampling hold circuit, comprise the clock generating electronic circuit, Bootstrap unit and sampling keep electronic circuit, described clock generating electronic circuit has respectively and is connected the first output and the second output that the Bootstrap unit connects, and described the first output and complementary two clock pulse of the second output output, described sampling keeps electronic circuit to comprise sampling switch and keeps electric capacity, described sampling switch is sampled to external signal, described maintenance electric capacity is preserved the signal that sampling obtains, described Bootstrap unit also connects with external power source and sampling switch respectively, described Bootstrap unit comprises bootstrap capacitor, described bootstrap capacitor provides fixing gate source voltage for described sampling switch, described sampling switch is controlled to the sampling of external signal by the clock pulse of described clock generating electronic circuit output in described Bootstrap unit, it is characterized in that, also comprise the anti-leak electronic circuit, described anti-leak electronic circuit is connected between the bootstrap capacitor and ground of described Bootstrap unit, and described anti-leak electronic circuit connects with clock generating electronic circuit and external power source, when described sampling keeps electronic circuit to switch to sampling by maintenance, described anti-leak electronic circuit cuts off the connection between described bootstrap capacitor and ground.

2. sampling hold circuit as claimed in claim 1, is characterized in that, described sampling switch is field effect transistor.

3. sampling hold circuit as claimed in claim 2, it is characterized in that, described Bootstrap unit comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and bootstrap capacitor, described the first output be connected the grid of the second field effect transistor and described the 3rd field effect transistor and connect, described the second output be connected the grid of the first field effect transistor and described the 8th field effect transistor and connect, one end of described bootstrap capacitor respectively be connected the source electrode of the drain electrode of the first field effect transistor and described the second field effect transistor and connect, the other end of described bootstrap capacitor be connected the source electrode of the drain electrode of the 4th field effect transistor and described the 5th field effect transistor and connect, the drain electrode of described the 5th field effect transistor is by described anti-leak electronic circuit and the 8th field effect transistor ground connection, external power source be connected the source electrode of the source electrode of the 3rd field effect transistor and the 4th field effect transistor and connect, the source electrode of the drain electrode of the 6th field effect transistor and the 7th field effect transistor is connected with the source electrode of described sampling switch, the grid of described sampling switch respectively be connected the grid of the drain electrode of the 5th field effect transistor and described the 4th field effect transistor and connect.

4. sampling hold circuit as claimed in claim 3, it is characterized in that, described anti-leak electronic circuit comprises the 9th field effect transistor and the tenth field effect transistor, and the source electrode of the grid of described the 9th field effect transistor and described the tenth field effect transistor all is connected with external power source, the source electrode of described the 9th field effect transistor be connected the drain electrode of the 5th field effect transistor and connect, its drain electrode and the source electrode connection of the 8th field effect transistor of being connected, described the second output be connected the grid of the tenth field effect transistor and connect, the drain electrode of described the tenth field effect transistor be connected the source electrode of the 8th field effect transistor and connect.

5. sampling hold circuit as claimed in claim 4, is characterized in that, the architectural feature of described the 8th field effect transistor and described the 9th field effect transistor is identical.

6. sampling hold circuit as claimed in claim 4, it is characterized in that, described Bootstrap unit also comprises the 11 field effect transistor, the grid of described the 11 field effect transistor be connected the drain electrode of grid, the 5th field effect transistor of the 4th field effect transistor and the source electrode of described the 9th field effect transistor and connect, its drain electrode and the grid of the drain electrode of the drain electrode of the 3rd field effect transistor, described the second field effect transistor and described the 5th field effect transistor of being connected connect, and its source electrode is connected an end connection with bootstrap capacitor.

7. sampling hold circuit as claimed in claim 3, it is characterized in that, described the 6th field effect transistor and the 7th field effect transistor consist of a transmission gate, and described the first output be connected the grid of the 6th field effect transistor and connect, the second output be connected the grid of the 7th field effect transistor and connect.

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