CN203423670U - Variable-gain analog adder - Google Patents
Variable-gain analog adder Download PDFInfo
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- CN203423670U CN203423670U CN201320423700.2U CN201320423700U CN203423670U CN 203423670 U CN203423670 U CN 203423670U CN 201320423700 U CN201320423700 U CN 201320423700U CN 203423670 U CN203423670 U CN 203423670U
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Abstract
The utility model discloses a variable-gain analog adder which comprises a first bias current source, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor. The eighth MOS transistor, the ninth MOS transistor, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are used as an output load of the analog adder. Voltages Vb1 and Vb2 are regulated and controlled to change the on resistances of the eighth MOS transistor and the ninth MOS transistor, thereby regulating the output impedance of the whole analog adder. The reflection at differential output ends (Vop and Von) finally is that the gain of the analog adder is changed.
Description
Technical field
The utility model relates to analog integrated circuit technical field, relates to a kind of analog adder of variable gain.
Background technology
Along with the development of analog integrated circuit technology, the area of chip and power consumption have been proposed to more and more higher requirement, the circuit that need to realize analog as far as possible simple in structure, area is little and low in energy consumption.Analog adder and variable gain amplifier are two modules conventional in analog, and be that often level is linked togather use, independently realize respectively the variation function of addition and the gain of signal, after two modules connect, can realize the addition of signal and the variation of gain.Because used two modules, so circuit structure is complicated, the large power consumption of chip area is high.
Summary of the invention
The utility model, in order to solve the deficiencies in the prior art, has proposed a kind of analog adder of variable gain, realizes addition and the change in gain function of signal simultaneously, will greatly simplify circuit structure, reduces chip area and power consumption.
Technical solutions of the utility model are: a kind of analog adder of variable gain, comprises the first bias current sources, the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 8th MOS transistor, the 9th MOS transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance.
Wherein first bias current sources one end is connected to voltage source V DD, and the other end is connected to the drain electrode of the first MOS transistor, the grid of the grid of the first MOS transistor, the second MOS transistor and the grid of the 3rd MOS transistor;
The drain electrode of the first MOS transistor is connected to the grid of self, and is connected to the grid of the second MOS transistor and the grid of the 3rd MOS transistor, and the source class of the first MOS transistor is connected to ground;
The drain electrode of the second MOS transistor is connected to the source class of the 4th MOS transistor and the source class of the 5th MOS transistor, the grid of the second MOS transistor is connected to the grid of the grid of the first MOS transistor, the drain electrode of the first MOS transistor and the 3rd MOS transistor, the source class ground connection of the second MOS transistor, the effect of the second MOS transistor is tail current source;
The drain electrode of the 3rd MOS transistor is connected to the source class of the 6th MOS transistor and the source class of the 7th MOS transistor, the grid of the 3rd MOS transistor is connected to the grid of the second MOS transistor, grid and the drain electrode of the first MOS transistor, the source class ground connection of the 3rd MOS transistor, the effect of the 3rd MOS transistor is tail current source;
The drain electrode of the 4th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 4th MOS transistor is connected to the positive input IP of the first input differential signal, and the source class of the 4th MOS transistor is connected to the source class of the 5th MOS transistor and the leakage level of the second MOS transistor; The drain electrode of the 5th MOS transistor is connected to the forward output end vo p of output difference sub-signal, the grid of the 5th MOS transistor is connected to the reverse input end IN of the first input differential signal, and the source class of the 5th MOS transistor is connected to the source class of the 4th MOS transistor and the leakage level of the second MOS transistor; Described the 4th MOS transistor and the 5th MOS transistor form the first input difference to pipe;
The drain electrode of the 6th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 6th MOS transistor is connected to the positive input QP of the second input differential signal, and the source class of the 6th MOS transistor is connected to the source class of the 7th MOS transistor and the leakage level of the 3rd MOS transistor; The drain electrode of the 7th MOS transistor is connected to the forward output end vo p of output difference sub-signal, the grid of the 7th MOS transistor is connected to the reverse input end QN of the second input differential signal, and the source class of the 7th MOS transistor is connected to the source class of the 6th MOS transistor and the leakage level of the 3rd MOS transistor; Described the 6th MOS transistor and the 7th MOS transistor form the second input difference to pipe;
The drain electrode of the 8th MOS transistor is connected to the 5th resistance with respect to the other end of Von, and the grid of the 8th MOS transistor connects controls voltage Vb2, and the source class of the 8th MOS transistor is connected to the 6th resistance with respect to the other end of Vop; The 8th MOS transistor plays the effect of switch at this;
The drain electrode of the 9th MOS transistor is connected to the 3rd resistance with respect to the other end of Von, and the grid of the 9th MOS transistor connects controls voltage Vb1, and the source class of the 9th MOS transistor is connected to the 4th resistance with respect to the other end of Vop; The 9th MOS transistor plays the effect of switch at this;
One end of the first resistance is connected to power vd D, and the other end is connected to the inverse output terminal Von of output difference sub-signal;
One end of the second resistance is connected to power vd D, and the other end is connected to the forward output end vo p of output difference sub-signal;
One end of the 3rd resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 9th MOS transistor;
One end of the 4th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 9th MOS transistor;
One end of the 5th resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 8th MOS transistor;
One end of the 6th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 8th MOS transistor;
Described the 8th MOS transistor, the 9th MOS transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance are as the output loading of analog adder, by adjusting, control voltage Vb1 and Vb2, change the conducting resistance of the 8th MOS transistor and the 9th MOS transistor, thereby regulate the output impedance of whole analog adder, the gain that is finally reflected as analog adder at difference output end (Vop and Von) changes;
The utility model is compared with traditional prior art, and the advantage and the effect that have are: greatly simplified circuit structure, reduced chip area and power consumption.
Accompanying drawing explanation
Fig. 1 is the analog adder circuit theory diagrams of variable gain described in the utility model;
Embodiment
Below in conjunction with accompanying drawing, the utility model is elaborated.
Referring to Fig. 1, a kind of analog adder of variable gain comprises the first bias current sources Idc1, the first MOS transistor M1, the second MOS transistor M2, the 3rd MOS transistor M3, the 4th MOS transistor M4, the 5th MOS transistor M5, the 6th MOS transistor M6, the 7th MOS transistor M7, the 8th MOS transistor M8, the 9th MOS transistor M9, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5 and the 6th resistance R 6.
Wherein first bias current sources Idc1 one end is connected to voltage source V DD, and the other end is connected to the drain electrode of the first MOS transistor M1, the grid of the grid of the first MOS transistor M1, the second MOS transistor M2 and the grid of the 3rd MOS transistor M3;
The drain electrode of the first MOS transistor M1 is connected to the grid of self, and is connected to the grid of the second MOS transistor M2 and the grid of the 3rd MOS transistor M3, and the source class of the first MOS transistor M1 is connected to ground;
The drain electrode of the second MOS transistor M2 is connected to the source class of the 4th MOS transistor M4 and the source class of the 5th MOS transistor M5, the grid of the second MOS transistor M2 is connected to the grid of the grid of the first MOS transistor M1, the drain electrode of the first MOS transistor M1 and the 3rd MOS transistor M3, the source class ground connection of the second MOS transistor M2, the effect of the second MOS transistor M2 is tail current source;
The drain electrode of the 3rd MOS transistor M3 is connected to the source class of the 6th MOS transistor M6 and the source class of the 7th MOS transistor M7, the grid of the 3rd MOS transistor M3 is connected to the grid of the second MOS transistor M2, grid and the drain electrode of the first MOS transistor M1, the source class ground connection of the 3rd MOS transistor M3, the effect of the 3rd MOS transistor M3 is tail current source;
The drain electrode of the 4th MOS transistor M4 is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 4th MOS transistor M4 is connected to the positive input IP of the first input differential signal, and the source class of the 4th MOS transistor M4 is connected to the leakage level of source class and the second MOS transistor M2 of the 5th MOS transistor M5; The drain electrode of the 5th MOS transistor M5 is connected to the forward output end vo p of output difference sub-signal, the grid of the 5th MOS transistor M5 is connected to the reverse input end IN of the first input differential signal, and the source class of the 5th MOS transistor M5 is connected to the leakage level of source class and the second MOS transistor M2 of the 4th MOS transistor M4; Described the 4th MOS transistor M4 and the 5th MOS transistor M5 form the first input difference to pipe;
The drain electrode of the 6th MOS transistor M6 is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 6th MOS transistor M6 is connected to the positive input QP of the second input differential signal, and the source class of the 6th MOS transistor M6 is connected to the leakage level of source class and the 3rd MOS transistor M3 of the 7th MOS transistor M7; The drain electrode of the 7th MOS transistor M7 is connected to the forward output end vo p of output difference sub-signal, the grid of the 7th MOS transistor M7 is connected to the reverse input end QN of the second input differential signal, and the source class of the 7th MOS transistor M7 is connected to the leakage level of source class and the 3rd MOS transistor M3 of the 6th MOS transistor M6; Described the 6th MOS transistor M6 and the 7th MOS transistor M7 form the second input difference to pipe;
The drain electrode of the 8th MOS transistor M8 is connected to the 5th resistance R 5 with respect to the other end of Von, and the grid of the 8th MOS transistor M8 connects controls voltage Vb2, and the source class of the 8th MOS transistor M8 is connected to the 6th resistance R 6 with respect to the other end of Vop; The 8th MOS transistor M8 plays the effect of switch at this;
The drain electrode of the 9th MOS transistor M9 is connected to the 3rd resistance R 3 with respect to the other end of Von, and the grid of the 9th MOS transistor M9 connects controls voltage Vb1, and the source class of the 9th MOS transistor M9 is connected to the 4th resistance R 4 with respect to the other end of Vop; The 9th MOS transistor M9 plays the effect of switch at this;
One end of the first resistance R 1 is connected to power vd D, and the other end is connected to the inverse output terminal Von of output difference sub-signal;
One end of the second resistance R 2 is connected to power vd D, and the other end is connected to the forward output end vo p of output difference sub-signal;
One end of the 3rd resistance R 3 is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 9th MOS transistor M9;
One end of the 4th resistance R 4 is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 9th MOS transistor M9;
One end of the 5th resistance R 5 is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 8th MOS transistor M8;
One end of the 6th resistance R 6 is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 8th MOS transistor M8;
Described the 8th MOS transistor M8, the 9th MOS transistor M9, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5 and the 6th resistance R 6 are as the output loading of analog adder, by adjusting, control voltage Vb1 and Vb2, change the conducting resistance of the 8th MOS transistor M8 and the 9th MOS transistor M9, thereby regulate the output impedance of whole analog adder, the gain that is finally reflected as analog adder at difference output end (Vop and Von) changes;
The input of the first input differential signal is IP and IN, the input of the second input differential signal is QP and QN, two differential signals exist respectively, the 4th MOS transistor M4 and the 5th MOS transistor M5 form the first input difference to pipe, the 6th MOS transistor M6 and the 7th MOS transistor M7 form the second input difference to being converted to difference current on pipe, two-pass DINSAR electric current synthetic road difference current in the first resistance R 1 and the second resistance R 2 is converted to again differential voltage simultaneously, by difference output end Vop and Von, exports;
By adjusting, control voltage Vb1 and Vb2, can change the conducting resistance of the 8th MOS transistor M8 and the 9th MOS transistor M9; When the 8th MOS transistor M8 and the 9th MOS transistor M9 conducting, increase the conducting resistance that control voltage Vb1 and Vb2 can increase the 8th MOS transistor M8 and the 9th MOS transistor M9, and then the output impedance that increases whole analog adder, the gain that improves analog adder; When the 8th MOS transistor M8 and the 9th MOS transistor M9 conducting, reduce to control the conducting resistance that voltage Vb1 and Vb2 can reduce the 8th MOS transistor M8 and the 9th MOS transistor M9, and then reduce the output impedance of whole analog adder, reduce the gain of analog adder;
And when regulating control voltage Vb1 and Vb2 that the output impedance of analog adder is changed, the DC point of whole analog adder circuit is stablized constant, and input and output common-mode point is fixed, and has greatly simplified the design of front stage circuits and late-class circuit.
So control voltage Vb1 and Vb2 by adjusting, cooperatively interact, can realize the addition function of the first input differential signal and the first input differential signal, change the gain of analog adder simultaneously.
More than show and described basic principle of the present utility model and principal character and advantage of the present utility model.The technical staff of the industry should understand; the utility model is not restricted to the described embodiments; that in above-described embodiment and specification, describes just illustrates principle of the present utility model; do not departing under the prerequisite of the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (1)
1. an analog adder for variable gain, is characterized in that: comprise the first bias current sources, the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 8th MOS transistor, the 9th MOS transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance;
Described first bias current sources one end is connected to voltage source V DD, and the other end is connected to respectively the drain electrode of the first MOS transistor, the grid of the grid of the first MOS transistor, the second MOS transistor and the grid of the 3rd MOS transistor;
The drain electrode of described the first MOS transistor is connected to respectively grid, the grid of the second MOS transistor and the grid of the 3rd MOS transistor of self, and the source class of the first MOS transistor is connected to ground;
The drain electrode of described the second MOS transistor is connected to the source class of the 4th MOS transistor and the source class of the 5th MOS transistor, the grid of the second MOS transistor is connected to the grid of the 3rd MOS transistor, the source class ground connection of the second MOS transistor, the effect of the second MOS transistor is tail current source;
The drain electrode of described the 3rd MOS transistor is connected to the source class of the 6th MOS transistor and the source class of the 7th MOS transistor, the source class ground connection of the 3rd MOS transistor, and the effect of the 3rd MOS transistor is tail current source;
The drain electrode of described the 4th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 4th MOS transistor is connected to the positive input IP of the first input differential signal, and the source class of the 4th MOS transistor is also connected to the source class of the 5th MOS transistor;
The drain electrode of described the 5th MOS transistor is connected to the forward output end vo p of output difference sub-signal, and the grid of the 5th MOS transistor is connected to the reverse input end IN of the first input differential signal; Described the 4th MOS transistor and the 5th MOS transistor form the first input difference to pipe;
The drain electrode of described the 6th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, and the grid of the 6th MOS transistor is connected to the positive input QP of the second input differential signal, and the source class of the 6th MOS transistor is connected to the source class of the 7th MOS transistor;
The drain electrode of described the 7th MOS transistor is connected to the forward output end vo p of output difference sub-signal, and the grid of the 7th MOS transistor is connected to the reverse input end QN of the second input differential signal; Described the 6th MOS transistor and the 7th MOS transistor form the second input difference to pipe;
The drain electrode of described the 8th MOS transistor is connected to the 5th resistance with respect to the other end of Von, and the grid of the 8th MOS transistor connects controls voltage Vb2, and the source class of the 8th MOS transistor is connected to the 6th resistance with respect to the other end of Vop; The 8th MOS transistor plays the effect of switch at this;
The drain electrode of described the 9th MOS transistor is connected to the 3rd resistance with respect to the other end of Von, and the grid of the 9th MOS transistor connects controls voltage Vb1, and the source class of the 9th MOS transistor is connected to the 4th resistance with respect to the other end of Vop; The 9th MOS transistor plays the effect of switch at this;
One end of the first resistance is connected to power vd D, and the other end is connected to the inverse output terminal Von of output difference sub-signal;
One end of the second resistance is connected to power vd D, and the other end is connected to the forward output end vo p of output difference sub-signal;
One end of the 3rd resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 9th MOS transistor;
One end of the 4th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 9th MOS transistor;
One end of the 5th resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 8th MOS transistor;
One end of the 6th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 8th MOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320423700.2U CN203423670U (en) | 2013-07-16 | 2013-07-16 | Variable-gain analog adder |
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| CN201320423700.2U CN203423670U (en) | 2013-07-16 | 2013-07-16 | Variable-gain analog adder |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103973249A (en) * | 2014-05-09 | 2014-08-06 | 华为技术有限公司 | Variable gain amplifier |
| CN104300961A (en) * | 2013-07-16 | 2015-01-21 | 陕西北斗恒通信息科技有限公司 | Variable-gain analog adder |
-
2013
- 2013-07-16 CN CN201320423700.2U patent/CN203423670U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104300961A (en) * | 2013-07-16 | 2015-01-21 | 陕西北斗恒通信息科技有限公司 | Variable-gain analog adder |
| CN103973249A (en) * | 2014-05-09 | 2014-08-06 | 华为技术有限公司 | Variable gain amplifier |
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Granted publication date: 20140205 Termination date: 20150716 |
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