CN202548685U - Reference voltage buffer circuit - Google Patents
Reference voltage buffer circuit Download PDFInfo
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- CN202548685U CN202548685U CN2011205386293U CN201120538629U CN202548685U CN 202548685 U CN202548685 U CN 202548685U CN 2011205386293 U CN2011205386293 U CN 2011205386293U CN 201120538629 U CN201120538629 U CN 201120538629U CN 202548685 U CN202548685 U CN 202548685U
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Abstract
The utility model provides a reference voltage buffer circuit, belonging to the integrated circuit field. The reference voltage buffer circuit comprises a first MOS (Metal Oxide Semiconductor) transistor and a second MOS transistor both driven by a first operational amplifier, and a current mirror circuit, wherein the current mirror circuit is connected with the first MOS transistor and the second MOS transistor; and the source of the second MOS transistor serves as a reference voltage output end. The current mirror circuit in the reference voltage buffer circuit provided by the utility model is capable of providing accurately matched current, thereby generating an accurately matched circuit working point, and solving the technical problem that the output voltage is incapable of well following the input voltage due to the change of factors such as resistance error, mismatch of two resistors, power supply voltage, process corner, temperature and the like in the reference voltage buffer circuit in the prior art. The output voltage of the reference voltage buffer circuit provided by the utility model is capable of accurately following the input voltage.
Description
Technical field
The utility model belongs to integrated circuit fields, relates in particular to a kind of reference voltage buffer circuit.
Background technology
The reference voltage buffer circuit is widely used in various analog to digital converter (ADC; Analog-to-Digital Converter) or other need in the circuit of reference voltage; Its function is to isolate the influence of late-class circuit to the prime reference voltage, and a kind of reference voltage signal of following the prime reference voltage that can drive late-class circuit is provided.
Differential reference voltage buffer circuit as shown in Figure 1, as to provide for prior art.First operational amplifier A 1 and the 5th NMOS pipe M5 are linked to be degenerative form, and second operational amplifier A 2 and the 7th PMOS pipe M7 are linked to be degenerative form.When first operational amplifier A, 1 positive input terminal is imported the first input reference voltage VREFP_IN; When second operational amplifier A, 2 positive input terminals are imported the second input reference voltage VREFN_IN; The output terminal of first operational amplifier A 1 can produce the first voltage signal V1; The output terminal of second operational amplifier A 2 can produce the second voltage signal V2, and the first voltage signal V1 drives the 5th NMOS pipe M5 and the 6th NMOS pipe M6, and the second voltage signal V2 drives the 7th PMOS pipe M7 and the 8th PMOS pipe M8.Breadth length ratio (W/L) as the 6th NMOS pipe M6
6It is the breadth length ratio (W/L) of the 5th NMOS pipe M5
5N doubly, and the breadth length ratio (W/L) of the 8th PMOS pipe M8
8It is the breadth length ratio (W/L) of the 7th PMOS pipe M7
7N doubly; When the size of second resistance R, 2 resistances is the 1/N of size of first resistance R, 1 resistance; The 6th NMOS pipe M6 is identical with the working point of the 5th NMOS pipe M5; The 8th PMOS pipe M8 is identical with the working point of the 7th PMOS pipe M7, promptly has the first output reference voltage VREFP to equal the 5th NMOS pipe source voltage VP, and the second output reference voltage VREFN equals the 7th PMOS pipe source voltage VN.When first operational amplifier A 1 and second operational amplifier A 2 are ideal operational amplifier, VP=VREFP_IN, VN=VREFN_IN; Therefore, VREFP=VREFP_IN, VREFN=VREFN_IN; Be that VREFP has followed reference voltage VREFP_IN, VREFN has followed reference voltage VREFN_IN.
This difference reference buffer circuit has low output impedance, i.e. the impedance of the first output terminal VREFP is approximately 1/gm6, and the impedance of the second output terminal VREFN is approximately 1/gm8, so its driving force is stronger, output reference voltage can be stablized fast.But it has following weak point:
(1) in the manufacture process of integrated circuit; The absolute error of resistance is up to ± 20%, if first resistance R, 1 resistance reduces 20%, then can cause first electric current I 1 to increase by 20%; Suppose that at this moment the 5th NMOS pipe source voltage VP follows the first input reference voltage VREFP_IN; The 7th PMOS pipe source voltage VN follows the second input reference voltage VREFN_IN, and under these circumstances, the first voltage signal V1 can increase; The second voltage signal V2 can reduce; The situation that possibly occur is: because the first voltage signal V1 increases to a certain degree, cause the part pipe of first operational amplifier A, 1 output stage to be in linear zone, because the second voltage signal V2 is reduced to a certain degree; Cause the part pipe of second operational amplifier A, 2 output stages to be in linear zone; Thereby the performance of first operational amplifier A 1 and second operational amplifier A 2 is descended or disabler, cause the 5th NMOS pipe source voltage VP can not finely follow the first input reference voltage VREFP_IN, the 7th PMOS pipe source voltage VN can not finely follow the second input reference voltage VREFN_IN; Even the 5th NMOS pipe M5 and the 6th NMOS pipe M6, first resistance R 1 and second resistance R 2, the 7th PMOS pipe M7 and the 8th PMOS manage M8 and mate fully; Promptly the first output reference voltage VREFP equals the 5th NMOS pipe source voltage VP, and the second output reference voltage VREFN equals the 7th PMOS pipe source voltage VN, and the first output reference voltage VREFP also is not equal to the first input reference voltage VREFP_IN; The second output reference voltage VREFN also is not equal to the second input reference voltage VREFN_IN, and promptly reference voltage can not be followed the reference voltage of input well with the reference voltage of buffer circuit output.
(2) suppose that the absolute error of first resistance R 1 and second resistance R 2 is all very little; But because the mismatch of first resistance R 1 and second resistance R 2; And the mismatch of the threshold voltage of the 5th NMOS pipe M5 and the 6th NMOS pipe M6, the 7th PMOS pipe M7 and the 8th PMOS pipe M8, size etc. can make the 6th NMOS pipe M6 and the 5th NMOS manage M5, the 8th PMOS to manage M8 and the 7th PMOS to manage the working point of M7 inconsistent; Cause the first output reference voltage VREFP to be not equal to the 5th NMOS pipe source voltage VP; The second output reference voltage VREFN is not equal to the 7th PMOS pipe source voltage VN; Thereby the first output reference voltage VREFP is not equal to the first input reference voltage VREFP_IN, and the second output reference voltage VREFN is not equal to the second input reference voltage VREFN_IN, and promptly the reference voltage of output can not be followed the reference voltage of input well.
(3) because the variation of factors such as supply voltage, process corner, temperature; Can cause first electric current I 1 and second electric current I, 2 mismatches bigger; So the changing operate-point of the 6th NMOS pipe M6 and the 5th NMOS pipe M5, the 8th PMOS pipe M8 and the 7th PMOS pipe M7 is bigger; Thereby the reference voltage of output can not be followed the reference voltage of input well, and the circuit robustness is relatively poor.
The utility model content
The utility model is the technical matters that the reference voltage of the output of the existing reference voltage buffer circuit appearance of solution can not well be followed input reference voltage, and a kind of reference voltage buffer circuit with precise voltage follow-up capability is provided.
A kind of reference voltage buffer circuit comprises: mos pipe that first operational amplifier drives and the 2nd mos pipe, and current mirroring circuit, and said current mirroring circuit is connected with the 2nd mos pipe with mos pipe; The source electrode of said the 2nd mos pipe is a reference voltage output terminal.
Further, said reference voltage buffer circuit also comprises: the 7th mos pipe of second operational amplifier and driving thereof and the 8th mos pipe, and said the 7th mos pipe is connected with said current mirroring circuit with the 8th mos pipe; The source electrode of said the 8th mos pipe is reference voltage output VREFN.
Current mirroring circuit can provide the electric current of accurate coupling in the reference voltage buffer circuit of the utility model; And then produce the accurately circuit working point of coupling, solve the technical matters that output voltage that factors vary such as resistance error in the prior art reference voltage buffer circuit or two resistance mismatch or supply voltage, process corner, temperature cause can not well be followed input voltage; Thereby make the output voltage of the utility model reference voltage buffer circuit have the effect of accurately following input voltage.
Description of drawings
Fig. 1 is the circuit diagram of the reference voltage buffer circuit that provides of prior art.
Fig. 2 is the circuit diagram of the reference voltage buffer circuit that provides of the utility model embodiment 1.
Fig. 3 is the circuit diagram of the reference voltage buffer circuit that provides of the utility model embodiment 2.
Fig. 4 is the circuit diagram of the reference voltage buffer circuit that provides of the utility model embodiment 3.
Fig. 5 is the circuit diagram of the reference voltage buffer circuit that provides of the utility model embodiment 4.
Fig. 6 is the circuit diagram of the reference voltage buffer circuit that provides of the utility model embodiment 5.
Embodiment
Clearer for technical matters, technical scheme and beneficial effect that the utility model is solved, below in conjunction with accompanying drawing and embodiment, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
In order to solve the technical matters that existing reference voltage buffer circuit exists; The utility model provides a kind of reference voltage buffer circuit; Comprise mos pipe, the 2nd mos pipe and current mirroring circuit that first operational amplifier drives, said current mirroring circuit is connected with the 2nd mos pipe with mos pipe; The source electrode of said the 2nd mos pipe is a reference voltage output terminal.
Current mirroring circuit can provide the electric current of accurate coupling in the reference voltage buffer circuit of the utility model; And then the circuit working point of the accurate coupling of generation; Solve the output voltage that factors vary such as resistance error in the prior art reference voltage buffer circuit or two resistance mismatch or supply voltage, process corner, temperature cause and well to follow the technical matters of input voltage, thereby make the output voltage of the utility model reference voltage buffer circuit have the effect of accurately following input voltage.
The single-ended reference voltage buffer circuit of the utility model embodiment 1 is as shown in Figure 2, comprises that first operational amplifier A 1, mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos manage M6; Said mos pipe M1, the 2nd mos pipe M2, the 5th mos pipe M5, the 6th mos pipe M6 are the nmos pipe; Said the 3rd mos pipe M3 and the 4th mos pipe M4 are the pmos pipe.
The positive input of said first operational amplifier A 1 connects the first input reference voltage VREFP_IN, and reverse input end connects the source electrode of said mos pipe M1, and output terminal connects the grid of said mos pipe M1 and said the 2nd mos pipe M2; The drain electrode of said mos pipe M1 and the 2nd mos pipe M2 all meets power vd D;
Said the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos pipe M6 constitute current mirroring circuit; The grid of said the 3rd mos pipe M3 links to each other with the grid of said the 4th mos pipe M4, and the grid of said the 4th mos pipe M4 links to each other with drain electrode; The grid of said the 5th mos pipe M5 links to each other with the grid of said the 6th mos pipe M6, and the grid of said the 5th mos pipe M5 links to each other with drain electrode; The drain electrode of said the 3rd mos pipe M3 links to each other with the drain electrode of said the 5th mos pipe M5; The drain electrode of said the 4th mos pipe M4 links to each other with the drain electrode of said the 6th mos pipe M6; The source grounding of said the 5th mos pipe M5 and the 6th mos pipe M6;
The source electrode of said mos pipe M1 connects the source electrode of said the 3rd mos pipe M3; The source electrode of said the 2nd mos pipe M2 connects the source electrode of said the 4th mos pipe M4; The source electrode of said the 2nd mos pipe M2 is the first reference voltage output terminal VREFP.
For the mos pipe that makes first operational amplifier A 1 output branch road can be operated in the saturation region better, and in order to make the circuit can be in operate as normal under the low supply voltage, preferred methods be the mos pipe that mos pipe M1 and the 2nd mos pipe M2 adopt low threshold voltage.Further, in order to improve output voltage swing and application under low supply voltage, preferred methods is the mos pipe of the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos pipe M6 employing low threshold voltage.In order to reduce to carry on the back matrix effect and the matching precision that improves threshold voltage, the substrate terminal of the 3rd mos pipe M3, the 4th mos pipe M4 all connects source terminal separately.
The single-ended reference voltage buffer circuit of the utility model embodiment 2 is as shown in Figure 3, comprises that first operational amplifier A 1, mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos manage M6; Said mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4 are the pmos pipe; Said the 5th mos pipe M5 and the 6th mos pipe M6 are the nmos pipe.
The 3rd mos pipe M3 and the 4th mos pipe M4 constitute first current mirror; And the 5th mos manages M5 and the 6th mos pipe M6 constitutes second current mirror; The grid of the 3rd mos pipe M3 links to each other with the grid of said the 4th mos pipe M4 in said first current mirror, and the grid of said the 3rd mos pipe M3 links to each other with drain electrode; The source electrode of said the 3rd mos pipe M3 and the 4th mos pipe M4 all is connected power vd D; The grid of the 5th mos pipe M5 links to each other with the grid of said the 6th mos pipe M6 in said second current mirror, and the grid of said the 6th mos pipe M6 links to each other with drain electrode; The source grounding VSS of said the 5th mos pipe M5 and the 6th mos pipe M6.
The positive input of said first operational amplifier A 1 connects the first input reference voltage VREFP_IN, and reverse input end connects the source electrode of said mos pipe M1, and output terminal connects the grid of said mos pipe M1 and said the 2nd mos pipe M2.
The source electrode of said mos pipe M1 connects the drain electrode of said the 3rd mos pipe M3; The source electrode of said the 2nd mos pipe M2 connects the drain electrode of said the 4th mos pipe M4; The drain electrode of said mos pipe M1 connects the drain electrode of said the 5th mos pipe M5; The drain electrode of said the 2nd mos pipe M2 connects the drain electrode of said the 6th mos pipe M6; The source electrode of said the 2nd mos pipe M2 is the first reference voltage output terminal VREFP.
First current mirror and second current mirror among the embodiment 2 are equivalent to the current mirroring circuit among the embodiment 1.In order to improve output voltage swing and under low supply voltage, to use, preferred methods is: the 5th mos pipe M5, the 6th mos pipe M6, mos pipe M1, the 2nd mos pipe M2 adopt the mos pipe of low threshold voltage.In order to reduce to carry on the back matrix effect and the matching precision that improves threshold voltage, the substrate terminal of the 3rd mos pipe M3, the 4th mos pipe M4, mos pipe M1, the 2nd mos pipe M2 connects source end separately.The mos pipe that the 3rd mos manages M3 and the 4th mos pipe M4 employing low threshold voltage still is the mos pipe of high threshold voltage, is to determine according to the size of the first input reference voltage VREFP_IN and the working point of circuit.Usually, when the first input reference voltage VREFP_IN was big, the mos pipe that the 3rd mos pipe M3 and the 4th mos pipe M4 adopt low threshold voltage was for good; When the first input reference voltage VREFP_IN hour, the mos pipe that the 3rd mos pipe M3 and the 4th mos pipe M4 adopt high threshold voltage is for good.The 3rd mos pipe M3 and the 4th mos pipe M4 adopt the mos pipe of low threshold voltage here.
The single-ended reference voltage buffer circuit of the utility model embodiment 3 is as shown in Figure 4, comprises that first operational amplifier A 1, mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos manage M6; Said mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4 are the pmos pipe; Said the 5th mos pipe M5 and the 6th mos pipe M6 are the nmos pipe.
Said current mirroring circuit is the circuit of the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos pipe M6 formation; The grid of said the 3rd mos pipe M3 links to each other with the grid of said the 4th mos pipe M4, and the grid of said the 4th mos pipe M4 links to each other with drain electrode; The source electrode of said the 3rd mos pipe M3 and the 4th mos pipe M4 all meets power vd D; The grid of said the 5th mos pipe M5 links to each other with the grid of said the 6th mos pipe M6, and the grid of said the 5th mos pipe M5 links to each other with drain electrode; The drain electrode of said the 3rd mos pipe M3 links to each other with the drain electrode of said the 5th mos pipe M5; The drain electrode of said the 4th mos pipe M4 links to each other with the drain electrode of said the 6th mos pipe M6.
The positive input of said first operational amplifier A 1 connects the second input reference voltage VREFN_IN, and reverse input end connects the source electrode of said mos pipe M1, and output terminal connects the grid of said mos pipe M1 and said the 2nd mos pipe M2; The equal ground connection VSS of drain electrode of said mos pipe M1 and the 2nd mos pipe M2.
The source electrode of said mos pipe M1 connects the source electrode of said the 5th mos pipe M5; The source electrode of said the 2nd mos pipe M2 connects the source electrode of said the 6th mos pipe M6; The source electrode of said the 2nd mos pipe M2 is the second reference voltage output terminal VREFN.
For the pipe that makes first operational amplifier A 1 output branch road can be operated in the saturation region better, and in order to make the circuit can be in operate as normal under the low supply voltage, preferred methods be the pipe that mos pipe M1 and the 2nd mos pipe M2 adopt low threshold voltage.Further, in order to improve output voltage swing and application under low supply voltage, preferred methods is the pipe of the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos pipe M6 employing low threshold voltage.In order to reduce to carry on the back matrix effect and the matching precision that improves threshold voltage, the substrate terminal of mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4 connects source terminal separately.
The single-ended reference voltage buffer circuit of the utility model embodiment 4 is as shown in Figure 5, comprises that first operational amplifier A 1, mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos manage M6; Said mos pipe M1, the 2nd mos pipe M2, the 5th mos pipe M5, the 6th mos pipe M6 are the nmos pipe; Said the 3rd mos pipe M3 and the 4th mos pipe M4 are the pmos pipe.
The 3rd mos pipe M3 and the 4th mos pipe M4 constitute first current mirror; The 5th mos pipe M5 and the 6th mos pipe M6 constitute second current mirror; The grid of the 3rd mos pipe M3 links to each other with the grid of said the 4th mos pipe M4 in said first current mirror, and the grid of said the 4th mos pipe M4 links to each other with drain electrode; The source electrode of said the 3rd mos pipe M3 and the 4th mos pipe M4 all is connected power vd D; The grid of the 5th mos pipe M5 links to each other with the grid of said the 6th mos pipe M6 in said second current mirror, and the grid of said the 5th mos pipe M5 links to each other with drain electrode; The source grounding VSS of said the 5th mos pipe M5 and the 6th mos pipe M6.
The positive input of said first operational amplifier A 1 connects the second input reference voltage VREFN_IN, and reverse input end connects the source electrode of said mos pipe M1, and output terminal connects the grid of said mos pipe M1 and said the 2nd mos pipe M2.
The drain electrode of said mos pipe M1 connects the drain electrode of said the 3rd mos pipe M3; The drain electrode of said the 2nd mos pipe M2 connects the drain electrode of said the 4th mos pipe M4; The source electrode of said mos pipe M1 connects the drain electrode of said the 5th mos pipe M5; The source electrode of said the 2nd mos pipe M2 connects the drain electrode of said the 6th mos pipe M6; The source electrode of said the 2nd mos pipe M2 is the second reference voltage output terminal VREFN.
First current mirror and second current mirror among the embodiment 4 are equivalent to the current mirroring circuit among the embodiment 3.In order to improve output voltage swing and application under low supply voltage, preferred methods is the mos pipe of mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4 employing low threshold voltage.The 3rd mos pipe M3 is connected supply voltage VDD with the substrate terminal of the 4th mos pipe M4.It still is the pipe of high threshold voltage that the 5th mos pipe M5 and the 6th mos pipe M6 adopt the pipe of low threshold voltage, is to determine according to the size of the second input reference voltage VREFN_IN and the working point of circuit.Usually, when the second input reference voltage VREFN_IN was big, the mos pipe that the 5th mos pipe M5 and the 6th mos pipe M6 adopt high threshold voltage was for good; When the second input reference voltage VREFN_IN hour, the mos pipe that the 5th mos pipe M5 and the 6th mos pipe M6 adopt low threshold voltage is for good.The 5th mos pipe M5 and the 6th mos pipe M6 adopt the mos pipe of low threshold voltage here.
The utility model also provides the embodiment 5 of the reference voltage buffer circuit that a kind of both-end follows; As shown in Figure 6, comprising: comprise that first operational amplifier A 1, second operational amplifier A 2, mos pipe M1, the 2nd mos pipe M2, the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5, the 6th mos pipe M6, the 7th mos pipe M7, the 8th mos manage M8; Said mos pipe M1, the 2nd mos pipe M2, the 5th mos pipe M5 and the 6th mos pipe M6 are the nmos pipe; Said the 3rd mos pipe M3 and the 4th mos pipe M4, the 7th mos pipe M7 and the 8th mos pipe M8 are the pmos pipe.
First operational amplifier A 1 and NMOS pipe M1 connect into degenerative form; The positive input of said first operational amplifier A 1 connects the first input reference voltage VREFP_IN; Reverse input end connects the source electrode of said mos pipe M1, and output terminal connects the grid of said mos pipe M1 and said the 2nd mos pipe M2; The drain electrode of said mos pipe M1 and the 2nd mos pipe M2 all meets power vd D.
Second operational amplifier A 2 and the 7th PMOS pipe M7 connect into degenerative form; The positive input of said second operational amplifier A 2 connects the second input reference voltage VREFN_IN; Reverse input end connects the source electrode of said the 7th mos pipe M7, and output terminal connects the grid of said the 7th mos pipe M7 and said the 8th mos pipe M8; The equal ground connection VSS of drain electrode of said the 7th mos pipe M7 and the 8th mos pipe M8.
Said the 3rd mos pipe M3 and the 5th mos pipe M5, the 4th mos pipe M4 manage M6 with the 6th mos and constitute two branch roads respectively, the mutual by a certain percentage mirror image of first electric current I 1 of first branch road and second electric current I 2 of second branch road or duplicate mutually.The grid of said the 3rd mos pipe M3 links to each other with the grid of said the 4th mos pipe M4, and the grid of said the 4th mos pipe M4 links to each other with drain electrode; The grid of said the 5th mos pipe M5 links to each other with the grid of said the 6th mos pipe M6, and the grid of said the 5th mos pipe M5 links to each other with drain electrode; The drain electrode of said the 3rd mos pipe M3 links to each other with the drain electrode of said the 5th mos pipe M5; The drain electrode of said the 4th mos pipe M4 links to each other with the drain electrode of said the 6th mos pipe M6.
The source electrode of said mos pipe M1 connects the source electrode of said the 3rd mos pipe M3; The source electrode of said the 2nd mos pipe M2 connects the source electrode of said the 4th mos pipe M4.
The source electrode of said the 7th mos pipe M7 connects the source electrode of said the 5th mos pipe M5; The source electrode of said the 8th mos pipe M8 connects the source electrode of said the 6th mos pipe M6; The source electrode of said the 2nd mos pipe M2 is the first reference voltage output terminal VREFP; The source electrode of said the 8th mos pipe M8 is the second reference voltage output terminal VREFN.
For the mos pipe that makes first operational amplifier A 1 and second operational amplifier A, 2 output branch roads can be operated in the saturation region better; And in order to make the circuit can be in operate as normal under the low supply voltage, preferred methods be the pipe that mos pipe M1, the 2nd mos pipe M2, the 7th mos pipe M7 and the 8th mos pipe M8 adopt low threshold voltage.Further, in order to improve output voltage swing and under low supply voltage, to use, preferred methods is the pipe that the 3rd mos pipe M3, the 4th mos pipe M4, the 5th mos pipe M5 and the 6th mos pipe M6 adopt low threshold voltage.In order to reduce to carry on the back matrix effect and the matching precision that improves threshold voltage, the substrate terminal of the 3rd mos pipe M3, the 4th mos pipe M4, the 7th mos pipe M7 and the 8th mos pipe M8 all connects source end separately.
The first input reference voltage VREFP_IN produces the first voltage signal V1 that drives mos pipe M1 and the 2nd mos pipe M2 through first operational amplifier A 1, and the second input reference voltage VREFN_IN produces the second voltage signal V2 that drives the 7th mos pipe M7 and the 8th mos pipe M8 through second operational amplifier A 2.The breadth length ratio of supposing the 4th mos pipe M4 be the 3rd mos pipe M3 breadth length ratio N doubly, the breadth length ratio of the 6th mos pipe M6 be the 5th mos pipe M5 breadth length ratio N doubly, i.e. (W/L)
4=N (W/L)
3, (W/L)
6=N (W/L)
5, ignoring the channel length modulation effect, I2=NI1 then, the mutual mirror image circuit of promptly forming through M3, M4, M5 and M6 can make I1 and I2 mate accurately in certain proportion.If the breadth length ratio of the 2nd mos pipe M2 be mos pipe M1 breadth length ratio N doubly, the breadth length ratio of the 8th mos pipe M8 be the 7th mos pipe M7 breadth length ratio N doubly, i.e. (W/L)
2=N (W/L)
1, (W/L)
8=N (W/L)
7, the electric current that the mos pipe that is then driven by the first voltage signal V1 and the second voltage signal V2 flows through receives mirror image circuit control accurately according to a certain percentage.Because first electric current I 1 and second electric current I 2 are mated according to a certain percentage accurately; So the source end of the 4th mos pipe M4 and the 3rd mos pipe M3 by clamped at same voltage; Promptly a mos manages M1 source voltage VP; At same voltage, promptly the 7th mos manages M7 source voltage VN to the source end of the 6th mos pipe M6 and the 5th mos pipe M5 by clamped.Therefore, the first output reference voltage VREFP can follow the first input reference voltage VREFP_IN well, and the second output reference voltage VREFN can follow the second input reference voltage VREFN_IN well.
Through increasing the breadth length ratio of mos pipe; The 3rd mos pipe M3 and the 4th mos pipe M4, the 5th mos pipe M5 and the 6th mos pipe M6 can accomplish good coupling; Its absolute precision and relative accuracy are all very high; When supply voltage, process corner, temperature variation because first electric current I 1 and second electric current I 2 coupling accurately according to a certain percentage, the source end that the 3rd mos pipe M3 and the 4th mos manage M4 all the time by clamped at same current potential; The source end of the 5th mos pipe M5 and the 6th mos pipe M6 all the time by clamped at same current potential; Therefore the reference voltage of this circuit output can be followed the reference voltage of input well, receives supply voltage, technology, temperature effect very little, and the robustness of circuit is higher.
Because this reference buffer circuit has low output impedance; The i.e. output impedance of the first reference voltage output terminal VREFP is approximately 1/gm2; The output impedance of the second reference voltage output terminal VREFN is approximately 1/gm8, so its driving force is stronger, and output reference voltage can be stablized fast.
Because not high to the bandwidth requirement of first operational amplifier A 1 and second operational amplifier A 2, so this reference voltage buffer circuit power consumption is lower.
Through introducing mirror image circuit, improved the matching precision of integrated circuit, make the reference voltage of this reference voltage buffer circuit output can follow the reference voltage of input well, receive supply voltage, technology, temperature effect very little, the robustness of circuit strengthens.
The above is merely the preferred embodiment of the utility model; Not in order to restriction the utility model; Any modification of being done within all spirit and principles at the utility model, be equal to replacement and improvement etc., all should be included within the protection domain of the utility model.
Claims (27)
1. reference voltage buffer circuit; Comprise: mos pipe that first operational amplifier drives and the 2nd mos pipe; It is characterized in that said reference voltage buffer circuit also comprises current mirroring circuit, said current mirroring circuit is connected with the 2nd mos pipe with mos pipe; The source electrode of said the 2nd mos pipe is a reference voltage output terminal.
2. reference voltage buffer circuit as claimed in claim 1 is characterized in that, said current mirroring circuit is the circuit of the 3rd mos pipe, the 4th mos pipe, the 5th mos pipe, the 6th mos pipe formation;
The grid of said the 3rd mos pipe links to each other with the grid of said the 4th mos pipe, and the grid of said the 4th mos pipe links to each other with drain electrode; The grid of said the 5th mos pipe links to each other with the grid of said the 6th mos pipe, and the grid of said the 5th mos pipe links to each other with drain electrode; The drain electrode of said the 3rd mos pipe links to each other with the drain electrode of said the 5th mos pipe; The drain electrode of said the 4th mos pipe links to each other with the drain electrode of said the 6th mos pipe; The source grounding of said the 5th mos pipe and the 6th mos pipe;
The positive input of said first operational amplifier connects the first input reference voltage VREFP_IN, and reverse input end connects the source electrode of said mos pipe, and output terminal connects the grid of said mos pipe and said the 2nd mos pipe; The drain electrode of said mos pipe and the 2nd mos pipe all meets power vd D;
The source electrode of said mos pipe connects the source electrode of said the 3rd mos pipe; The source electrode of said the 2nd mos pipe connects the source electrode of said the 4th mos pipe; The source electrode of said the 2nd mos pipe is the first reference voltage output terminal VREFP.
3. reference voltage buffer circuit as claimed in claim 2 is characterized in that, said mos pipe, the 2nd mos pipe, the 5th mos pipe and the 6th mos pipe are the nmos pipe; Said the 3rd mos pipe and the 4th mos pipe are the pmos pipe.
4. reference voltage buffer circuit as claimed in claim 2 is characterized in that, said mos pipe, the 2nd mos pipe are low threshold voltage mos pipe.
5. reference voltage buffer circuit as claimed in claim 2 is characterized in that, said the 3rd mos pipe, the 4th mos pipe, the 5th mos pipe, the 6th mos pipe are the mos pipe of low threshold voltage.
6. reference voltage buffer circuit as claimed in claim 2 is characterized in that, the substrate terminal of said the 3rd mos pipe, the 4th mos pipe all connects source terminal separately.
7. reference voltage buffer circuit as claimed in claim 1 is characterized in that, said current mirroring circuit comprises: first current mirror that the 3rd mos pipe and the 4th mos pipe constitute; And second current mirror of the 5th mos pipe and the 6th mos pipe formation;
The grid of the 3rd mos pipe links to each other with the grid of said the 4th mos pipe in said first current mirror, and the grid of said the 3rd mos pipe links to each other with drain electrode; The source electrode of said the 3rd mos pipe and the 4th mos pipe all is connected power vd D;
The grid of the 5th mos pipe links to each other with the grid of said the 6th mos pipe in said second current mirror, and the grid of said the 6th mos pipe links to each other with drain electrode; The source grounding VSS of said the 5th mos pipe and the 6th mos pipe;
The positive input of said first operational amplifier connects the first input reference voltage VREFP_IN, and reverse input end connects the source electrode of said mos pipe, and output terminal connects the grid of said mos pipe and said the 2nd mos pipe;
The source electrode of said mos pipe connects the drain electrode of said the 3rd mos pipe; The source electrode of said the 2nd mos pipe connects the drain electrode of said the 4th mos pipe;
The drain electrode of said mos pipe connects the drain electrode of said the 5th mos pipe; The drain electrode of said the 2nd mos pipe connects the drain electrode of said the 6th mos pipe; The source electrode of said the 2nd mos pipe is the first reference voltage output terminal VREFP.
8. reference voltage buffer circuit as claimed in claim 7 is characterized in that, said mos pipe, the 2nd mos pipe, the 3rd mos pipe and the 4th mos pipe are the pmos pipe; Said the 5th mos pipe and the 6th mos pipe are the nmos pipe.
9. reference voltage buffer circuit as claimed in claim 7 is characterized in that, said mos pipe, the 2nd mos pipe, the 5th mos pipe, the 6th mos pipe are the mos pipe of low threshold voltage.
10. reference voltage buffer circuit as claimed in claim 7 is characterized in that, said the 3rd mos pipe, the 4th mos pipe are the mos pipe of low threshold voltage.
11. reference voltage buffer circuit as claimed in claim 7 is characterized in that, the substrate terminal of said mos pipe, the 2nd mos pipe, the 3rd mos pipe, the 4th mos pipe all connects source terminal separately.
12. reference voltage buffer circuit as claimed in claim 1 is characterized in that, said current mirroring circuit is the circuit of the 3rd mos pipe, the 4th mos pipe, the 5th mos pipe, the 6th mos pipe formation;
The grid of said the 3rd mos pipe links to each other with the grid of said the 4th mos pipe, and the grid of said the 4th mos pipe links to each other with drain electrode; The source electrode of said the 3rd mos pipe and the 4th mos pipe all meets power vd D; The grid of said the 5th mos pipe links to each other with the grid of said the 6th mos pipe, and the grid of said the 5th mos pipe links to each other with drain electrode; The drain electrode of said the 3rd mos pipe links to each other with the drain electrode of said the 5th mos pipe; The drain electrode of said the 4th mos pipe links to each other with the drain electrode of said the 6th mos pipe;
The positive input of said first operational amplifier connects the second input reference voltage VREFN_IN, and reverse input end connects the source electrode of said mos pipe, and output terminal connects the grid of said mos pipe and said the 2nd mos pipe; The equal ground connection VSS of drain electrode of said mos pipe and the 2nd mos pipe;
The source electrode of said mos pipe connects the source electrode of said the 5th mos pipe; The source electrode of said the 2nd mos pipe connects the source electrode of said the 6th mos pipe; The source electrode of said the 2nd mos pipe is the second reference voltage output terminal VREFN.
13. reference voltage buffer circuit as claimed in claim 12 is characterized in that, said mos pipe, the 2nd mos pipe, the 3rd mos pipe and the 4th mos pipe are the pmos pipe; Said the 5th mos pipe and the 6th mos pipe are the nmos pipe.
14. reference voltage buffer circuit as claimed in claim 12 is characterized in that, said mos pipe, the 2nd mos pipe are the mos pipe of low threshold voltage.
15. reference voltage buffer circuit as claimed in claim 12 is characterized in that, said the 3rd mos pipe, the 4th mos pipe, the 5th mos pipe, the 6th mos pipe are the mos pipe of low threshold voltage.
16. reference voltage buffer circuit as claimed in claim 12 is characterized in that, the substrate terminal of said mos pipe, the 2nd mos pipe, the 3rd mos pipe, the 4th mos pipe all connects source terminal separately.
17. reference voltage buffer circuit as claimed in claim 1 is characterized in that, said current mirroring circuit comprises: first current mirror that the 3rd mos pipe and the 4th mos pipe constitute; Second current mirror that the 5th mos pipe and the 6th mos pipe constitute;
The grid of the 3rd mos pipe links to each other with the grid of said the 4th mos pipe in said first current mirror, and the grid of said the 4th mos pipe links to each other with drain electrode; The source electrode of said the 3rd mos pipe and the 4th mos pipe all is connected power vd D;
The grid of the 5th mos pipe links to each other with the grid of said the 6th mos pipe in said second current mirror, and the grid of said the 5th mos pipe links to each other with drain electrode; The source grounding VSS of said the 5th mos pipe and the 6th mos pipe;
The positive input of said first operational amplifier connects the second input reference voltage VREFN_IN, and reverse input end connects the source electrode of said mos pipe, and output terminal connects the grid of said mos pipe and said the 2nd mos pipe;
The drain electrode of said mos pipe connects the drain electrode of said the 3rd mos pipe; The drain electrode of said the 2nd mos pipe connects the drain electrode of said the 4th mos pipe;
The source electrode of said mos pipe connects the drain electrode of said the 5th mos pipe; The source electrode of said the 2nd mos pipe connects the drain electrode of said the 6th mos pipe; The source electrode of said the 2nd mos pipe is the second reference voltage output terminal VREFN.
18. reference voltage buffer circuit as claimed in claim 17 is characterized in that, said mos pipe, the 2nd mos pipe, the 5th mos pipe and the 6th mos pipe are the nmos pipe; Said the 3rd mos pipe and the 4th mos pipe are the pmos pipe.
19. reference voltage buffer circuit as claimed in claim 17 is characterized in that, said mos pipe, the 2nd mos pipe, the 3rd mos pipe, the 4th mos pipe are the mos pipe of low threshold voltage.
20. reference voltage buffer circuit as claimed in claim 17 is characterized in that, said the 5th mos pipe, the 6th mos pipe are the mos pipe of low threshold voltage.
21. reference voltage buffer circuit as claimed in claim 17 is characterized in that, the substrate terminal of said the 3rd mos pipe, the 4th mos pipe all connects source terminal separately.
22. reference voltage buffer circuit as claimed in claim 1; It is characterized in that; Said reference voltage buffer circuit also comprises: the 7th mos pipe of second operational amplifier and driving thereof and the 8th mos pipe, and said the 7th mos pipe is connected with said current mirroring circuit with the 8th mos pipe; The source electrode of said the 8th mos pipe is second reference voltage output VREFN.
23. reference voltage buffer circuit as claimed in claim 22 is characterized in that, said current mirroring circuit is the circuit of the 3rd mos pipe, the 4th mos pipe, the 5th mos pipe, the 6th mos pipe formation;
The grid of said the 3rd mos pipe links to each other with the grid of said the 4th mos pipe, and the grid of said the 4th mos pipe links to each other with drain electrode; The grid of said the 5th mos pipe links to each other with the grid of said the 6th mos pipe, and the grid of said the 5th mos pipe links to each other with drain electrode; The drain electrode of said the 3rd mos pipe links to each other with the drain electrode of said the 5th mos pipe; The drain electrode of said the 4th mos pipe links to each other with the drain electrode of said the 6th mos pipe;
The positive input of said first operational amplifier connects the first input reference voltage VREFP_IN, and reverse input end connects the source electrode of said mos pipe, and output terminal connects the grid of said mos pipe and said the 2nd mos pipe; The drain electrode of said mos pipe and the 2nd mos pipe all meets power vd D;
The positive input of said second operational amplifier connects the second input reference voltage VREFN_IN, and reverse input end connects the source electrode of said the 7th mos pipe, and output terminal connects the grid of said the 7th mos pipe and said the 8th mos pipe; The equal ground connection VSS of drain electrode of said the 7th mos pipe and the 8th mos pipe;
The source electrode of said mos pipe connects the source electrode of said the 3rd mos pipe; The source electrode of said the 2nd mos pipe connects the source electrode of said the 4th mos pipe;
The source electrode of said the 7th mos pipe connects the source electrode of said the 5th mos pipe; The source electrode of said the 8th mos pipe connects the source electrode of said the 6th mos pipe;
The source electrode of said the 2nd mos pipe is the first reference voltage output terminal VREFP; The source electrode of said the 8th mos pipe is the second reference voltage output terminal VREFN.
24. reference voltage buffer circuit as claimed in claim 23 is characterized in that, said the 3rd mos pipe, the 4th mos pipe, the 7th mos pipe, the 8th mos pipe are the pmos pipe; Said mos pipe, the 2nd mos pipe, the 5th mos pipe, the 6th mos pipe are the nmos pipe.
25. reference voltage buffer circuit as claimed in claim 23 is characterized in that, said mos pipe, the 2nd mos pipe, the 7th mos pipe, the 8th mos pipe are the mos pipe of low threshold voltage.
26. reference voltage buffer circuit as claimed in claim 23 is characterized in that, said the 3rd mos pipe, the 4th mos pipe, the 5th mos pipe, the 6th mos pipe are the mos pipe of low threshold voltage.
27. reference voltage buffer circuit as claimed in claim 23 is characterized in that, the substrate terminal of said the 3rd mos pipe, the 4th mos pipe, the 7th mos pipe, the 8th mos pipe all connects source terminal separately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205386293U CN202548685U (en) | 2011-12-21 | 2011-12-21 | Reference voltage buffer circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205386293U CN202548685U (en) | 2011-12-21 | 2011-12-21 | Reference voltage buffer circuit |
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|---|---|
| CN202548685U true CN202548685U (en) | 2012-11-21 |
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| CN2011205386293U Expired - Lifetime CN202548685U (en) | 2011-12-21 | 2011-12-21 | Reference voltage buffer circuit |
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| CN (1) | CN202548685U (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104731144A (en) * | 2013-12-23 | 2015-06-24 | 比亚迪股份有限公司 | Reference voltage generating circuit |
| WO2016029341A1 (en) * | 2014-08-25 | 2016-03-03 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN108415499A (en) * | 2017-02-10 | 2018-08-17 | 中芯国际集成电路制造(上海)有限公司 | Reference voltage driver |
| CN112087231A (en) * | 2020-11-12 | 2020-12-15 | 深圳市汇顶科技股份有限公司 | Reference voltage buffer circuit |
| CN113867466A (en) * | 2021-10-14 | 2021-12-31 | 上海安路信息科技股份有限公司 | Voltage stabilizer circuit |
| WO2022099558A1 (en) * | 2020-11-12 | 2022-05-19 | 深圳市汇顶科技股份有限公司 | Reference voltage buffer circuit |
| CN114756076A (en) * | 2021-01-08 | 2022-07-15 | 成都微光集电科技有限公司 | Voltage buffer circuit |
| CN117908616A (en) * | 2024-02-29 | 2024-04-19 | 杭州芯迈半导体技术有限公司 | Voltage dividing circuit with driving capability |
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2011
- 2011-12-21 CN CN2011205386293U patent/CN202548685U/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104731144A (en) * | 2013-12-23 | 2015-06-24 | 比亚迪股份有限公司 | Reference voltage generating circuit |
| WO2016029341A1 (en) * | 2014-08-25 | 2016-03-03 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
| US9692398B2 (en) | 2014-08-25 | 2017-06-27 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
| US9762215B1 (en) | 2014-08-25 | 2017-09-12 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
| CN106325351A (en) * | 2016-10-14 | 2017-01-11 | 广州昌钰行信息科技有限公司 | Two-channel voltage buffer circuit |
| CN108415499A (en) * | 2017-02-10 | 2018-08-17 | 中芯国际集成电路制造(上海)有限公司 | Reference voltage driver |
| CN112087231A (en) * | 2020-11-12 | 2020-12-15 | 深圳市汇顶科技股份有限公司 | Reference voltage buffer circuit |
| WO2022099558A1 (en) * | 2020-11-12 | 2022-05-19 | 深圳市汇顶科技股份有限公司 | Reference voltage buffer circuit |
| US11824549B2 (en) | 2020-11-12 | 2023-11-21 | Shenzhen GOODIX Technology Co., Ltd. | Reference voltage buffer circuit |
| CN114756076A (en) * | 2021-01-08 | 2022-07-15 | 成都微光集电科技有限公司 | Voltage buffer circuit |
| CN113867466A (en) * | 2021-10-14 | 2021-12-31 | 上海安路信息科技股份有限公司 | Voltage stabilizer circuit |
| CN113867466B (en) * | 2021-10-14 | 2023-03-14 | 上海安路信息科技股份有限公司 | Voltage stabilizer circuit |
| CN117908616A (en) * | 2024-02-29 | 2024-04-19 | 杭州芯迈半导体技术有限公司 | Voltage dividing circuit with driving capability |
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Effective date of registration: 20191231 Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Patentee after: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address before: BYD 518118 Shenzhen Road, Guangdong province Pingshan New District No. 3009 Patentee before: BYD Co.,Ltd. |
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Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. |
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Granted publication date: 20121121 |