CN105897271A - High-intermediate frequency sample hold circuit for pipeline analog-to-digital converter - Google Patents
High-intermediate frequency sample hold circuit for pipeline analog-to-digital converter Download PDFInfo
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- CN105897271A CN105897271A CN201610188351.9A CN201610188351A CN105897271A CN 105897271 A CN105897271 A CN 105897271A CN 201610188351 A CN201610188351 A CN 201610188351A CN 105897271 A CN105897271 A CN 105897271A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
Abstract
The invention relates to a high-intermediate frequency sample hold circuit for a pipeline analog-to-digital converter. The high-intermediate frequency sample hold circuit comprises a switch capacitance circuit, an input drive circuit, two gate voltage substrate bootstrapping circuits, two common-mode resetting circuit and a main operational amplifier. A conventional charge redistribution type sample hold circuit is modified, and the improved sample hold circuit structure suppresses charge leakage of a parasitic capacitor at a source-leakage end of an input sampling switch. Extra input sampling switches are added to offset parasitic capacitor charge leakage, so that incoming signal bandwidth is increased.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of sampling being suitable for high-frequency signal is carried out if sampling and keep electricity
Road, a kind of high if sampling holding circuit for production line analog-digital converter.
Background technology
In recent years, the analog-digital converter (Analog to Digital Converter, ADC) of high-speed, high precision is at HD video, 3G
The fields such as communication, medical apparatus and instruments and radar are widely used.Production line analog-digital converter (Pipeline ADC) conduct
The optimum selection of high-speed, high precision field ADC, its performance is developed rapidly.Sampling hold circuit is in pipeline ADC
Foremost, it has been used for analogue signal by continuing to discrete transformation process.Its performance is the highest of whole analog-digital converter
Performance, and have can not corrective, be restriction pipeline ADC system speed, precision and the bottleneck of linearity index advantage.
According to nyquist sampling theorem, along with increasing substantially of frequency input signal and sample clock frequency, sampling keeps electricity
The response speed on road is also required to improve accordingly.And the core work that its response speed promotes and restriction are exactly switching capacity
The high gain-bandwidth that technology is relied on amasss the response speed of operational amplifier and the raising of precision.CMOS technology condition in standard
Under, the lifting of the performance of such operational amplifier encounters increasing restriction.Intermediate frequency Undersampling technique is used greatly to drop
The response speed requirement of low sampling hold circuit.
In production line analog-digital converter, the charge redistribution formula sampling hold circuit of prior art is as shown in Figure 1.Such as Fig. 2 institute
Showing, its work process is as follows: sampling, phase, i.e. clk1 and clk1p are high level, when clk2 is low level, and switch S1 Guan Bi,
Input signal is sampled on electric capacity Cs, and sample/hold amplifier input is shorted to Vcm, outfan also short circuit.Protecting
Hold phase, i.e. clk1 is low level, and when clk2 is high level, switch S1 turns off, and S2 closes, and clk1p than clk1 early jump is
Low level, now, amplifier is connected into closed loop, and two sampling capacitance bottom crowns are coupled together, and differential mode electric charge is transferred to instead
Feed holds on Cf, this completes the discrete sampling to continuous signal.This circuit is applicable to high-speed, high precision A/D converter.
Conventional charge reassigns in formula sampling hold circuit, due to the non-linear and bulk effect of the equivalent resistance of input sample switch,
And and source and drain end exist parasitic capacitance, the biggest distortion can be introduced, thus limit input signal bandwidth.Further, since
Being the closed-loop structure of capacitive form, amplifier needs possess higher bandwidth and gain to meet the requirement of high-speed, high precision, so
Inevitable requirement its consume the biggest power consumption to realize less setting up the time.
Summary of the invention
The technical problem to be solved in the present invention is to overcome existing defect, it is provided that a kind of high intermediate frequency for production line analog-digital converter
Sampling hold circuit, suppresses the non-linear and body of the equivalent resistance of input sample switch in existing charge redistribution sampling hold circuit
Effect, and the distorted signals problem that the parasitic capacitance of source and drain end existence causes, so that sampling hold circuit has higher defeated
Enter bandwidth.
In order to solve above-mentioned technical problem, the invention provides following technical scheme:
A kind of high if sampling holding circuit for production line analog-digital converter of the present invention, sampling hold circuit includes:
One switched-capacitor circuit, switchs including sampling capacitance and input sample, the input sample being connected in switched-capacitor circuit
Sample and keep in switch one end；Simultaneously
One input driving circuit, completes the detection of the common mode electrical level to differential input signal and common mode electrical level shift function, and output carries
Supply two common mode reset circuits and two grid voltage substrate boostrap circuits；
Two grid voltage substrate boostrap circuits, receive the differential input signal through level shift and the optional clock of two-way respectively, carry out
Grid voltage and the bootstrapping of substrate, the grid end of the input sample switch that output signal is transferred in switched-capacitor circuit and substrate terminal；
Two common mode reset circuits, including common mode reset circuit one and common mode reset circuit two, common mode reset circuit one is keeping rank
Section provides input common mode electrical level for sampling hold circuit, and sample phase disconnects；Common mode reset circuit two is protected for sampling in sample phase
Hold circuit and input common mode electrical level is provided, keep the stage to disconnect；
One main operational amplifier, at sample phase input short circuit, does not receive signal, is keeping the stage to form feedback control loop,
Sampled signal is kept.
Further, sampling capacitance is 6, and input sample switch is 10.
Further, main operational amplifier is high intermediate frequency operational amplifier.
Further, input driving circuit includes: input common mode detection follow circuit, two automatic biasing source followers and two
Individual input follow circuit, the two ends of differential input signal be connected respectively to input common mode detection two inputs of follow circuit, two
The input of individual automatic biasing source follower and two input follow circuits inputs, the outfan of two automatic biasing source followers and
The outfan of two input follow circuits connects four signal node respectively.
Further, input common mode detection follow circuit includes: be connected respectively to two common mode detections at differential input signal two ends
Resistance, two common mode detection electric capacity and a reference voltage drive circuit.
Further, reference voltage drive circuit includes: an auxiliary operation amplifier and an input follow circuit, auxiliary fortune
Calculate amplifier first input end connect reference voltage, the second input of auxiliary operation amplifier and outfan be connected to input with
With circuit, input follow circuit receives input common-mode signal.
Further, the structure of two grid voltage substrate boostrap circuits is identical, and control signal uses biphase complementation not overlap clock signal,
Input signal all connects the outfan of input follow circuit, and Bootstrap output connects two outfans respectively, and substrate bootstrapping output is respectively
Connect two other outfan.
Further, common mode reset circuit one is keeping the stage to be connected with sampling capacitance, provides input common mode for sampling hold circuit
Level, common mode reset circuit one is connected disconnection in sample phase with sampling capacitance, and input common mode electrical level is carried by common mode reset circuit two
Supply；The control signal of common mode reset circuit two is the clock through bootstrapping.
Beneficial effects of the present invention: improve existing charge redistribution formula sampling hold circuit, is kept by the sampling improved
Circuit structure, suppresses the charge leakage issue of wherein input sample switch source and drain end parasitic capacitance, extra by adding
Input sample switch offset parasitic capacitance charge leakage, thus realize increasing the purpose of input signal bandwidth.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing charge redistribution formula sampling hold circuit；
Fig. 2 is the control sequential chart of existing charge redistribution formula sampling hold circuit；
Fig. 3 is the high if sampling holding circuit schematic diagram for production line analog-digital converter that the present invention proposes；
Fig. 4 is that the one of the input driving circuit that the present invention proposes implements schematic diagram；
Fig. 5 is that the one of the input common mode detection follow circuit that the present invention proposes implements schematic diagram；
Fig. 6 is that the one of the grid voltage substrate boostrap circuit that the present invention proposes implements schematic diagram；
Fig. 7 is that the one of the common mode reset circuit 1 that the present invention proposes implements schematic diagram；
Fig. 8 is that the one of the common mode reset circuit 2 that the present invention proposes implements schematic diagram.
Detailed description of the invention
Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the limit to scope
Fixed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to the present invention
Making improvements and modifications, these improve and modification also falls in the range of the claims in the present invention protection.
As it is shown on figure 3, the structured flowchart of the high if sampling holding circuit for production line analog-digital converter proposed for the present invention,
It includes an input driving circuit 1, two grid voltage substrate boostrap circuits 2,3, two common mode reset circuits, a main computing
Amplifier 6, the first to the tenth metal-oxide-semiconductor (switching tube) and the switched-capacitor circuit of the first to the 6th electric capacity composition.Its structure exists
Two sampling capacitances and six input sample switches are added on the basis of existing structure.The input being connected in switched-capacitor circuit
Sample and keep in sampling switch one end, be simultaneously entered drive circuit 1 complete the common mode electrical level to differential input signal detection and
Common mode electrical level shift function, output is supplied to two common mode reset circuits and two grid voltage substrate boostrap circuits 2,3；Two identical
The grid voltage substrate boostrap circuit 2,3 of structure receives the differential input signal through level shift and the optional clock of two-way respectively, carries out
Grid voltage and the bootstrapping of substrate, the grid end of the input sample switch that output signal is transferred in switched-capacitor circuit and substrate terminal；Common mode
Reset circuit 1 is keeping the stage to provide input common mode electrical level for sampling hold circuit, and sample phase disconnects；Common mode reset circuit
25 provide common mode electrical level in sample phase for sampling hold circuit, keep the stage to disconnect；High intermediate frequency operational amplifier 6 is in sampling
Stage input short circuit, does not receive signal, is keeping the stage to form feedback control loop, is keeping sampled signal.
For the pipeline ADC sampling hold circuit carrying out if sampling, except the conducting resistance of input sample switch is non-
Outside linearly impacting sampling hold circuit performance, source and drain end parasitic capacitance and the bulk effect of input sample switch also can be tight
Ghost image rings the performance of sampling hold circuit, and in order to solve the two problem, the grid voltage substrate boostrap circuit that the present invention proposes solves
The distortion that the bulk effect of input sample switch causes, the sampling hold circuit of the improvement that the present invention proposes solves input sample switch
The distortion that causes of source and drain end parasitic capacitance.
As it is shown on figure 3, the annexation of circuit is as follows: differential input signal carries out level shift through input driving circuit 1,
The outfan 11 of input driving circuit 1 is connected to the input Vi of the first grid voltage substrate boostrap circuit 2, input driving circuit 1
Outfan 12 be connected to the input Vi of the second grid voltage substrate boostrap circuit 3, the outfan 13 of input driving circuit 1 connects
To the first metal-oxide-semiconductor M1, the 3rd metal-oxide-semiconductor M3, the 5th metal-oxide-semiconductor M5 and the source of the 7th metal-oxide-semiconductor M7, input
The outfan 14 of drive circuit 1 is connected to the second metal-oxide-semiconductor M2, the 4th metal-oxide-semiconductor M4, the 6th metal-oxide-semiconductor M6 and
The source of eight metal-oxide-semiconductor M8；The drain terminal of the first metal-oxide-semiconductor M1 and the 6th metal-oxide-semiconductor M6 is connected to the 9th metal-oxide-semiconductor M9
Source and the left pole plate of the first electric capacity Cs1, the drain terminal of the second metal-oxide-semiconductor M2 and the 5th metal-oxide-semiconductor M5 be connected to second electricity
Hold left pole plate and the first outfan 41 of common mode reset circuit 1, the 4th metal-oxide-semiconductor M4 and the 7th metal-oxide-semiconductor M7 of Cs2
Drain terminal be connected to source and the left pole plate of the 4th electric capacity Cs4 of the tenth metal-oxide-semiconductor M10, the 3rd metal-oxide-semiconductor M3 and the 8th
The drain terminal of metal-oxide-semiconductor M8 is connected to the left pole plate of the 3rd electric capacity Cs3 and the second outfan 42 of common mode reset circuit 1；
It is the 3rd defeated that the grid end of the first metal-oxide-semiconductor M1 and the 5th metal-oxide-semiconductor M5 is all connected to the second grid voltage substrate boostrap circuit 3
Go out to hold G2, underlayer voltage to be all connected to the 4th outfan B2 of the second grid voltage substrate boostrap circuit 3；Second metal-oxide-semiconductor M2 and
The grid end of the 6th metal-oxide-semiconductor M6 is all connected to the 3rd outfan G2 of the first grid voltage substrate boostrap circuit 2, and underlayer voltage all connects
Receive the 4th outfan B2 of the first grid voltage substrate boostrap circuit 2；3rd metal-oxide-semiconductor M3 and the grid end of the 7th metal-oxide-semiconductor M7
Being all connected to the first outfan G1 of the second grid voltage substrate boostrap circuit 3, underlayer voltage is all connected to the second grid voltage substrate bootstrapping electricity
The second outfan B1 on road 3；The grid end of the 4th metal-oxide-semiconductor M4 and the 8th metal-oxide-semiconductor M8 is all connected to the first grid voltage substrate certainly
Lifting the first outfan G1 of circuit 2, underlayer voltage is all connected to the second outfan B1 of the first grid voltage substrate boostrap circuit 2；
The right pole plate of the first electric capacity Cs1 and the second electric capacity Cs2 is connected, and is connected to the first outfan of common mode reset circuit 25
51, the positive input terminal of main operational amplifier 6 and the left pole plate of the 5th electric capacity Cf1；3rd electric capacity Cs3's and the 4th electric capacity Cs4
Right pole plate is connected, and is connected to the second outfan 52 of common mode reset circuit 25, the negative input end of main operational amplifier 6 and the
The left pole plate of six electric capacity Cf2；
The grid end of the 9th metal-oxide-semiconductor M9 is connected to clock signal clk2, drain terminal be connected to main operational amplifier 6 negative output terminal,
The right pole plate of the 5th electric capacity Cf1 and the source of the 11st metal-oxide-semiconductor M11；The grid end of the tenth metal-oxide-semiconductor M10 is connected to clock
Signal clk2, drain terminal is connected to the positive output end of main operational amplifier 6, the right pole plate of the 6th electric capacity Cf2 and the 11st MOS
The drain terminal of pipe M11；
The first input end ck1 of the first grid voltage substrate boostrap circuit 2, the second input ck2 of the second grid voltage substrate boostrap circuit 3
It is all connected to clock signal clk1 with the grid end of the 11st metal-oxide-semiconductor M11；Second input of the first grid voltage substrate boostrap circuit 2
The first input end ck1 of end ck2 and the second grid voltage substrate boostrap circuit 3 is all connected to control signal ctrl；Wherein clk1 and clk2
Two clock signals are that biphase complementation does not overlap clock signal.
In sample phase, by the configuration of grid voltage substrate boostrap circuit so that switching tube M5, M6, M7, M8 turn off,
M1, M2, M3, M4 turn on, and common mode reset circuit 24 provides common mode input, so that input signal is to sampling
Electric capacity is charged, and differential input signal is sampled in sampling capacitance；Keeping the stage, all input samples switch all closes
Disconnected, differential input signal is transferred in feedback capacity.In the holding stage, the sampling hold circuit of prior art is due to input
The existence of sampling switch source and drain end parasitic capacitance, causes input signal still to have Partial charge to transfer in sampling capacitance, thus makes
Becoming distortion, the present invention switchs by introducing extra input sample, offsets its impact.Such as in the present invention, M1 is keeping rank
The electric charge that section parasitic capacitance introduces, introduces equal electric charge by M7 and eliminates.
As shown in Figure 4, the circuit diagram of the input driving circuit 1 proposed for the present invention.Including one input common mode detection with
Follow circuit 104,105 is inputted with 101, two automatic biasing source followers of circuit 102,103 and two.Circuit as shown in Figure 4
Annexation be: Differential Input positive end signal Vinp be connected to input the first input end of common mode detection follow circuit 101, the
The input of one input follow circuit 104 and the input of the first automatic biasing source follower 102；Differential Input negative terminal signal Vinn
It is connected to input input common mode detection the second input of follow circuit 101, the input and the of the second input follow circuit 105
The input of two automatic biasing source followers 103；The output termination signal node 11 of the first input follow circuit 104, the second input
The output termination signal node 12 of follow circuit 105, the output termination signal node 13 of the first automatic biasing source follower 102, the
The output termination signal node 14 of two automatic biasing source followers 103.
As it is shown in figure 5, the input common mode detection follow circuit structure proposed for the present invention, it includes being connected respectively to Differential Input
Two common mode detection resistance of signal VinP and VinN, two common mode detection electric capacity and a reference voltage drive circuit 1011.
The annexation of circuit is: it is poor that the upper end of the first common mode detection resistance R1 and the top crown of the first common mode detection electric capacity C1 are connected to
Divide and input positive end signal VinP；The upper end of the second common mode detection resistance R2 and the top crown of the second common mode detection electric capacity C2 are connected to
Differential Input negative terminal signal VinN；The lower end of first and second common mode detection resistance R1, R2 is connected and is connected to reference voltage
The outfan of drive circuit 1011；The equal ground connection of bottom crown of first and second common mode detection electric capacity C1, C2.
Reference voltage drive circuit 1011 described in Fig. 5 is by an auxiliary operation amplifier 1012 and an input follow circuit
1013 (common mode follower) is constituted, and an input follow circuit 1013 is made up of 3 NMOS tube, NMOS tube M1 grid
End receives input common-mode signal, and drain terminal connects high level, source and the drain terminal of substrate termination M2 and the end of oppisite phase of operational amplifier,
The grid termination bias voltage Vb1 of M2, drain terminal connects source and the end of oppisite phase of operational amplifier 1012 of M1, and source connects M3's
Drain terminal, the grid termination bias voltage Vb2 of M3, drain terminal connects the source of M2, source ground connection.The present invention follows by increasing input
Circuit, improves driving force.
As shown in Figure 6, the one of the grid voltage substrate boostrap circuit proposed for the present invention implements schematic diagram.Electricity as shown in Figure 6
The annexation on road is:
First can configure grid voltage substrate boostrap circuit 2:
First NMOS tube N1, its grid connects the drain electrode of the second NMOS tube N2, and drain electrode connects high level, and source electrode connects the first electricity
Hold C1；
First electric capacity C1, it can be one or more mos capacitance, the source electrode of termination first NMOS tube N1, one end
Connect the first control signal CLK1；
Second NMOS tube N2, its grid connects the drain electrode of the first NMOS tube N1, and drain electrode connects high level, and source electrode connects the second electricity
Hold C2；
Second electric capacity C2, it can be one or more mos capacitance, the source electrode of termination second NMOS tube N2, one end
Connect the outfan of the first phase inverter；
First phase inverter, its input termination first control signal CLK1, output termination the second phase inverter and the second electric capacity C2's
One end；
3rd NMOS tube N3, its grid connects the grid of the second NMOS tube N2, and drain electrode connects high level, and source electrode connects the 3rd electricity
Hold C3 and the source electrode of the first PMOS P1；
3rd electric capacity C3, it can be one or more mos capacitance, the source electrode of termination the 3rd NMOS tube N3, one end
Connect the drain electrode of the 4th NMOS tube N4；
4th NMOS tube N4, its grid connects the first control signal CLK1, and drain electrode meets the 3rd electric capacity C3, and source electrode connects the 5th
The drain electrode of NMOS tube N5；
5th NMOS tube N5, its grid connects the outfan of the second phase inverter, and drain electrode connects the source electrode of the 4th NMOS tube N4,
Source ground；
Second phase inverter, its input termination first inverter output, the grid end of output termination the 5th NMOS tube N5；
First PMOS P1, its grid connects the first control signal CLK1, and drain electrode connects output end vo utG1, source electrode and substrate
Terminate the source of the 3rd NMOS tube N3；
6th NMOS tube N6, its grid connects the first control signal CLK1, and drain electrode connects the drain electrode of the first PMOS P1,
Source ground；
7th NMOS tube N7, its grid connects the first inverter output, and drain electrode connects the drain electrode of the 4th NMOS tube N4, source
The outfan Vin of pole input follow circuit.
8th NMOS tube N8, its grid meets Bootstrap output end vo utG1, and drain electrode meets input follow circuit outfan Vin,
Source electrode and substrate termination substrate bootstrapping output end vo utB1.
9th NMOS tube N9, its grid connects the first control signal CLK1, and drain electrode connects substrate bootstrapping output end vo utB1, source
Pole ground connection.
Second can configure Bootstrap circuit 3 structure, and to can configure Bootstrap circuit 2 structure with described first identical, wherein controls
Signal processed is the second control signal CLK2, and input signal meets the outfan Vin of input follow circuit, and Bootstrap output connects output
End VoutG2, substrate bootstrapping output meets output end vo utB2.
In boot-strapped switch technology, cause the body that further comprises input sample switch in the factor of switch conduction non-linear resistance
Effect.Change along with input signal due to grid terminal voltage, so producing bulk effect, due to the fact that and substrate is booted, adopting
Sample switch uses NMOS tube, uses twin well process, thus causes the substrate terminal that input sample switchs in sample phase
There is bigger parasitic capacitance, in order to make input signal not affected by parasitic capacitance, thus with the addition of input follow circuit, simultaneously
Input clock signal can be configured.When CLK1 normally works, CLK2 keeps low level, so that part input
Sampling switch is in off state always, to eliminate the impact that the input sample switch source and drain end parasitic capacitance of normal work causes.
As it is shown in fig. 7, the circuit diagram of the common mode reset circuit 1 proposed for the present invention.The annexation of circuit as shown in Figure 7
For: operational amplifier 43 in-phase input end connects Vref1, anti-phase termination outfan, constitutes a unity gain buffer, output
One end of termination two switching tubes M1, M2, the other end of two switching tubes M1, M2 meets sampling capacitance Cs2 and Cs3 respectively
Left pole plate, switching tube M3 two ends connect the left pole plate of sampling capacitance Cs2 and Cs3 respectively, and switch controlled signal is Φ 2.?
Sample phase, common mode reset circuit 1 is connected disconnection with sampling capacitance, and input common mode electrical level is provided by common mode reset circuit 25；
Keeping the stage, common mode reset circuit 1 is connected with sampling capacitance, provides input common mode electrical level for sampling hold circuit.
As shown in Figure 8, the circuit diagram of the common mode reset circuit 25 proposed for the present invention.The annexation of circuit as shown in Figure 8
For: operational amplifier 53 in-phase input end meets Vref1, anti-phase termination outfan, and output terminates two switching tubes M1, M2
One end, the other end of two switching tubes M1, M2 connects the right pole plate of sampling capacitance Cs2 and Cs3, switching tube M3 two ends respectively
Connecing the right pole plate of sampling capacitance Cs2 and Cs3 respectively, switch controlled signal is the Φ 1p through bootstrapping.In sample phase, altogether
Mould reset circuit 1 is connected disconnection with sampling capacitance, and input common mode electrical level is provided by common mode reset circuit 25；Keeping the stage,
Common mode reset circuit 1 is connected with sampling capacitance, provides input common mode electrical level for sampling hold circuit.
In the present invention, owing to the control signal of common mode reset circuit 25 is the clock through bootstrapping, so reducing sample phase
To the fringe time in holding stage, thus reduce setting up the time of amplifier, improve speed.
Claims (8)
1. the high if sampling holding circuit for production line analog-digital converter, it is characterised in that described sampling hold circuit
Including:
One switched-capacitor circuit, switchs including sampling capacitance and input sample, the input sample being connected in switched-capacitor circuit
Sample and keep in switch one end；Simultaneously
One input driving circuit (1), completes the detection of the common mode electrical level to differential input signal and common mode electrical level shift function, defeated
Go out to be supplied to two common mode reset circuits and two grid voltage substrate boostrap circuits (2,3)；
Two grid voltage substrate boostrap circuits (2,3), receive the differential input signal through level shift and the optional clock of two-way respectively,
Carry out the bootstrapping of grid voltage and substrate, the grid end of the input sample switch that output signal is transferred in switched-capacitor circuit and substrate terminal；
Two common mode reset circuits, including common mode reset circuit one (4) and common mode reset circuit two (5), common mode reset circuit one
(4) keeping the stage to provide input common mode electrical level for sampling hold circuit, sample phase disconnects；Common mode reset circuit two (5)
There is provided input common mode electrical level in sample phase for sampling hold circuit, keep the stage to disconnect；
One main operational amplifier (6), at sample phase input short circuit, does not receive signal, forms feedback loop keeping the stage
Road, keeps sampled signal.
High if sampling holding circuit for production line analog-digital converter the most according to claim 1, it is characterised in that
Described sampling capacitance is 6, and input sample switch is 10.
High if sampling holding circuit for production line analog-digital converter the most according to claim 1, it is characterised in that
Described main operational amplifier (6) is high intermediate frequency operational amplifier.
High if sampling holding circuit for production line analog-digital converter the most according to claim 1, it is characterised in that
Described input driving circuit (1) including: input common mode detection follow circuit (101), two automatic biasing source followers (102,
103) and two inputs follow circuit (104,105), the two ends of differential input signal are connected respectively to input common mode detection and follow
Two inputs of circuit (101), the input of two automatic biasing source followers (102,103) and two input follow circuits
The input of (104,105), the outfan of two automatic biasing source followers (102,103) and two input follow circuit (104,
105) outfan connects four signal node respectively.
High if sampling holding circuit for production line analog-digital converter the most according to claim 4, it is characterised in that
Described input common mode detection follow circuit (101) including: be connected respectively to differential input signal two ends two common modes detection resistance,
Two common mode detection electric capacity and a reference voltage drive circuit (1011).
High if sampling holding circuit for production line analog-digital converter the most according to claim 5, it is characterised in that
Described reference voltage drive circuit (1011) including: an auxiliary operation amplifier (1012) and input follow circuit (1013),
The first input end of auxiliary operation amplifier (1012) connects reference voltage, the second input of auxiliary operation amplifier (1012)
End and outfan are connected to input follow circuit (1013), and input follow circuit (1013) receives input common-mode signal.
High if sampling holding circuit for production line analog-digital converter the most according to claim 1, it is characterised in that
The structure of said two grid voltage substrate boostrap circuit (2,3) is identical, and control signal uses biphase complementation not overlap clock signal,
Input signal all connects the outfan of input follow circuit, and Bootstrap output connects two outfans respectively, and substrate bootstrapping output is respectively
Connect two other outfan.
High if sampling holding circuit for production line analog-digital converter the most according to claim 1, it is characterised in that
Described common mode reset circuit one (4) is keeping the stage to be connected with sampling capacitance, provides input common mode electrical level for sampling hold circuit,
Common mode reset circuit one (4) is connected disconnection in sample phase with sampling capacitance, and input common mode electrical level is by common mode reset circuit two (5)
There is provided；The control signal of common mode reset circuit two (5) is the clock through bootstrapping.
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| CN109194330A (en) * | 2018-08-27 | 2019-01-11 | 中国电子科技集团公司第二十四研究所 | buffer circuit and buffer |
| CN111147101A (en) * | 2019-12-31 | 2020-05-12 | 龙迅半导体（合肥）股份有限公司 | Data switch and data transmission system |
| CN111884657A (en) * | 2020-08-04 | 2020-11-03 | 中国电子科技集团公司第二十四研究所 | Sample-and-hold circuit and method |
| CN112751537A (en) * | 2020-05-26 | 2021-05-04 | 上海韬润半导体有限公司 | Linear amplifying circuit and analog-to-digital conversion device comprising same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108427030A (en) * | 2017-02-13 | 2018-08-21 | 珠海全志科技股份有限公司 | A kind of signal energy detection circuit |
| CN107733432A (en) * | 2017-11-10 | 2018-02-23 | 中国电子科技集团公司第五十八研究所 | The charge-domain pipelined ADC common mode charges error calibration system of high accuracy |
| CN107733432B (en) * | 2017-11-10 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | Charge-domain pipelined ADC common mode charge error calibration system in high precision |
| CN109194330A (en) * | 2018-08-27 | 2019-01-11 | 中国电子科技集团公司第二十四研究所 | buffer circuit and buffer |
| CN109194330B (en) * | 2018-08-27 | 2020-08-11 | 中国电子科技集团公司第二十四研究所 | Buffer circuit and buffer |
| CN111147101A (en) * | 2019-12-31 | 2020-05-12 | 龙迅半导体（合肥）股份有限公司 | Data switch and data transmission system |
| CN112751537A (en) * | 2020-05-26 | 2021-05-04 | 上海韬润半导体有限公司 | Linear amplifying circuit and analog-to-digital conversion device comprising same |
| CN112751537B (en) * | 2020-05-26 | 2024-04-19 | 上海韬润半导体有限公司 | Linear amplifying circuit and analog-to-digital conversion device comprising same |
| CN111884657A (en) * | 2020-08-04 | 2020-11-03 | 中国电子科技集团公司第二十四研究所 | Sample-and-hold circuit and method |
| CN111884657B (en) * | 2020-08-04 | 2024-03-12 | 中国电子科技集团公司第二十四研究所 | Sample hold circuit and method |
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