CN106208982A - A kind of trsanscondutance amplifier imbalance based on output electric current storage eliminates structure - Google Patents
A kind of trsanscondutance amplifier imbalance based on output electric current storage eliminates structure Download PDFInfo
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- CN106208982A CN106208982A CN201610565518.9A CN201610565518A CN106208982A CN 106208982 A CN106208982 A CN 106208982A CN 201610565518 A CN201610565518 A CN 201610565518A CN 106208982 A CN106208982 A CN 106208982A
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- switch
- nmos tube
- imbalance
- trsanscondutance amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
Abstract
The invention discloses a kind of trsanscondutance amplifier imbalance based on output electric current storage and eliminate structure, eliminate structure including trsanscondutance amplifier, an electric capacity C1 and output offset current；Trsanscondutance amplifier is a classical trsanscondutance amplifier, and electric capacity C1 is connected between NMOS tube MN5 and the grid of MN6；Output offset current eliminates structure and includes the switch switch SW4 between SW3, positive-negative input end on the switch SW2 on positive input branch road, negative sense input branch road and the switch SW5 on negative sense input channel；Switch SW3 uses the construction of switch that low electric charge injects.Under conditions of input short circuit, first pass through output electric current storage organization and offset current is carried out samples storage, afterwards when normally working, do subtraction by the signal code when offset current prestored and work, eliminate composition of lacking of proper care in signal.
Description
Technical field
The present invention relates to field of analog integrated circuit, can be used for sensor and digital and analog mixed signal particularly to one
In circuit, trsanscondutance amplifier output current imbalance eliminates structure.
Background technology
Various kinds of sensors is by by the optical signal in nature, acoustical signal, and the various signals such as pressure signal are converted into telecommunications
Number, after late-class circuit processes, become the manageable signal of telecommunication of people, substantially increase people's knowledge of natural environment, nature remodeling
Ability.And the signal of telecommunication that sensor signal reading field initially obtains may often be such that analogue signal, need through suitable circuit
Processing amplification can be by subsequent conditioning circuit identification.Therefore noise reduction and amplification method to ultra-weak electronic signal are always sensor and read
Circuit studies focus.
In SOI diode type infrared image detection device, diode operation is under positively biased state, and optical system is by infrared spoke
Penetrating and be delivered to detector surface, cause detector temperature to raise, the feature utilizing the IV characteristic of diode to vary with temperature obtains
Voltage change Δ V, as shown in Figure 1.In reading circuit, input stage often uses trsanscondutance amplifier module, is first transformed into by Δ V
Current signal Δ I, then be integrated, it is thus achieved that the processed signal after amplification, eventually pass through analog-digital converter and quantify output.
But initially the voltage signal Δ V of acquisition is fainter, relative signal Δ V, input stage trsanscondutance amplifier self is lacked of proper care
Voltage is relatively big, can reduce actual signal composition proportion in subsequent conditioning circuit out-put dynamic range, cause circuit output area and
Noise characteristic degradation.Accordingly, it would be desirable to use trsanscondutance amplifier imbalance removing method, reduce trsanscondutance amplifier imbalance, promote
Circuit performance.
Conventional circuit structure, the deficiency existed mainly has following two:
1. tradition trsanscondutance amplifier structure does not the most possess imbalance elimination function, and offset current occupies relatively in output electric current
Big proportion, actual signal constituent reduction in out-put dynamic range, reduce signal to noise ratio.
2. tradition imbalance eliminates the switch-charge injection phenomenon in structure, can affect crucial charge conservation node imbalance storage
Precision is bigger on imbalance eradicating efficacy impact.
Summary of the invention
The deficiency existed for prior art, in order to improve infrared reading circuit performance, it is achieved trsanscondutance amplifier output is lost
Adjusting circuit for eliminating, the present invention proposes a kind of trsanscondutance amplifier imbalance based on output electric current storage and eliminates structure, traditional
Consider offset current on the basis of classical trsanscondutance amplifier, and switch is improved, further reduce switch-charge note
Enter the impact of phenomenon.Input voltage signal Δ V can be transformed into current signal Δ I by the circuit structure that the present invention proposes, and
Eliminate offset current composition in current signal Δ I.
In order to solve above-mentioned technical problem, a kind of based on output electric current storage the trsanscondutance amplifier imbalance that the present invention proposes
Eliminate structure, eliminate structure including Differential Input trsanscondutance amplifier, an imbalance storage electric capacity C1 and output offset current；Described
Differential Input trsanscondutance amplifier comprises tail current PMOS MP5, and the PMOS input being made up of PMOS MP1 and MP2PMOS pipe is right
Pipe, PMOS MP3 of cascade and PMOS MP4, by NMOS tube MN3, NMOS tube MN4, NMOS tube MN5 and NMOS tube MN6
The load pipe that cascade connects；The described imbalance storage left pole plate of electric capacity C1 connects the grid of NMOS tube MN5, and described imbalance stores
The right pole plate of electric capacity C1 connects the grid of NMOS tube MN6；Described output offset current eliminates structure and includes four switches, four switches
Including the switch SW2 on positive input branch road, negative sense input the switch SW4 between SW3, positive-negative input end of the switch on branch road and
Switch SW5 on negative sense input channel；Described switch SW2 connects the drain electrode of NMOS tube MN3 and the grid of NMOS tube MN5 and protects
Hold normally on；Described switch SW3 connects drain electrode and the grid of MN6 of NMOS tube MN4；Switch SW4 connect PMOS MP1 and
The grid of MP2PMOS pipe；Switch SW5 connects Differential Input trsanscondutance amplifier negative input and negative end input signal VIN-；
Described switch SW3 uses the construction of switch that low electric charge injects, and the construction of switch that described low electric charge injects includes that single tube switchs NMOS
Pipe MN7, electric charge injecting compensating NMOS tube MN8, buffer BUF1 and phase inverter INV1；Wherein, described NMOS tube MN7 and compensation
NMOS tube MN8 size ratio is classified as 2:1, buffer BUF1 and phase inverter INV1 and all uses low-voltage VL to power.
Present invention trsanscondutance amplifier imbalance based on output electric current storage eliminates structure, and wherein, the running voltage of circuit is
5V, low-voltage VL that in the construction of switch that described low electric charge injects, buffer BUF1 and phase inverter INV1 is used is 3.3V, protects
Card switch NMOS tube MN7 can be opened and be turned on.
Use circuit structure of the present invention under conditions of input short circuit, first pass through output electric current storage organization to imbalance electricity
Stream carries out samples storage, afterwards when normally working, by the letter comprising imbalance when the offset current prestored and work
Number electric current does subtraction, eliminates composition of lacking of proper care in signal.Compared with prior art, beneficial effects of the present invention is as follows:
1, by the way of output offset current storage, trsanscondutance amplifier is carried out imbalance to eliminate, improve useful signal and exist
Proportion in output electric current, effect is notable.
2, injected electric charge by switch and affected to reduce crucial charge conservation node, by improving construction of switch, employing
A kind of low electric charge injects switch and realizes injecting switch channel electric charge and the suppression of clock feedthrough phenomenon, reduce further imbalance
The error of storage organization, improves imbalance eradicating efficacy.
3, the present invention only need to carry out simple structural change to traditional circuit and can realize, and does not increase circuit complicated
Degree, is not significantly increased extra power consumption and area overhead, has the highest practical value.
Accompanying drawing explanation
Fig. 1 is infrared image sensor input stage trsanscondutance amplifier operation principle schematic diagram；
Fig. 2 is the electric current storage ultimate principle that the present invention uses；
Fig. 3 is tradition transconductance amplifier circuit figure；
Fig. 4 is the circuit diagram that the trsanscondutance amplifier imbalance based on output electric current storage that the present invention proposes eliminates structure；
Fig. 5 is circuit of the present invention imbalance storage status circuit figure；
Fig. 6 is the normal circuit operation status circuit figure that the present invention proposes；
Fig. 7 is the construction of switch that the novel suppression channel charge that the present invention proposes injects；
Classics trsanscondutance amplifier output offset current distribution when Fig. 8 is to eliminate without imbalance；
After Fig. 9 is the imbalance removing method using present invention proposition, output offset current distribution；
Figure 10 is, after the novel low channel charge of employing injects construction of switch realization imbalance elimination, to export offset current distribution.
Detailed description of the invention
Below in conjunction with detailed description of the invention, the present invention is described in further detail.
The mentality of designing of the present invention is to use imbalance storage mode for output current imbalance storage, its ultimate principle such as Fig. 2
Shown in, first Fig. 2 breaker in middle SW1 turns on, and current source I1 drives NMOS tube MN1 and NMOS tube MN2, stores at electric capacity C1 top crown
Voltage V1, on path, electric current is I1.Switch SW1 disconnects afterwards, and current source I1 becomes load RL, now electric capacity C1 top crown electric charge
Conservation, still keeping voltage is V1, and on path, electric current is maintained as I1, i.e. on load RL, electric current is I1.
If traditional classical trsanscondutance amplifier is not as it is shown on figure 3, consider offset current, PMOS MP1 electric current is i, NMOS
Pipe MN5 electric current is i, and the electric current that NMOS tube MN6 mirror image MN5 obtains is also i, and PMOS MP2 electric current is-i, and final output electric current is
2i.If positively and negatively there is offset current ios on branch road, PMOS MP1 electric current is i+ios, and NMOS tube MN5 electric current is i+
Ios, the electric current that NMOS tube MN6 mirror image MN5 obtains is also i+ios, and PMOS MP2 electric current is-i-ios, and final output electric current is
2i+2ios, contains positively and negatively branch road offset current sum 2ios.
A kind of based on output electric current storage the trsanscondutance amplifier imbalance that the present invention proposes eliminates structure, including Differential Input
Trsanscondutance amplifier, an imbalance storage electric capacity C1 and the output imbalance being made up of four switches (switch SW2, SW3, SW4 and SW5)
Electric current eliminates structure.
As shown in Figure 4, described Differential Input trsanscondutance amplifier comprises tail current PMOS MP5, by PMOS MP1 and
The PMOS that MP2PMOS pipe is constituted inputs pipe, and PMOS MP3 of cascade and PMOS MP4, by NMOS tube MN3, NMOS tube
The load pipe that MN4, NMOS tube MN5 and NMOS tube MN6 cascade connect；The described imbalance storage left pole plate of electric capacity C1 connects NMOS
The grid of pipe MN5, the described imbalance storage right pole plate of electric capacity C1 connects the grid of NMOS tube MN6.
Described output offset current eliminates structure and includes that four switches, four switches include the switch on positive input branch road
Switch switch SW4 between SW3, positive-negative input end on SW2, negative sense input branch road and the switch SW5 on negative sense input channel.
Described switch SW2 connects the drain electrode of NMOS tube MN3 and the grid of NMOS tube MN5 and keeps normally on, is used for and switch
SW3 mates, and reduces positive and negative two flow adaptation errors.Described switch SW3 connects drain electrode and the grid of MN6 of NMOS tube MN4,
Imbalance memory phase conducting, inputs negative sense branch current corresponding voltage value and is stored in the imbalance storage right pole plate of electric capacity C1, switch
SW3 disconnects at working stage, now imbalance storage electric capacity C1 right plate charge conservation.Switch SW4 connect PMOS MP1 and
The grid of MP2PMOS pipe, in imbalance memory phase switch SW4 conducting, Differential Input trsanscondutance amplifier input is shorted to VIN+,
In normal work stage, switch SW4 disconnects.Switch SW5 connects Differential Input trsanscondutance amplifier negative input and negative end is defeated
Entering signal VIN-, at imbalance memory phase, switch SW5 disconnects, and cuts off VIN-and the connection of negative input, and normally work rank
Section, switch SW5 Guan Bi, VIN+ and VIN-connects Differential Input trsanscondutance amplifier positive-negative input end respectively.Imbalance storage sampling and
Normal operating conditions is respectively shown in Fig. 5 and Fig. 6.
Imbalance storage method is used to have a problem that when eliminating trsanscondutance amplifier offset current.The electric charge note that switch causes
Enter and can reduce storage precision with clock feed-through effect, affect calibration result.And the switch shadow that in circuit, charge conservation node is subject to
Ringing maximum, for foregoing circuit structure, the imbalance storage right pole plate of electric capacity C1 is connected with NMOS tube MN6 grid, normal circuit operation
Time, this node is charge conservation node, needs to be optimized switch SW3, and other switches (switch SW2, SW4 and SW5) use
Regular tap structure.The present invention proposes a kind of Novel switch structure electric charge injection and clock feedthrough are pressed down
System, switch SW3 uses the construction of switch that this novel low electric charge injects, as it is shown in fig. 7, the switch knot that described low electric charge injects
Structure includes that single tube switchs NMOS tube MN7, electric charge injecting compensating NMOS tube MN8, buffer BUF1 and phase inverter INV1；Wherein, institute
Stating NMOS tube MN7 and compensation NMOS tube MN8 size ratio is classified as 2:1, NMOS tube MN7 size is the twice of NMOS tube MN8.
As shown in Figure 7, it is assumed that during clock CLK upset, in NMOS tube MN7, the electric charge of gate capacitance storage has half to transfer to
B point, then electric chargeAfter a phase inverter time delay, clock CKN overturns, NMOS
The electric charge that pipe MN8 absorbs from B pointIn order to make electric charge △ q1 and the △ q2 that B point changes
It is completely counterbalanced by, makes W8=0.5W7, L8=L7.At this point it is possible to be completely counterbalanced by clock feed-through effect.
It practice, the hypothesis of point electric charge such as NMOS tube MN7 source electrode and drain electrode is the most invalid, so using this side
The effect that method eliminates electric charge injection is the most very good.Notice that △ q1, △ q2 are respectively and VCK、VCKNIt is directly proportional.Therefore fall is used
Low VCK、VCKNMethod can reduce △ q1, △ q2, thus realize the effect suppressing channel charge to inject.By subtracting in the present invention
Minibuffer device BUF1 and the method for phase inverter INV1 supply voltage, reduce VCK、VCKN, significantly reduce channel charge injection effect
Impact.In the present invention, buffer BUF1 and phase inverter INV1 all uses low-voltage VL to power, and circuit voltage is 5V, should
Low-voltage VL is according to switch ends virtual voltage value 3.3V, it is ensured that switch NMOS tube MN7 can be opened and be turned on.
Use the present invention to propose a kind of trsanscondutance amplifier imbalance elimination structure based on output electric current storage and realize mutual conductance
Amplifier imbalance removing method, by imbalance memory phase, exists offset current on circuit node, in normal work stage,
Offset current is deducted from signal code.
Imbalance memory phase circuit structure, as it is shown in figure 5, now switch SW2 holding normal open, switch SW3 conducting, switchs SW4
Conducting, switch SW5 disconnects.Now, trsanscondutance amplifier input short circuit, applied signal voltage is 0, positive input branch road imbalance electricity
Stream is ios, and negative sense input branch road offset current is-ios.Now, the imbalance storage left polar plate voltage of electric capacity C1 is VGS5=V1+
VOS, wherein, V1 is free from the grid voltage of NMOS tube MN5 of imbalance composition, and VOS is the NMOS tube MN5 grid electricity that imbalance causes
Pressure variable quantity, the imbalance storage right polar plate voltage of electric capacity C1 is VGS6=V1 VOS, and imbalance storage electric capacity C1 stores offset voltage
2VOS.NMOS tube MN5 and NMOS tube MN6 transconductance value are gm, then i+ios=gm (V1+VOS), i-ios=gm (V1-VOS), its
In, i is trsanscondutance amplifier quiescent current composition, and ios is the current component that imbalance causes.
As shown in Figure 6, now switch SW2 keeps normal open, switch SW3 to disconnect to normal work stage circuit structure diagram, switch
SW4 disconnects, and switch SW5 conducting, now amplifier positive-negative input end exists signal voltage 2Vsig, normal phase input end PMOS MP1
Electric current is
ID1=i+ios+ △ i (1)
Wherein, i is trsanscondutance amplifier quiescent current composition, and ios is the current component that imbalance causes, and △ i is that mutual conductance is amplified
The signal code that device input voltage signal produces.
Negative-phase input PMOS MP2 electric current is
ID2=i-ios-△ i (2)
Now, the imbalance storage left polar plate voltage of electric capacity C1 becomes VGS5=V1+VOS+ △ V, △ V is due to trsanscondutance amplifier
The change of the NMOS tube MN5 grid voltage that input voltage signal causes.Charge conservation on imbalance storage electric capacity C1, imbalance storage electricity
Holding about C1 polar plate voltage difference keeps 2VOS constant, consistent with imbalance memory phase.Under imbalance storage electric capacity C1 drives, imbalance
The storage right polar plate voltage of electric capacity C1 becomes VGS6=V1-VOS+ △ V.Owing to signal is less, the mutual conductance change caused is less, permissible
Think that NMOS tube MN5 and the mutual conductance of NMOS tube MN6 are the most constant, for gm.Then NMOS tube MN5 and NMOS tube MN6 power on stream respectively
ID5=gm × VGS5=gm × (V1+VOS+ △ V)=i+ios+ △ i (3)
ID6=gm × VGS6=gm × (V1-VOS+ △ V)=i-ios+ △ i (4)
From formula (2) and formula (4), final IOUT output electric current is
IOUT=ID6-ID2=2 △ i (5)
By the imbalance removing method of circuit realiration of the present invention, make output electric current does not contains offset current composition.
During real work, switch channel electric charge injects the effect also eliminated imbalance and produces impact.In work process, crucial
Node is the grid of NMOS tube MN6, and this node is charge conservation node, if subjected to the impact that switch channel electric charge injects, meeting
Charge conservation is caused to be false, impact imbalance eradicating efficacy.Accordingly, it would be desirable to this node related device is carried out special handling.Open
Closing the construction of switch that SW3 uses the low electric charge proposed in the present invention to inject, when CLK rising edge arrives, switching tube NMOS tube MN7 is led
Logical, now without the concern for getting at electric charge injection；When CLK trailing edge arrives, switching tube NMOS tube MN7 disconnects, and produces node B
Channel charge injects.Now CKN rising edge arrives, and absorbs a part of switching tube NMOS tube MN7 note by compensating pipe NMOS tube MN8
Enter the electric charge to B point, it can be difficult to all absorb.By reducing the voltage of CK and CKN, further reduce the electric charge of remnants.
When not carrying out imbalance elimination, during input short circuit, output current imbalance is distributed as shown in Figure 8, and the most about 1uA loses
Adjust electric current；After using regular tap to carry out imbalance elimination, output current imbalance distribution, as it is shown in figure 9, at most about 6nA, is adopted
After carrying out imbalance elimination with the low electric charge injection construction of switch proposed in the present invention, output current imbalance is distributed such as Figure 10 institute
Show, the most about 3.5nA.Imbalance removing method and the low electric charge injection construction of switch used that the present invention realizes can be real
Now good effect.
Although above in conjunction with figure, invention has been described, but the invention is not limited in above-mentioned specific embodiment party
Formula, above-mentioned detailed description of the invention is only schematic rather than restrictive, and those of ordinary skill in the art is at this
Under bright enlightenment, without deviating from the spirit of the invention, it is also possible to make many variations, these belong to the guarantor of the present invention
Within protecting.
Claims (2)
1. trsanscondutance amplifier imbalance based on output electric current storage eliminates a structure, including Differential Input trsanscondutance amplifier, institute
State Differential Input trsanscondutance amplifier and comprise tail current PMOS MP5, the PMOS input being made up of PMOS MP1 and MP2PMOS pipe
To pipe, PMOS MP3 of cascade and PMOS MP4, by NMOS tube MN3, NMOS tube MN4, NMOS tube MN5 and NMOS tube
The load pipe that MN6 cascade connects；It is characterized in that:
Transconductance amplifier circuit also includes that an imbalance storage electric capacity C1 and output offset current eliminate structure；
The described imbalance storage left pole plate of electric capacity C1 connects the grid of NMOS tube MN5, and the described imbalance storage right pole plate of electric capacity C1 connects
The grid of NMOS tube MN6；
Described output offset current eliminates structure and includes four switches, four switches include positive input the switch SW2 on branch road,
Switch switch SW4 between SW3, positive-negative input end on negative sense input branch road and the switch SW5 on negative sense input channel；Described
Switch SW2 connects the drain electrode of NMOS tube MN3 and the grid of NMOS tube MN5 and keeps normally on；Described switch SW3 connects
The drain electrode of NMOS tube MN4 and the grid of MN6；Switch SW4 connects PMOS MP1 and the grid of MP2PMOS pipe；Switch SW5 connects
Differential Input trsanscondutance amplifier negative input and negative end input signal VIN-；
Described switch SW3 uses the construction of switch that low electric charge injects, and the construction of switch that described low electric charge injects includes that single tube switchs
NMOS tube MN7, electric charge injecting compensating NMOS tube MN8, buffer BUF1 and phase inverter INV1；Wherein, described NMOS tube MN7 and benefit
Repay NMOS tube MN8 size ratio to be classified as 2:1, buffer BUF1 and phase inverter INV1 and all use low-voltage VL to power.
The most according to claim 1, trsanscondutance amplifier imbalance based on output electric current storage eliminates structure, it is characterised in that: electricity
The running voltage on road is 5V, the low electricity that in the construction of switch that described low electric charge injects, buffer BUF1 and phase inverter INV1 is used
Pressure VL is 3.3V.
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| CN201610565518.9A CN106208982B (en) | 2016-07-15 | 2016-07-15 | A kind of trsanscondutance amplifier imbalance elimination structure based on output electric current storage |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107769733A (en) * | 2017-10-25 | 2018-03-06 | 天津大学 | A kind of switched capacitor amplifier imbalance eliminates structure |
| CN108092628A (en) * | 2017-12-12 | 2018-05-29 | 上海集成电路研发中心有限公司 | A kind of operational amplifier and amplifier circuit that there is imbalance to eliminate structure |
| CN109639261A (en) * | 2018-11-16 | 2019-04-16 | 无锡芯朋微电子股份有限公司 | Comparison circuit, delay removing method |
| CN112365853A (en) * | 2020-11-13 | 2021-02-12 | 昂宝电子（上海）有限公司 | Multi-path LED backlight system and constant current control circuit and method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7782243B1 (en) * | 2009-03-11 | 2010-08-24 | Windtop Technology Corp. | Direct capacitance-to-digital converter |
| CN102789261A (en) * | 2012-06-18 | 2012-11-21 | 天津大学 | Current source circuit used for complementary metal-oxide-semiconductor transistor (CMOS) image sensor and insensitive to power supply voltage drop |
| CN103095302A (en) * | 2012-12-19 | 2013-05-08 | 天津大学 | Sampling holding circuit applied to high-speed high-precision circuit |
| CN104270152A (en) * | 2014-10-13 | 2015-01-07 | 中国电子科技集团公司第五十八研究所 | PVT insensitive common mode charge control device for charge coupling assembly line analog-digital converter |
-
2016
- 2016-07-15 CN CN201610565518.9A patent/CN106208982B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7782243B1 (en) * | 2009-03-11 | 2010-08-24 | Windtop Technology Corp. | Direct capacitance-to-digital converter |
| CN102789261A (en) * | 2012-06-18 | 2012-11-21 | 天津大学 | Current source circuit used for complementary metal-oxide-semiconductor transistor (CMOS) image sensor and insensitive to power supply voltage drop |
| CN103095302A (en) * | 2012-12-19 | 2013-05-08 | 天津大学 | Sampling holding circuit applied to high-speed high-precision circuit |
| CN104270152A (en) * | 2014-10-13 | 2015-01-07 | 中国电子科技集团公司第五十八研究所 | PVT insensitive common mode charge control device for charge coupling assembly line analog-digital converter |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107769733A (en) * | 2017-10-25 | 2018-03-06 | 天津大学 | A kind of switched capacitor amplifier imbalance eliminates structure |
| CN107769733B (en) * | 2017-10-25 | 2020-10-23 | 天津大学 | Offset cancellation circuit of switched capacitor amplifier |
| CN108092628A (en) * | 2017-12-12 | 2018-05-29 | 上海集成电路研发中心有限公司 | A kind of operational amplifier and amplifier circuit that there is imbalance to eliminate structure |
| CN109639261A (en) * | 2018-11-16 | 2019-04-16 | 无锡芯朋微电子股份有限公司 | Comparison circuit, delay removing method |
| CN109639261B (en) * | 2018-11-16 | 2022-12-30 | 无锡芯朋微电子股份有限公司 | Comparison circuit and delay eliminating method |
| CN112365853A (en) * | 2020-11-13 | 2021-02-12 | 昂宝电子（上海）有限公司 | Multi-path LED backlight system and constant current control circuit and method thereof |
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| Publication number | Publication date |
|---|---|
| CN106208982B (en) | 2019-01-18 |
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