CN102789261A - Current source circuit used for complementary metal-oxide-semiconductor transistor (CMOS) image sensor and insensitive to power supply voltage drop - Google Patents

Abstract

The invention relates to the design field of integrated circuits of microelectronics and aims at providing stable current bias not related with power supply voltage drop and utilizing the current bias in a high definition CMOS image sensor to improve characteristics of the sensor. The technical scheme is that a current source circuit used for the CMOS image sensor and insensitive to the power supply voltage drop comprises a capacitor Cn1, a capacitor Cn2, a transistor Mn1, a transistor Mn2, a transistor Mn3, a switch S1 and a switch S2. When S1 is closed, and S2 is opened, an upper pole plate on the capacitor Cn1 is connected onto a reference power supply VDD_ref, a lower pole plate of the capacitor Cn1 is connected onto a grid electrode of a transistor M0, an upper pole plate of Cn2 is connected onto a power supply VDD_power of a power supply source unit on the nth list, and a lower pole plate of Cn2 is connected onto a grid electrode of the transistor Mn1. When S1 is opened, and S2 is closed, the positions of the capacitor Cn1 and the capacitor Cn2 are exchanged. The current source circuit is mainly applied to design manufacture of integrated circuits.

Description

Be used for cmos image sensor to the insensitive current source circuit of power voltage-drop

Technical field

The present invention relates to microelectronic IC design field, relate in particular to a kind of be used for cmos image sensor to the insensitive current source circuit of power voltage-drop.

Background technology

At present, (High-Definition Television, the development of high resolution CMOS image sensor has been quickened in development HDTV) to HDTV.In the high resolution CMOS image sensor chip, the length that power supply and the metal connecting line on ground can be very, this will introduce bigger voltage drop (IR-Drop) between power supply and load unit.General cmos image sensor can adopt the framework among Fig. 1; Every row pixel adopts a current source to setover and to the source follower in the pixel working current is provided; This current source generally realizes that through nmos pass transistor the grid voltage Vbias of this nmos pass transistor is determined by current mirror in the prior art.The current mirror grid that the NMOS pipe constitutes connects current offset voltage, source ground, and drain electrode connects the output terminal of pixel, for pixel provides current offset.Between the signal reading duration, the biased electrical of pixel fails to be convened for lack of a quorum and flows to ground VSS from power vd D, and the dead resistance in the ground wire can cause the voltage on the ground wire to begin to rise from VSS.Therefore although all current source nmos transistors all use identical grid voltage, the electric current that reduces nmos pass transistor is provided of the voltage Vgs between the grid source can reduce so.This problem also exists in the row parallel read-out circuit of high resolution CMOS image sensor.The reduction of current source bias current can cause using the speed of the circuit of this current source to produce deviation with gain, and then worsens the image quality of imageing sensor, will be more serious for this deterioration of the high resolution CMOS image sensor of high frame frequency.

Summary of the invention

The present invention is intended to overcome the deficiency of prior art; Provide and the irrelevant stable current offset of power voltage-drop, it is applied in the characteristic that can promote sensor in the high definition cmos image sensor, for achieving the above object; The technical scheme that the present invention takes is; Be used for cmos image sensor to the insensitive current source circuit of power voltage-drop, comprise the current mirroring circuit of forming by transistor M0, also comprise capacitor C n1, capacitor C n2, transistor Mn1, Mn2, Mn3; Switch S 1, S2, switch S 1 is the linkage groups switch, switch S 2 also is the linkage groups switch; When the S1 closure, when S2 opened, the top crown of capacitor C n1 was connected on the reference power source VDD_ref; Bottom crown is connected on the grid of transistor M0; Meanwhile, the top crown of Cn2 is connected on the power vd D_power of n row current source cell, and its bottom crown is connected on the grid of transistor Mn1; When S1 opens, when S2 was closed, the location swap of capacitor C n1 and Cn2, capacitor C n1 had connected source electrode and the grid of transistor Mn1, source electrode and the grid of capacitor C n2 connection transistor M0; Transistor Mn1 source electrode connects power vd D_power; Transistor Mn1 drain electrode connects transistor Mn2 source electrode, transistor Mn2 source electrode, grid short circuit, and transistor Mn2 drain electrode connects ground VSS; Export behind the current mirror of current mirror that transistor Mn2 and Mn3 constitute transistor Mn1.

The breadth length ratio of transistor M0 is 60: 1, and the breadth length ratio of transistor Mn1 is 6: 1, and the working current of M0 is 60uA, and then the working current of Mn1 is 6uA, and the breadth length ratio of transistor Mn2 and Mn3 is 2: 1, and Mn3 can provide stable 6uA bias current; Capacitor C n1 and Cn2 realize that through mos capacitance its appearance value is 500fF.

Capacitor C n1, capacitor C n2 appearance value than the grid of transistor Mn1 over the ground stray capacitance CP go out greatly more than the one magnitude.

Switch S 1, S2 be in two foldings under the control of clock that do not overlap mutually, makes source electrode that is connected to transistor Mn1 that capacitor C n1 and Cn2 replace and grid to keep stable gate source voltage.

Technical characterstic of the present invention and effect:

Guaranteed that through two electric capacity that receive clock control the gate source voltage of current source transistor keeps constantly,, and then guaranteed that electric current that current source transistor provides does not receive the influence of voltage voltage drop with supply independent.When supply voltage from normal value to reducing by 30% when changing; The variation contrast of the current source output current value that current source that the present invention describes and prior art provide is as shown in Figure 3; It is thus clear that; When the supply voltage current source that prior art provides 30% time that descends can't normally provide electric current, and about 1.6% decay has only appearred in the electric current of current source described in the invention output, falls non-sensitive electric current so the current source that the present invention describes can provide with supply voltage.

Description of drawings

Fig. 1 typical C mos image sensor Organization Chart.

The non-sensitive current source circuit structural drawing of power voltage-drop that Fig. 2 the present invention describes.A part: available current mirroring circuit in the prior art, B part: the non-sensitive current source circuit of n row power voltage-drop unit.

The electric current that the non-sensitive current source of Fig. 3 power voltage-drop provides is with the change curve of power voltage-drop.

Embodiment

Current source circuit that the present invention describes and its control timing are as shown in Figure 2.VX representes the grid voltage of transistor M0, and VY representes the grid voltage of transistor Mn1, the grid voltage of transistor Mn1 when k clock period of VY [k] expression finishes.The A partial circuit is an available current mirroring circuit in the prior art among Fig. 2, and the electric current that this current mirror flows through is Iref, and the power supply of its use is respectively the reference power source VDD_ref and ground VSS_ref that does not have IR-drop with ground.Because VX is the grid voltage of transistor M0, it can be expressed as:

$V_{\mathrm{DD}\_\mathrm{ref}}-V_X=\left|V_{\mathrm{TH}}\right|+\sqrt{\frac{{2I}_{\mathrm{ref}}}{\mathrm{\μ}{C}_{\mathrm{ox}}\frac{W}{L}}}---\left(1\right)$

B partly is the major part of the current source circuit described of the present invention among Fig. 2, and wherein capacitor C P is the grid stray capacitance over the ground of transistor Mn1.In imageing sensor, the circuit of B part can be used as the row current source and uses.Current source with the n row is that example is described; The course of work of this current source is following: work as S1=1, during S2=0, the top crown of capacitor C n1 is connected on the reference power source VDD_ref; Bottom crown is connected on the grid of transistor M0, so charge stored is among the capacitor C n1:

Q ₁＝(V _{DD_ref}-V _X)·C _n1 (2)

Meanwhile, the top crown of Cn2 is connected on the power vd D_power of n row current source cell, and its bottom crown is connected on the grid of transistor Mn1.Work as S1=0, during S2=1, the location swap of capacitor C n1 and Cn2, capacitor C n1 have connected source electrode and the grid of transistor Mn1, and capacitor C n2 connects source electrode and the grid of transistor M0.When first clock period finished, the voltage of Cn1 top crown became VDD_power, and the voltage of bottom crown becomes VY [1].The initial storage electric charge of supposing stray capacitance CP is 0, then is stored in the electric charge of Mn1 gate node this moment to be:

Q ₂＝(V _{DD_power}，n-V _Y[1])·C _n1+V _Y[1]·C _P (3)

Because the grid node of the Mn1 floating empty node that is high resistant, so Q1 equals Q2, can obtain like this:

$V_Y\left[1\right]=(V_{\mathrm{DD}\_\mathrm{power},n}-V_{\mathrm{DD}\_\mathrm{ref}}+V_X)\frac{C_{n1}}{C_{n1}-C_p}---\left(4\right)$

When k clock period finishes, theoretical according to charge conservation, can obtain following equality:

(V _{DD_ref}-V _X)·C _n1+V _Y[k-1]·C _P＝(V _{DD_power}，n-V _Y[k])·C _n1+V _Y[k]·C _P (05)

$V_Y\left[k\right]=(V_{\mathrm{DD}\_\mathrm{power},n}-V_{\mathrm{DD}\_\mathrm{ref}}+V_X)\frac{C_{n1}}{C_{n1}-C_p}+V_Y[k-1]\·\frac{C_p}{C_p-C_{n1}}---\left(6\right)$

Can obtain the substitution equality (6) with VY [k-j] from j=1 to the j=k-1 recurrence:

$V_Y\left[n\right]=(V_{\mathrm{DD}\_\mathrm{power},n}-V_{\mathrm{DD}\_\mathrm{ref}}+V_X)\·(1-\frac{C_P}{C_P-C_{n1}})\·\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{\left(\frac{C_P}{C_P-C_{n1}}\right)}^{i-1}---\left(7\right)$

The ratio CP of Cn1 design is big a lot, therefore as i [CP/ (CP-Cn1)] greater than 3 the time ^I-1Can ignore, so the finally stabilised voltage of VY is:

$V_Y[\∞]=(V_{\mathrm{DD}\_\mathrm{power},n}-V_{\mathrm{DD}\_\mathrm{ref}}+V_X)\·[1-{\left(\frac{C_P}{C_P-C_{n1}}\right)}^2]$

$\≈V_{\mathrm{DD}\_\mathrm{power},n}-V_{\mathrm{DD}\_\mathrm{ref}}+V_X---\left(8\right)$

The gate source voltage of final Mn1 is VDD_ref-VX, and is identical with the gate source voltage of M0.Therefore the electric current that flows through Mn1 is the image current with the irrelevant M0 of its power vd D_power.Do not overlap mutually under the control of clock two, source electrode that is connected to transistor Mn1 that capacitor C n1 and Cn2 replace and grid to be keeping stable gate source voltage, and then guarantee that Mn1 provides stable bias current.For the external circuit that reduce to use this current source is introduced noise to Mn1, through the current mirror that constitutes by transistor Mn2 and Mn3 with the current mirror of Mn1 after output offer the external circuit use.

The breadth length ratio of transistor M0 is 60: 1, and the breadth length ratio of transistor Mn1 is 6: 1, and the working current of M0 is 60uA, and then the working current of Mn1 is 6uA, and the breadth length ratio of transistor Mn2 and Mn3 is 2: 1, and Mn3 can provide stable 6uA bias current.Capacitor C n1 and Cn2 realize that through mos capacitance its appearance value is 500fF.This current source can be applicable in the pixel column biasing of high resolution CMOS image sensor and also can be used in the row parallel read-out circuit.

Claims (4)

1. One kind be used for cmos image sensor to the insensitive current source circuit of power voltage-drop, comprise the current mirroring circuit of forming by transistor M0, it is characterized in that, also comprise capacitor C n1, capacitor C n2, transistor Mn1, Mn2, Mn3; Switch S 1, S2, switch S 1 is the linkage groups switch, switch S 2 also is the linkage groups switch; When the S1 closure, when S2 opened, the top crown of capacitor C n1 was connected on the reference power source VDD_ref; Bottom crown is connected on the grid of transistor M0; Meanwhile, the top crown of Cn2 is connected on the power vd D_power of n row current source cell, and its bottom crown is connected on the grid of transistor Mn1; When S1 opens, when S2 was closed, the location swap of capacitor C n1 and Cn2, capacitor C n1 had connected source electrode and the grid of transistor Mn1, source electrode and the grid of capacitor C n2 connection transistor M0; Transistor Mn1 source electrode connects power vd D_power; Transistor Mn1 drain electrode connects transistor Mn2 source electrode, transistor Mn2 source electrode, grid short circuit, and transistor Mn2 drain electrode connects ground VSS; Export behind the current mirror of current mirror that transistor Mn2 and Mn3 constitute transistor Mn1.
2. 2. as claimed in claim 1 be used for cmos image sensor to the insensitive current source circuit of power voltage-drop; It is characterized in that; Switch S 1, S2 be in two foldings under the control of clock that do not overlap mutually, makes source electrode that is connected to transistor Mn1 that capacitor C n1 and Cn2 replace and grid to keep stable gate source voltage.
3. 3. as claimed in claim 1 be used for cmos image sensor to the insensitive current source circuit of power voltage-drop, it is characterized in that, capacitor C n1, capacitor C n2 appearance value than the grid of transistor Mn1 over the ground stray capacitance CP go out greatly more than the one magnitude.
4. 4. as claimed in claim 1 be used for cmos image sensor to the insensitive current source circuit of power voltage-drop; It is characterized in that the breadth length ratio of transistor M0 is 60: 1, the breadth length ratio of transistor Mn1 is 6: 1; The working current of M0 is 60uA; Then the working current of Mn1 is 6uA, and the breadth length ratio of transistor Mn2 and Mn3 is 2: 1, and Mn3 can provide stable 6uA bias current; Capacitor C n1 and Cn2 realize that through mos capacitance its appearance value is 500fF.

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