CN109639261A - Comparison circuit, delay removing method - Google Patents
Comparison circuit, delay removing method Download PDFInfo
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- CN109639261A CN109639261A CN201811373743.8A CN201811373743A CN109639261A CN 109639261 A CN109639261 A CN 109639261A CN 201811373743 A CN201811373743 A CN 201811373743A CN 109639261 A CN109639261 A CN 109639261A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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- Nonlinear Science (AREA)
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- Manipulation Of Pulses (AREA)
Abstract
A kind of comparison circuit, delay removing method, comparison circuit includes: control circuit, condenser network and transconductance amplifier circuit, in which: control circuit is suitable for receiving input signal, and the output signal based on input signal and comparison circuit, control comparison circuit are in different working stages；Condenser network is suitable for storing DC offset voltage signal in the automatic zero adjustment stage；At the time of measuring phases and output signal overturning, input signal is stored；In delay sample phase, equivalent delay voltage signal is stored；Transconductance amplifier circuit is suitable for storing DC offset voltage signal to condenser network in the automatic zero adjustment stage；In measuring phases, the voltage signal of positive-negative input end is compared, and generates the output signal of comparison circuit；In delay sample phase, equivalent delay voltage signal is stored to the condenser network.Using above-mentioned comparison circuit, the inherent delay of comparison circuit can be eliminated.
Description
Technical field
The present embodiments relate to circuit field more particularly to a kind of comparison circuits, delay removing method.
Background technique
In circuit field, comparison circuit is very widely used.The basic principle of comparison circuit are as follows: by input signal and ginseng
Examine voltage carry out it is real-time, quick and accurately compare with judgement, and export judging result for other processing of circuit.For example,
It changes to when input signal lower than reference voltage by changing to higher than reference voltage, or by being higher than reference voltage lower than ginseng
When examining voltage, then judging result is exported immediately and is dealt with to subsequent conditioning circuit.
In the prior art, constantly improved by structure, the device parameters to comparison circuit, can to compare
Circuit quickly and accurately exports comparison result.But due to the presence of inherent delay (usually tens nanosecond), cause to compare
Always there is certain constant error in circuit.
Therefore existing comparison circuit, intrinsic response delay make comparison result generate error.
Summary of the invention
The technical issues of embodiment of the present invention solves is the inherent delay how eliminated in existing comparison circuit.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of comparison circuit, comprising: control circuit, capacitor electricity
Road and transconductance amplifier circuit, in which: the control circuit is suitable for receiving input signal, and is based on the input signal and institute
The output signal for stating comparison circuit controls the comparison circuit and is in different working stages, wherein the working stage includes:
Automatic zero adjustment stage, measuring phases and delay sample phase；The condenser network is suitable in the automatic zero adjustment stage, storage
The DC offset voltage signal of the transconductance amplifier circuit；At the time of the measuring phases and output signal overturning,
Store the input signal；In the delay sample phase, the equivalent delay voltage signal of the transconductance amplifier circuit is stored,
Wherein the equivalent delay voltage signal is related to the input signal that the measuring phases store；The trsanscondutance amplifier electricity
Road is suitable for storing the DC offset voltage signal of the transconductance amplifier circuit to the electricity in the automatic zero adjustment stage
Capacitive circuit；In the measuring phases, the voltage signal of positive-negative input end is compared, and generates the output of the comparison circuit
Signal；In the delay sample phase, the voltage signal of positive-negative input end is compared, and the equivalent delay voltage is believed
It number stores to the condenser network.
Optionally, the transconductance amplifier circuit includes: trsanscondutance amplifier and its corresponding DC offset voltage, in which:
The DC offset voltage, positive reference end are the negative input end of the transconductance amplifier circuit, and negative reference end is put with the mutual conductance
The negative input end coupling of big device；The trsanscondutance amplifier, positive input terminal are the positive input terminal of the transconductance amplifier circuit, output
End is the output end of the transconductance amplifier circuit.
Optionally, the comparison circuit further include: voltage buffer circuit suitable for transmission voltage signal and exports the comparison
The output signal of circuit；The control circuit include: first switch, second switch, third switch, the 4th switch, the 5th switch,
6th switch, the 7th switch, the 8th switch and the 9th switch, the condenser network includes: first capacitor, the second capacitor and third
Capacitor, the voltage buffer circuit include: first voltage buffer, second voltage buffer and tertiary voltage buffer, in which:
The first switch, the first port of the first switch is the first input end of the comparison circuit, to be compared for receiving
Input signal, the positive reference potential end of the second port of the first switch and the first capacitor, the second switch
First port, the first voltage buffer input terminal mutually couple；The first capacitor, the negative ginseng of the first capacitor
Examine potential end ground connection；The second switch, the input terminal of the second port of the second switch and the second voltage buffer
Coupling is the second input terminal of the comparison circuit, for receiving reference signal；The first voltage buffer, described first
The first port coupling at the negative reference potential end of the output end of voltage buffer and second capacitor, the 5th switch；Institute
The second capacitor is stated, the positive reference potential end of second capacitor and first port, the third of the 4th switch switch
First port couples；4th switch, the described 4th second port switched are just defeated with the transconductance amplifier circuit
Enter the second port coupling at end, the 5th switch；The second voltage buffer, the output end of second voltage buffer and institute
State the negative reference potential end coupling of third capacitor；The third capacitor, the positive reference potential end of the third capacitor and described the
The negative input end coupling of the first port, the transconductance amplifier circuit of six switches；The third switch, the third switch
The output end of second port and the transconductance amplifier circuit, the second port of the 6th switch, the 7th switch the
Single port couples；7th switch, the second port of the 7th switch and the described 8th first port, described that switchs
The first port of 9th switch, the input terminal of the tertiary voltage buffer couple；8th switch, the 8th switch
Second port and it is described 9th switch second port be grounded；The tertiary voltage buffer, the tertiary voltage buffering
The output end of device is the output end of the comparison circuit, is suitable for output signal.
Optionally, the control circuit, suitable for controlling at the comparison circuit by opening or being closed different switches
In different working stages.
Optionally, the control circuit is suitable for being closed the second switch, the 5th switch, the 6th switch, institute
The 8th switch is stated, disconnects the first switch, the third switchs, the described 4th switchs, the described 7th switchs, the described 9th opens
It closes, controls the comparison circuit and be in the automatic zero adjustment stage, so that the third capacitor stores the transconductance amplifier circuit
DC offset voltage signal；Be closed the first switch, it is described 4th switch, it is described 7th switch, disconnect the second switch,
The third switch, the 5th switch, the 6th switch, the 8th switch, the 9th switch, control the comparison
Circuit is in measuring phases, so that the first capacitor stores the input signal at the time of output signal is overturn；It closes
Third switch, the 5th switch and the 9th switch are closed, the first switch, second switch, described is disconnected
4th switch, the 6th switch, the 7th switch and the 8th switch, so that described in second condenser network storage
The equivalent delay voltage signal of transconductance amplifier circuit.
Optionally, the input signal is periodic signal.
Optionally, the periodic signal is low-frequency periodic signal.
Optionally, the period of the periodic signal is greater than the period of the inherent delay signal of the comparison circuit.
The embodiment of the present invention provides a kind of delay removing method, using comparison circuit described in any of the above-described kind, eliminates institute
State the inherent delay of comparison circuit.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
Comparison circuit provided in an embodiment of the present invention is combined by control circuit, condenser network and transconductance amplifier circuit
Work, control comparison circuit are in different working stages, although passing through arteface one there are still the inherent delay of system
The offset of a input signal can allow comparison circuit during signal compares, export comparison result earlier,
The inherent delay of comparison circuit is equally eliminated with this.
Detailed description of the invention
Fig. 1 is the schematic diagram for the relative error that existing comparison circuit generates；
Fig. 2 is a kind of structural schematic diagram of comparison circuit provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another comparison circuit provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of comparison circuit in the automatic zero adjustment stage provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of comparison circuit in measuring phases provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of comparison circuit in delay sample phase provided in an embodiment of the present invention；
Fig. 7 is a kind of schematic diagram of the sequential relationship of comparison circuit provided in an embodiment of the present invention；
Fig. 8 is a kind of schematic diagram of the sequential relationship of comparison circuit provided in an embodiment of the present invention；
Fig. 9 is a kind of detail flowchart of removing method that is delayed provided in an embodiment of the present invention.
Specific embodiment
In existing technology, there is certain inherent delay in comparison circuit always, and comparison result is caused to generate error.Example
Such as, as shown in Figure 1, during input signal VIN rises, when input signal VIN is equal to reference voltage VREF, VOUT is answered
Overturning immediately at the A moment is high level, but due to the inherent delay of comparator, so that when VOUT is overturn at the B moment as high electricity
Usually, and the voltage of input signal VIN has been not equal to reference voltage VREF at this time, to cause error.
Comparison circuit provided in an embodiment of the present invention is combined by control circuit, condenser network and transconductance amplifier circuit
Work, control comparison circuit are in different working stages, although passing through arteface one there are still the inherent delay of system
The offset of a input signal can allow comparison circuit during signal compares, export comparison result earlier,
System inherent delay is equally eliminated with this.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to fig. 2, the embodiment of the invention provides a kind of comparison circuits 20, may include: control circuit 21, condenser network
22 and transconductance amplifier circuit 23, in which:
The control circuit 21 is suitable for receiving input signal, and defeated based on the input signal and the comparison circuit
Signal out controls the comparison circuit and is in different working stages, wherein the working stage include: the automatic zero adjustment stage,
Measuring phases and delay sample phase.
The condenser network 22 is suitable for storing the direct current of the transconductance amplifier circuit 23 in the automatic zero adjustment stage
Offset voltage signal；At the time of the measuring phases and output signal overturning, the input signal is stored；Described
Be delayed sample phase, the equivalent delay voltage signal of the transconductance amplifier circuit 23 is stored, wherein the equivalent delay voltage
Signal is related to the input signal that the measuring phases store.
The transconductance amplifier circuit 23 is suitable in the automatic zero adjustment stage, by the transconductance amplifier circuit 23
DC offset voltage signal is stored to the condenser network 22；In the measuring phases, to the voltage signal of positive-negative input end into
Row compares, and generates the output signal of the comparison circuit 20；In the delay sample phase, the voltage of positive-negative input end is believed
It number is compared, and the equivalent delay voltage signal is stored to the condenser network 22.
For example, the transconductance amplifier circuit 23, in the automatic zero adjustment stage, using the feedback loop that it is constituted,
The DC offset voltage of trsanscondutance amplifier is stored to the condenser network 22, to be adopted in the measuring phases and the delay
DC offset voltage is eliminated when the sample stage is using trsanscondutance amplifier；In the measuring phases, to the voltage signal of positive-negative input end
It is compared, and the output signal of the comparison circuit 20 in conjunction with described in buffer circuit evolving；In delay sample phase, to positive and negative defeated
Enter voltage is held to be compared, and the voltage signal for characterizing constant time lag is stored to the condenser network 22.
In specific implementation, the transconductance amplifier circuit 23 can be made of trsanscondutance amplifier and DC offset voltage.
For example, the transconductance amplifier circuit 23 can be made of ideal trsanscondutance amplifier OTA1 and DC offset voltage VOS.
In an embodiment of the present invention, the transconductance amplifier circuit 23 includes: trsanscondutance amplifier and its corresponding intrinsic
The equivalent DC offset voltage in trsanscondutance amplifier negative input end, in which: the DC offset voltage, positive reference end are described
The negative input end of the negative input end of transconductance amplifier circuit 23, negative reference end and the trsanscondutance amplifier couples；The mutual conductance is put
Big device, positive input terminal are the positive input terminal of the transconductance amplifier circuit 23, and output end is the transconductance amplifier circuit 23
Output end.
In specific implementation, the comparison circuit 20 can also include: voltage buffer circuit (not shown), be suitable for transmission electricity
Press the output signal of signal or the output comparison circuit 20.
In a specific embodiment, the comparison circuit 20 can also include: voltage buffer circuit (not shown), be suitable for passing
Defeated voltage signal and the output signal for exporting the comparison circuit；The control circuit 21 include: first switch, second switch,
Third switch, the 4th switch, the 5th switch, the 6th switch, the 7th switch, the 8th switch and the 9th switch, the condenser network
It include: first capacitor, the second capacitor and third capacitor, the voltage buffer circuit includes: first voltage buffer, second voltage
Buffer and tertiary voltage buffer, in which: the first switch, the first port of the first switch are the comparison circuit
First input end, for receiving input signal to be compared, the second port of the first switch and the first capacitor
Positive reference potential end, the first port of the second switch, the first voltage buffer input terminal mutually couple；It is described
First capacitor, the negative reference potential end ground connection of the first capacitor；The second switch, the second port of the second switch with
The input terminal of the second voltage buffer couples, and is the second input terminal of the comparison circuit, for receiving reference signal；Institute
State first voltage buffer, it is the negative reference potential end of the output end of the first voltage buffer and second capacitor, described
The first port coupling of 5th switch；Second capacitor, the positive reference potential end of second capacitor and the 4th switch
First port, the third switch first port couple；It is described 4th switch, it is described 4th switch second port with
The second port coupling of the positive input terminal of the transconductance amplifier circuit, the 5th switch；The second voltage buffer, the
The negative reference potential end of the output end of two voltage buffers and the third capacitor couples；The third capacitor, the third electricity
The negative input end coupling of the first port of the positive reference potential end of appearance and the 6th switch, the transconductance amplifier circuit；Institute
Third switch is stated, what the output end of second port and the transconductance amplifier circuit that the third switchs, the described 6th switched
Second port, the first port of the 7th switch couple；7th switch, the second port of the 7th switch and institute
State the 8th switch first port, it is described 9th switch first port, the tertiary voltage buffer input terminal couple；
8th switch, the second port of the 8th switch and the second port of the 9th switch are grounded；The third electricity
Compression buffer, the output end of the tertiary voltage buffer are the output end of the comparison circuit, are suitable for output signal.
In specific implementation, the input signal can be periodic signal.
In an embodiment of the present invention, the periodic signal is low-frequency periodic signal.
In specific implementation, the period of the periodic signal can be greater than the week of the inherent delay signal of the comparison circuit
Phase.
To more fully understand those skilled in the art and implementing the present invention, the embodiment of the invention provides another kinds relatively
The structural schematic diagram of circuit, as shown in Figure 3.
Referring to Fig. 3, the comparison circuit includes: control circuit, condenser network, transconductance amplifier circuit and voltage buffer electricity
Road, wherein the control circuit includes: first switch SW1, second switch SW2, third switch SW3, the 4th switch SW4, the 5th
Switch SW5, the 6th switch SW6, the 7th switch SW7, the 8th switch SW8, the 9th switch SW9；The condenser network includes: first
Capacitor C1, the second capacitor C2, third capacitor C3；The voltage buffer circuit includes: first voltage buffer VBUF1, the second electricity
Compression buffer VBUF2, tertiary voltage buffer VBUF3；The transconductance amplifier circuit OTA include: DC offset voltage VOS and
Ideal trsanscondutance amplifier OTA1, in which:
The first port of first switch SW1 is the first input end VIN of the comparison circuit, and second port is respectively with first
The positive reference potential end of capacitor C1, the first port of second switch C2, first voltage buffer VBUF1 input terminal mutually couple.
The negative reference potential end of first capacitor C1 is grounded.
The input terminal of the second port of second switch C2 and the second voltage buffer couples, and is the comparison circuit
Second input terminal VREF.
The negative reference potential end of the output end of first voltage buffer VBUF1 and the second capacitor C2, the 5th switch SW5
Single port coupling.
The positive reference potential end of second capacitor C2 and first port, the first port of third switch SW3 of the 4th switch SW4
Couple.
The second of the positive input terminal of the second port of 4th switch SW4 and transconductance amplifier circuit OTA, the 5th switch SW5
Port coupling.
The output end of second voltage buffer VBUF2 and the negative reference potential end of third capacitor C3 couple.
The first port of the positive reference potential end of third capacitor C3 and the 6th switch SW6, transconductance amplifier circuit OTA are born
Input terminal coupling.
The second port of third switch SW3 and the output end of transconductance amplifier circuit OTA, the second end of the 6th switch SW6
Mouthful, the first port of the 7th switch SW7 couples.
The first port of the second port of 7th switch SW7 and the 8th switch SW8, the first port of the 9th switch SW9, the
The input terminal of three voltage buffer VBUF3 couples.
The second port of 8th switch SW8 and the second port of the 9th switch SW9 are grounded.
The output end of tertiary voltage buffer VBUF3 is the output end of the comparison circuit, is suitable for output signal.
The DC offset voltage VOS, positive reference end are the negative input end of the transconductance amplifier circuit OTA, bear reference
End and the negative input end of the trsanscondutance amplifier OTA1 couple.
The trsanscondutance amplifier OTA1, positive input terminal are the positive input terminal of the transconductance amplifier circuit OTA, and output end is
The output end of the transconductance amplifier circuit OTA.
In specific implementation, the control circuit, suitable for controlling the comparison by opening or being closed different switches
Circuit is in different working stages.
By taking Fig. 3 as an example, first switch SW1, second switch SW2, third switch SW3, the 4th switch SW4, the 5th switch
SW5, the 6th switch SW6, the 7th switch SW7, the 8th switch SW8, the 9th switch SW9 respectively by control signal MEA, SAM_AZ,
SAM_DC, MEA, SAM_AZ/SAM_DC, SAM_AZ, MEA, SAM_AZ, SAM_DC carry out the disconnection and connection of control switch.Work as control
When signal processed is high level, control is closed the switch, and when controlling signal is low level, the switch of control disconnects.
In specific implementation, the 5th switch SW5 is by control signal SAM_AZ and SAM_DC co- controlling, when control is believed
When any one in number SAM_AZ and SAM_DC is high level, otherwise the 5th switch SW5 closure the described 5th switchs
SW5 is disconnected.
In an embodiment of the present invention, the control circuit is suitable for being closed the second switch, the 5th switch, institute
The 6th switch, the 8th switch are stated, disconnects the first switch, the third switchs, the described 4th switchs, the described 7th opens
It closes, the 9th switch, controls the comparison circuit and be in the automatic zero adjustment stage, so that the third capacitor stores the mutual conductance
The DC offset voltage signal of amplifier circuit；It is closed the first switch, the 4th switch, the 7th switch, is disconnected
The second switch, third switch, the 5th switch, the 6th switch, the 8th switch, the described 9th open
It closes, controls the comparison circuit and be in measuring phases, so that the first capacitor at the time of output signal is overturn, stores
The input signal；It is closed the third switch, the 5th switch and the 9th switch, disconnects the first switch, institute
Second switch, the 4th switch, the 6th switch, the 7th switch and the 8th switch are stated, so that described second
Condenser network stores the equivalent delay voltage signal of the transconductance amplifier circuit.
To more fully understand those skilled in the art and implementing the present invention, the embodiment of the invention provides one kind in certainly
The structural schematic diagram of the comparison circuit of dynamic school zeroth order section, as shown in Figure 4.
Referring to fig. 4, in the automatic zero adjustment stage, control signal SAM_AZ is high level, other control signals are low level, the
Two switch SW2, the 5th switch SW5, the 6th switch SW6, the 8th switch SW8 closure, other switches disconnect.
In specific implementation, there are DC offset voltages by transconductance amplifier circuit OTA, which can be determined
It is characterized as VOS to amount.
In the automatic zero adjustment stage, first voltage buffer VBUF1, second voltage buffer VBUF2 output terminal potential all
Equal to reference voltage VREF, and the negative input end and output end of the transconductance amplifier circuit OTA being shorted constitute feedback loop, root
According to " empty short " principle, the positive input terminal current potential of transconductance amplifier circuit OTA is made to be equal to the negative input of ideal trsanscondutance amplifier OTA1
Terminal potential, namely the negative input end current potential of ideal trsanscondutance amplifier OTA1 are also equal to reference voltage VREF, in this way in third capacitor
The voltage equal with DC offset voltage VOS is just stored on C3.
For example, can also store 10mV, such DC maladjustment on third capacitor C3 when DC offset voltage VOS is+10mV
Voltage VOS is cancelled completely, and reference voltage VREF can unchangeably be input to the negative input end of ideal trsanscondutance amplifier OTA1.This
Afterwards, when system is in measuring phases or delay sample phase, the voltage and DC offset voltage VOS that are stored on third capacitor C3
It will cancel out each other, to eliminate the DC maladjustment error of transconductance amplifier circuit OTA.
In specific implementation, when the automatic zero adjustment stage is by after a certain period of time, voluntarily terminating.
To more fully understand those skilled in the art and implementing the present invention, the embodiment of the invention provides one kind in survey
The structural schematic diagram of the comparison circuit in amount stage, as shown in Figure 5.
Referring to Fig. 5, in measuring phases, control signal MEAS is high level, other control signals are low level, first switch
SW1, the 4th switch SW4 and the 7th switch SW7 closure, and other switches disconnect.
In measuring phases, after mono- new period of input signal VIN starts, using one section of set time (for example, anti-
Overlapping time) after, system starts to carry out input signal VIN compared with reference voltage.Once output signal VOUT is overturn, and first
Switch SW1 will be disconnected immediately, so that there are on first capacitor C1 instantaneous input signal VIN at this time.On first capacitor C1
Voltage and the pressure difference (can be described as input surplus) of reference voltage VREF are proportional with the equivalent delay of system, and pressure difference is bigger, shows
The equivalent delay of system is bigger.From starting to compare output signal VOUT overturning, this time is measuring phases.
In specific implementation, anti-overlapping (No-overlap) time is the unstable stage in order to avoid input signal.
In specific implementation, input signal VIN can be low-frequency periodic signal, such as the period is the period letter greater than 10*T
Number, wherein T is the inherent delay of comparison circuit.
To more fully understand those skilled in the art and implementing the present invention, it is in and prolongs the embodiment of the invention provides one kind
When sample phase comparison circuit structural schematic diagram, as shown in Figure 6.
Referring to Fig. 6, in delay sample phase, control signal SAM_DC is high level, other control signals are low level, the
Three switch SW3, the 5th switch SW5, the 9th switch SW9 closure, and other switches disconnect.
In delay sample phase, the output of transconductance amplifier circuit OTA is connected to the positive reference potential of the second capacitor C2
End is determined to the second capacitor C2 charging or is put by the polarity of voltage first capacitor C1 on and the pressure difference of reference voltage VREF
Electricity, by after a certain period of time, this delay sample phase voluntarily terminates, and the equivalent delayed data of system is stored in the second capacitor
On C2, value is denoted as VC1.In this way in next measuring phases, by the positive input terminal for artificially giving transconductance amplifier circuit OTA
DC offset voltage (its value is equal to voltage on the second capacitor C2) is constructed overturn output end VOUT earlier, to support
The inherent delay of sterilizing system.After multiple periods, voltage will tend towards stability on the second capacitor C2, and at this moment the equivalent of system prolongs
When be also just minimized.
For example, input signal VIN will be applied a second capacitor C2 and power on after voltage tends towards stability on the second capacitor C2
It is input into the positive input terminal of transconductance amplifier circuit OTA after pressure, is equivalent to input signal VIN and is artificially superimposed a direct current
Offset voltage, in this way in measuring phases, from input signal VIN rise during system output signal VOUT can be made to turn over earlier
Turn.
As shown in fig. 7, being overturn in A moment output signal VOUT, but in currently existing scheme by the intrinsic of comparison circuit
It can be overturn at the B moment after delay, comparison result is caused to generate error.
After comparison circuit provided in an embodiment of the present invention, due to being superimposed VC1, comparison circuit exports letter at the C moment
Number VOUT overturning, but can be overturn at the A moment after the inherent delay of comparison circuit, the equivalent delay of such system is equal to
Zero.
It is understood that in order to protrude innovative part of the invention, it will not be with this hair of solution in present embodiment
The technical issues of bright proposed, the less close unit of relationship introduced, i.e., all realization units of the described comparison circuit introduce, but
This, which is not indicated in embodiment of the present invention, realizes unit there is no other.
It using above-mentioned comparison circuit, is worked together by control circuit, condenser network and transconductance amplifier circuit, controls ratio
It is in different working stages compared with circuit, although passing through one input signal of arteface there are still the inherent delay of system
Offset, can allow comparison circuit signal relatively during, export comparison result earlier, equally with this
Eliminate the inherent delay of comparison circuit.
Meanwhile the embodiment of the present invention effectively overcomes various shortcoming in the prior art and has quick, accurate, error free
The advantages of.
To more fully understand those skilled in the art and implementing the present invention, the embodiment of the invention provides a kind of comparison is electric
The schematic diagram of the sequential logic on road, as shown in Figure 8.
It is reset signal referring to Fig. 8, RST, TO_MEA is signal relevant to input signal, and input signal is before the period
Occur in the section time, then just no longer occur, until next cycle.When there is no input signal input, TO_MEA signal
For low level, SAM_AZ, MEA and SAM_DC are the control signal of control circuit, and with opening or closure switch, VOUT is output
Signal.
In order to increase the readability of sequential logic figure, according to input signal, sequential logic figure is divided into four periods, point
It Wei not " resetting ", " preparation ", " period 1 of input signal ", " period 2 of input signal ".
In " resetting " period, RST is high level, and time period carries out the initialization of system；When RST becomes low level,
Entering " preparation " period at this time, the rising edge of the failing edge triggering SAM_AZ of TO_MEA enters " automatic zero adjustment " stage at this time,
" automatic zero adjustment " stage self terminates after set time.Hereafter system waits, until when initially entering " period 1 of input signal "
Between section when " preparation " period just terminate, at this time TO_MEA trigger rising edge, the one fixed anti-overlapping time by very little
Afterwards, system enters " test " stage and is compared to input signal VIN with reference voltage VREF, once exporting after relatively
Signal VOUT overturning, MEA trigger failing edge, and the failing edge of MEA triggers the rising edge of SAM_DC again, enter " delay sampling " at this time
In the stage, " delay sampling " stage self terminates after the set time." delay sampling " declines after the stage until TO_MEA is triggered
Along the rising edge for just triggering SAM_ZA, enter " automatic zero adjustment " stage, " automatic zero adjustment " stage self knot after the set time at this time
Beam.Just enter " period 2 of input signal " period after " period 1 of input signal " period of input signal VIN,
Hereafter the process of " period 1 of input signal " period is repeated.
The embodiment of the present invention provides a kind of delay removing method, using comparison circuit described in any of the above-described kind, eliminates institute
State the inherent delay of comparison circuit.
To more fully understand those skilled in the art and implementing the present invention, the embodiment of the invention provides in a kind of application
The delay removing method of comparison circuit is stated, as shown in Figure 9.
Referring to Fig. 9, the delay removing method be may include steps of:
Step S901, into the automatic zero adjustment stage.
In specific implementation, after system starts, into the automatic zero adjustment stage, transconductance amplifier circuit is eliminated with this
The input offset of OTA compares reference voltage VREF completely.Voluntarily terminate after the experience set time in this stage；
Step S902 judges whether the automatic zero adjustment stage of set time is overtime, if the automatic zero adjustment rank of set time
Section time-out, executes step S903, and otherwise circulation executes step S902.
Step S903, judges whether the new period of input signal starts (i.e. whether the signal of TO_MEA is rising edge), such as
The new period of fruit input signal executes step S904, and otherwise circulation executes step S903.
Step S904 judges whether the anti-overlapping time is overtime, if the anti-overlapping time is overtime, executes step S905, otherwise
Circulation executes step S904.
Step S905, into measuring phases.
Step S906, judges whether output signal VOUT overturns, if output signal VOUT is overturn, executes step S907,
Otherwise circulation executes step S906.
Step S907 stores input signal VIN to first capacitor C1, while test phase terminates.
In specific implementation, after the completion of the automatic zero adjustment stage, when mono- new period of input signal VIN, TO_
After MEA triggers rising edge, then after undergoing the anti-overlapping time of set time, namely enter measuring phases, is carried out in this stage defeated
Enter the comparison of voltage and reference voltage.Once output signal VOUT is overturn, input signal VIN at this time is stored immediately in the first electricity
Hold on C1, value and the pressure difference (can be described as input surplus) of reference voltage are proportional with the equivalent delay of system, and pressure difference is bigger, table
The equivalent delay of bright system is bigger.
Step S908, into delay sample phase.
In specific implementation, in delay sample phase, according to the voltage stored on first capacitor C1, equivalent delayed data turns
Voltage is changed into store to the second capacitor C2.
In specific implementation, delay sample phase is entered after measuring phases.This stage is according on first capacitor C1
Voltage, equivalent delayed data is converted by transconductance amplifier circuit OTA by voltage and is stored on the second capacitor C2, as under
The offset of input signal VIN in secondary measuring phases, to participate in input signal VIN compared with reference voltage VREF.Delay is adopted
After the sample stage undergoes the set time, this stage self terminates.
Step S909 judges whether the delay sample phase of set time is overtime, if the delay of set time samples rank
Section time-out, executes step S910, and otherwise circulation executes step S909.
Step S910 judges whether TO_MEA is low level, if TO_MEA is low level, executes step S901, otherwise
Circulation executes step S910.
In specific implementation, automatic school will be entered second until TO_MEA triggering failing edge after delay sampling
Zeroth order section, repeats the above steps later, and until by multiple periods, voltage will tend towards stability on the second capacitor C2, at this moment
" input surplus " will be minimized, so that the equivalent delay of system is also just minimized.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of comparison circuit characterized by comprising control circuit, condenser network and transconductance amplifier circuit, in which:
The control circuit is suitable for receiving input signal, and the output signal based on the input signal and the comparison circuit,
It controls the comparison circuit and is in different working stages, wherein the working stage includes: automatic zero adjustment stage, measuring phases
With delay sample phase；
The condenser network is suitable for storing the DC offset voltage of the transconductance amplifier circuit in the automatic zero adjustment stage
Signal；At the time of the measuring phases and output signal overturning, the input signal is stored；It is sampled in the delay
Stage stores the equivalent delay voltage signal of the transconductance amplifier circuit, wherein the equivalent delay voltage signal with it is described
The input signal of measuring phases storage is related；
The transconductance amplifier circuit is suitable in the automatic zero adjustment stage, by the DC maladjustment of the transconductance amplifier circuit
Voltage signal is stored to the condenser network；In the measuring phases, the voltage signal of positive-negative input end is compared, and raw
At the output signal of the comparison circuit；In the delay sample phase, the voltage signal of positive-negative input end is compared, and
The equivalent delay voltage signal is stored to the condenser network.
2. comparison circuit according to claim 1, which is characterized in that the transconductance amplifier circuit includes: mutual conductance amplification
Device and its corresponding DC offset voltage, in which:
The DC offset voltage, positive reference end be the transconductance amplifier circuit negative input end, negative reference end and it is described across
Lead the negative input end coupling of amplifier；
The trsanscondutance amplifier, positive input terminal are the positive input terminal of the transconductance amplifier circuit, and output end is that the mutual conductance is put
The output end of big device circuit.
3. comparison circuit according to claim 2, which is characterized in that further include:
Voltage buffer circuit, suitable for transmitting voltage signal and exporting the output signal of the comparison circuit；
The control circuit includes: first switch, second switch, third switch, the 4th switch, the 5th switch, the 6th switch, the
Seven switches, the 8th switch and the 9th switch, the condenser network includes: first capacitor, the second capacitor and third capacitor, the electricity
Pressing buffer circuit includes: first voltage buffer, second voltage buffer and tertiary voltage buffer, in which:
The first switch, the first port of the first switch are the first input end of the comparison circuit, for receive to
The input signal compared, the positive reference potential end of the second port of the first switch and the first capacitor, described second open
The first port of pass, the first voltage buffer input terminal mutually couple；
The first capacitor, the negative reference potential end ground connection of the first capacitor；
The input terminal of the second switch, the second port of the second switch and the second voltage buffer couples, for institute
The second input terminal for stating comparison circuit, for receiving reference signal；
The first voltage buffer, the negative reference potential of the output end of the first voltage buffer and second capacitor
The first port coupling at end, the 5th switch；
Second capacitor, first port, the third at the positive reference potential end of second capacitor and the 4th switch
The first port of switch couples；
The positive input terminal of 4th switch, the second port of the 4th switch and the transconductance amplifier circuit, described the
The second port coupling of five switches；
The second voltage buffer, the negative reference potential end coupling of the output end of second voltage buffer and the third capacitor
It connects；
First port, the mutual conductance of the third capacitor, the positive reference potential end of the third capacitor and the 6th switch
The negative input end of amplifier circuit couples；
The third switch, the output end of second port and the transconductance amplifier circuit that the third switchs, the described 6th
The second port of switch, the first port of the 7th switch couple；
The first port of 7th switch, the second port of the 7th switch and the 8th switch, the 9th switch
First port, the tertiary voltage buffer input terminal couple；
8th switch, the second port of the 8th switch and the second port of the 9th switch are grounded；
The tertiary voltage buffer, the output end of the tertiary voltage buffer are the output end of the comparison circuit, are suitable for
Output signal.
4. comparison circuit according to claim 3, which is characterized in that the control circuit, suitable for by opening or closing
Different switches is closed, the comparison circuit is controlled and is in different working stages.
5. comparison circuit according to claim 4, which is characterized in that the control circuit is suitable for
Be closed the second switch, it is described 5th switch, it is described 6th switch, it is described 8th switch, disconnect the first switch,
The third switch, the 4th switch, the 7th switch, the 9th switch, control the comparison circuit and are in automatic
School zeroth order section, so that the third capacitor stores the DC offset voltage signal of the transconductance amplifier circuit；
Be closed the first switch, it is described 4th switch, it is described 7th switch, disconnect the second switch, the third switch,
5th switch, the 6th switch, the 8th switch, the 9th switch, control the comparison circuit and are in measurement
Stage, so that the first capacitor stores the input signal at the time of output signal is overturn；
It is closed third switch, the 5th switch and the 9th switch, the first switch is disconnected, described second opens
Pass, the 4th switch, the 6th switch, the 7th switch and the 8th switch, so that second condenser network
Store the equivalent delay voltage signal of the transconductance amplifier circuit.
6. comparison circuit according to claim 5, which is characterized in that the input signal is periodic signal.
7. comparison circuit according to claim 6, which is characterized in that the periodic signal is low-frequency periodic signal.
8. comparison circuit according to claim 6, which is characterized in that it is electric that the period of the periodic signal is greater than the comparison
The period of the inherent delay signal on road.
9. a kind of delay removing method, which is characterized in that use comparison circuit as claimed in any one of claims 1 to 8, eliminate
The inherent delay of the comparison circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811373743.8A CN109639261B (en) | 2018-11-16 | 2018-11-16 | Comparison circuit and delay eliminating method |
| US16/447,389 US10700673B2 (en) | 2018-11-16 | 2019-06-20 | Comparison circuit and delay cancellation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811373743.8A CN109639261B (en) | 2018-11-16 | 2018-11-16 | Comparison circuit and delay eliminating method |
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| CN109639261A true CN109639261A (en) | 2019-04-16 |
| CN109639261B CN109639261B (en) | 2022-12-30 |
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| US (1) | US10700673B2 (en) |
| CN (1) | CN109639261B (en) |
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| CN114994393A (en) * | 2022-08-03 | 2022-09-02 | 钰泰半导体股份有限公司 | Voltage detection circuit, detection chip and electronic equipment |
| CN117388723A (en) * | 2023-12-12 | 2024-01-12 | 成都市易冲半导体有限公司 | Current sampling circuit, chip and electronic equipment |
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| US9083254B1 (en) * | 2006-11-20 | 2015-07-14 | Picor Corporation | Primary side sampled feedback control in power converters |
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| CN104980023A (en) * | 2015-06-15 | 2015-10-14 | 青岛歌尔声学科技有限公司 | Output voltage controlling circuit and power supply provided with same |
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| CN114994393A (en) * | 2022-08-03 | 2022-09-02 | 钰泰半导体股份有限公司 | Voltage detection circuit, detection chip and electronic equipment |
| CN114994393B (en) * | 2022-08-03 | 2022-11-11 | 钰泰半导体股份有限公司 | Voltage detection circuit, detection chip and electronic equipment |
| CN117388723A (en) * | 2023-12-12 | 2024-01-12 | 成都市易冲半导体有限公司 | Current sampling circuit, chip and electronic equipment |
| CN117388723B (en) * | 2023-12-12 | 2024-02-23 | 成都市易冲半导体有限公司 | Current sampling circuit, chip and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| US10700673B2 (en) | 2020-06-30 |
| CN109639261B (en) | 2022-12-30 |
| US20190312574A1 (en) | 2019-10-10 |
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