CN218958903U - Analog-to-digital converter - Google Patents

Abstract

Embodiments of the present disclosure describe an analog-to-digital converter for converting an analog signal of a detected device into a digital signal, comprising: an operational amplifier configured to receive an analog signal and output a pulse signal; a trigger connected to the operational amplifier for sampling the pulse signal into a digital signal having the same frequency as the clock signal based on the clock signal; wherein the operational amplifier is connected to the detected device in the vicinity of the detected device and the digital signal is fed back to the first input in a negative feedback manner, the operational amplifier being further configured to receive a reference voltage at the second input, the analog-to-digital converter further comprising an integrator configured to integrate the analog signal and the fed-back digital signal to obtain an average voltage fluctuating in the vicinity of the reference voltage. The analog-to-digital converter according to the present disclosure can rapidly realize a step response of a sampled analog quantity, has high linearity, has small influence of tolerance of a device on an output, and has cost advantages.

Description

Analog-to-digital converter

Technical Field

The present disclosure relates to an analog-to-digital converter for converting an analog signal of a device under test to a digital signal, and more particularly to an analog-to-digital converter of a separate device assembly.

Background

Analog-to-digital converter (ADC) chips are a popular application, and from a cost-saving perspective, analog-to-digital conversion is typically performed using analog-to-frequency (typically voltage) or analog-to-duty cycle (duty cycle) conversion circuitry. The analog quantities to be acquired can be voltage, current, temperature and the like. The sampled voltage, current, etc. are rapidly changing quantities that need to be sensed in real time, otherwise the controller cannot get the collected quantities in real time and subsequent control or protection (with digital isolators if any) will not be achieved.

In addition, the sampled analog quantity needs to be an analog quantity in a wide range, for example, a voltage range in which upper and lower threshold voltages are high, so that resolution can be improved. Furthermore, the analog quantity being sampled should not be affected by parameters such as tolerances or temperature during the physical phases in the circuit.

Disclosure of Invention

One aspect of the present disclosure relates to an analog-to-digital converter for converting an analog signal of a device under test to a digital signal. The analog-to-digital converter may include: an operational amplifier configured to receive an analog signal and output a pulse signal having a duty cycle related to an amplitude of the analog signal; a flip-flop connected to the operational amplifier and configured to receive the clock signal and the pulse signal and sample the pulse signal into a digital signal having the same frequency as the clock signal based on the clock signal; wherein the operational amplifier is connected to the detected device in the vicinity of the detected device to receive the analog signal at a first input of the operational amplifier and the digital signal is fed back to the first input in a negative feedback manner, the operational amplifier is further configured to receive a reference voltage at a second input, the analog-to-digital converter further comprises an integrator configured to integrate the analog signal received at the first input and the fed back digital signal to obtain an average voltage in the vicinity of the reference voltage, and the operational amplifier is further configured to output a pulse signal based on the average voltage and the reference voltage.

In some embodiments, the average voltage fluctuates within a particular range above and below the reference voltage.

In some embodiments, the operational amplifier includes an adder circuit including a first inverting input, a first co-directional input, and a first output, the inverting input being the first input; the comparison circuit comprises a second reverse input end, a second homodromous input end and a second output end, and pulse signals are output from the second output end; the first output terminal is electrically connected to the second inverting input terminal, the first and second inverting input terminals each receive a reference voltage, and the integrator includes a capacitor connected in parallel between the first inverting input terminal and the first output terminal such that the first output terminal outputs an average voltage that approximates the reference voltage.

In some embodiments, the analog signal is a voltage signal, the amplitude of the analog signal varies over a range of voltages, and the duty cycle of the pulse signal or the duty cycle of the digital signal increases as the amplitude of the analog signal increases.

In some embodiments, the flip-flop is a D flip-flop or a D flip-flop circuit, a digital signal is output from a first pin of the D flip-flop or the D flip-flop circuit, and a feedback signal having a level opposite to that of the digital signal is output from a second pin of the D flip-flop or the D flip-flop circuit to be fed back to the first input terminal.

In some embodiments, the analog-to-digital converter includes a sampling side proximate to the device under test and a transmission side distal from the device under test, the operational amplifier, the flip-flop, and the integrator are disposed on the sampling side, the analog-to-digital converter further includes a controller disposed on the transmission side, and the digital signal is transmitted from the flip-flop to the controller.

In some embodiments, the analog to digital converter further comprises a digital isolator connected between the flip-flop and the controller.

In some embodiments, the analog-to-digital converter further comprises a first weighting resistor connected between the detected device and the first input terminal such that the analog signal is input to the first input terminal after being weighted by the first weighting resistor, and a second weighting resistor connected between the flip-flop and the first input terminal such that the negatively fed-back digital signal is input to the first input terminal after being weighted by the second weighting resistor.

In some embodiments, a plurality of analog-to-digital converters are used to collect analog quantities of a plurality of detected devices, and a plurality of flip-flops in the plurality of analog-to-digital converters share a clock signal.

In some embodiments, the frequency of the clock signal is in the range between 10kHz and 100 MHz.

The analog-to-digital converter according to the present disclosure can rapidly realize a step response of a sampled analog quantity, has high linearity, has small influence of tolerance of a device on an output, and has cost advantages.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

fig. 1A shows a schematic diagram of the constituent structure of an analog-to-digital converter (ADC) according to one embodiment of the disclosure.

Fig. 1B shows a schematic diagram of the constituent structure of an ADC according to one embodiment of the disclosure.

Fig. 2 shows a schematic configuration of a circuit of an ADC according to one embodiment of the disclosure, in which a digital isolator is omitted.

Fig. 3 illustrates a plot of average or duty cycle versus sampled analog signal obtained for a D flip-flop according to an embodiment of the present disclosure.

Detailed Description

Various embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it may be apparent that in some or all cases any of the embodiments described below may be practiced without resorting to the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments. The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of the embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments.

References in the framework of the present description to "an embodiment" or "one embodiment" are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to the same embodiment. Furthermore, the particular structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so that certain aspects of the embodiments will not be obscured.

Like parts or elements are indicated with like reference numerals throughout the drawings attached hereto, and corresponding descriptions will not be repeated for the sake of brevity. The reference numerals used herein are provided for convenience only and thus do not define the extent of protection or the scope of the embodiments.

In a conventionally implemented ADC, the following methods are generally adopted, including but not limited to, the first: integrating an ADC chip in a central processing unit (MCU); second,: externally arranging an ADC chip outside the MCU; third,: the analog quantity is directly transmitted to an operational amplifier for gain conversion, then filtered, and then transmitted to an ADC chip integrated in the MCU.

The ADC chip integrated in the MCU can only collect analog quantity, but not digital quantity. The ADC chip integrated in the MCU is quite long away from the sampled position, and the long-line transmission analog quantity can introduce a lot of noise pollution so as to influence the transfer function, so that the processing of the noise pollution is high in requirement. In addition, if the degree of filtering during the processing is large, a delay is large, which adversely affects the control signal.

For an external ADC chip, this typically results in a higher cost, which is several times the cost of the ADC disclosed in this disclosure. In addition, it is difficult to obtain matching external ADC chips from different vendors when data from multiple sources needs to be collected.

For the third method, the analog signal is transmitted for a long distance, so noise is easily introduced, and the difficulty of signal processing is increased.

At least to overcome the various drawbacks of the prior art schemes mentioned above, embodiments of the present disclosure propose an analog-to-digital converter that can quickly achieve a step response of the sampled analog quantity, has high linearity, has little effect of device tolerance on output, and has cost advantages.

An exemplary embodiment according to the present disclosure will be described below with reference first to fig. 1A to 2, in which fig. 1A shows a schematic diagram of a constituent structure of an ADC according to one embodiment of the present disclosure, fig. 1B shows a schematic diagram of a constituent structure of an ADC according to one embodiment of the present disclosure, and fig. 2 shows a schematic diagram of a circuit of an ADC according to one embodiment of the present disclosure, in which a digital isolator is omitted.

In the embodiment according to the present disclosure, the ADC 100 is constructed using components separated from each other, unlike the conventional method. As shown in fig. 1A and 1B, the separate devices include an operational amplifier 1, a flip-flop 2, and an integrator 3.

In the embodiment according to the present disclosure, the operational amplifier 1 includes therein an addition circuit 11 and a comparison circuit 12. The adder circuit 11 and the comparator circuit 12 may be packaged together to form a single component. The single component may be formed by a series connection of a summing circuit and a comparison circuit, respectively, commercially available, without the need for integration in the MCU. Thus, the single component may be located anywhere, for example the operational amplifier 1 may be mounted in the vicinity of the device to be tested as close as possible to the device to be tested, so as to be able to receive an analogue signal from the device to be tested, for example a voltage signal of a switch cabinet.

In the case where the sampled signal is a current signal, a resistor may be used to convert the current signal into a voltage signal, and the voltage signal may be inputted to the operational amplifier 1. In the case where the sampled signal is a temperature signal, a thermistor may be used to convert the temperature to a voltage signal. When the voltage of the sampled signal greatly exceeds the input range of the ADC (for example, from (ground potential+0.3v) to (ADC power supply voltage-0.5V), the sampled voltage is reduced to within the input range of the ADC by means of resistive voltage division.

The operational amplifier 1 processes the received signal to output a pulse signal having a duty cycle related to the amplitude of the analog signal. For example, in the case where 10V has a duty cycle of 100%, the 1V voltage has a duty cycle of 10%. That is, the sum of the high level times is 10% of the total pulse time in the sampling window (which typically includes a plurality of periods). The duty cycle is counted more accurately in a plurality of sampling periods, and is not generally counted in one sampling period.

The flip-flop 2 samples the pulse signal generated by the operational amplifier 1, for example, by using the clock signal received by it to sample the pulse signal generated by the operational amplifier 1, thereby sampling the pulse signal into a digital signal having the same period or frequency as that of the clock signal.

The flip-flop 2 can be a D flip-flop or a D flip-flop device that samples the pulse signal at the rising edge of the clock signal and remains at a fixed value for the period of the clock signal including the rising edge until the next clock period, and resamples the pulse signal. For example, if the pulse signal is high at the rising edge of the clock signal, the D flip-flop remains high for the clock period, and the output signal of the D flip-flop for the clock period does not change even if the pulse signal changes for the clock period. If the pulse signal goes low on the rising edge of the next clock cycle, the value of the D flip-flop also goes low on the next clock cycle, and if the pulse signal remains high on the rising edge of the next clock cycle, the value of the D flip-flop also remains high on the next clock cycle. Since the frequency of the clock signal used by the D flip-flop of the present application can be set as large as possible, that is, the period of the clock signal is as small as possible, which is generally smaller than the period of the pulse signal, for example, the period of the clock is at most 1/2 of the period of the pulse signal. Thus, each change in one period of the pulse signal can be captured.

The digital signal output from the D flip-flop is inverted, and the inverted digital signal is input to one input terminal of the operational amplifier 1. As shown in fig. 2, 1Q is a pin of the D flip-flop outputting a digital signal, which inputs the digital signal into the controller 4, and as shown in fig. 2, 1QZ inverts the digital signal sampled by the D flip-flop and then feeds back the inverted setting signal to an input terminal (for example, an inverting input terminal described below) of the operational amplifier 1. The controller 4 comprises a digital filter (not shown) which decimates the digital signal to obtain a final digital signal. The final digital signal has a duty cycle corresponding to the amplitude or input voltage of the sampled analog signal, the duty cycle being a proportion of the number of high levels in the digital signal to the total number of clock cycles within the sampling window.

As shown in fig. 2, the input of the inverting input terminal of the adder 11 of the operational amplifier 1 includes a digital signal fed back and an analog signal acquired. The homodromous input of the adder 11 receives a reference voltage Vref, which in one example is 50% of the supply voltage 5V of the adder 11, i.e. 2.5V. The reference voltage of 2.5V is only an example, and it is possible to appropriately adjust the reference voltage according to the voltage condition of the collected circuit. For example, in the case where the collected voltage ranges from 0V to 3V, the reference voltage may be set at about 1.5V or about 2V.

As shown in fig. 2, the inverting input terminal of the comparison circuit 12 of the operational amplifier 1 is connected to the output terminal of the addition circuit 11, and the homodromous input terminal of the comparison circuit 12 also receives the reference voltage Vref, about 2.5V. If the output voltage of the adder 11 received at the inverting input is less than 2.5V, the comparator 12 outputs a high level at the output, and conversely outputs a low level.

The ADC further comprises an integrator in the form of a capacitor 3, as shown in fig. 1 and 2, the capacitor 3 being connected in parallel between the inverting input and the output of the summing circuit 11 and integrating the analog signal received at the inverting input and the fed-back digital signal such that the average voltage at the output of the summing circuit 11 approaches the reference voltage, i.e. fluctuates around the reference voltage (e.g. 2.5V) at a low amplitude and high frequency. Then, the comparison circuit 12 outputs a pulse waveform based on the average voltage and the reference voltage. The ratio of the sum of times at which high levels occur in the pulse waveform to the total time in the unit sampling window is the duty ratio of the pulse signal.

By feedback and integration, the average voltage can fluctuate with low amplitude and high frequency over a range above and below the reference voltage, for example within + -10% of the reference voltage, preferably within + -5% of the reference voltage, more preferably within + -2% of the reference voltage. The average voltage oscillates at a high frequency with a low variation amplitude (e.g., in the range of ±10% or less of the reference voltage), enabling a fast step response, enabling rapid tracking of changes in analog quantities (e.g., signals of voltage, current, temperature, etc.) of the sampled circuit.

In an ADC according to the present disclosure, the addition circuit 11 and the comparison circuit 12 may be packaged together to constitute a single component. The single component may be formed by a series connection of a commercially available and inexpensive summing circuit and a comparison circuit, respectively, without the need for integration in the MCU. Furthermore, integrators are also readily available and inexpensive capacitors. The flip-flop may be a readily available and inexpensive D flip-flop or a starting circuit. Thus, the individual constituent devices are readily available and low cost, so the present disclosure enables the ADC to be implemented at a low cost. In this application, the separation device, the operational amplifier and the D flip flop are separated from each other, and they have strong alternatives in the market, and thus are all easily available in the market. In addition, the operational amplifier and the D flip-flop are also low in cost, so that an ADC formed by separate devices has a cost advantage over an internal or external ADC chip.

The closer the sampling device of the circuit is to the sampled point, the better, thus shortening the path of analog signal transmission, and reducing the noise pollution caused on the transmission path. Correspondingly, the transmission path of the digital signal is enlarged, the transmission of the digital signal can not receive noise pollution on the transmission path, and the method is suitable for long-distance transmission.

In the ADC according to the present disclosure, the operational amplifier 1 may be disposed as close as possible to the detected device since it is separated from the MCU or the controller or the like. The flip-flop 2 is set next to the operational amplifier 1 and then directly converts the sampled analog signal into a digital signal. The operational amplifier 1 and the flip-flop 2 are both provided on the sampling side, and the digital signal output from the flip-flop 2 is transmitted to the controller 4 via remote transmission. The transmission of the digital signal is not contaminated by noise on the transmission path and therefore the transmission from the trigger 2 to the controller 4 is more efficient. Furthermore, the noise introduced is small (thus, high frequency or low frequency noise is not introduced and thus the analog quantity is not affected), and the signal can be sampled with a higher bandwidth.

The circuit of the present application supports rail-to-rail inputs. For a voltage sampling range of 0V-5V, the circuit of the application can support an analog signal input range of 0.3V to 4.8V. The window range of the samples is increased and thus the resolution is also increased.

The distance from the components of the circuit to the sampled point is short, so that the noise immunity is strong, the introduced noise is small, the high bandwidth can be adopted, and the influence of the noise is not excessively introduced. Furthermore, the frequency of the clock signal (CLK) can be adjusted, so that different bandwidths can be realized for different demands. The frequency of CLK may be adjusted up for analog signals that need to be sampled at high speed, so that sampling is performed at high speed. Since transmission is mainly performed in the form of digital signals, and is insensitive to noise, transmission of digital signals can be performed over a relatively high bandwidth. The higher bandwidth may be higher than the frequency of the digital filter in the subsequent controller. The digital filter is used for extracting the digital signal output by the trigger, and the output of the digital filter can be in the form of a percentage, which can be a duty cycle corresponding to the acquired voltage, based on which the magnitude of the sampled voltage can be deduced. For example, 5V represents a duty cycle of 100%, and if a digital duty cycle is 50%, the input voltage of the circuit can be estimated to be 2.5V, and the voltage level of the sample can be further estimated by dividing the voltage.

In an ADC according to the present disclosure, the pulse signal received by the D flip-flop may come from a controller, or a Field Programmable Gate Array (FPGA). For D flip-flop devices, the frequency of the clock signal employed may range from 10kHz to 100MHz, so a larger sampling rate (e.g., sampling at 100MHz frequency) may be achieved. The higher the sampling speed, the higher the accuracy or resolution. The order of the digital filter in the controller also has an effect on the resolution, so that the ADC of the present disclosure can achieve comparable accuracy with an internal or external ADC chip at a lower cost.

If analog data amounts of a plurality of branches, such as voltages of a plurality of buses, currents of a plurality of buses, or the like, need to be collected, a plurality of paths may be provided for measurement, each path including one operational amplifier 1 and one flip-flop 2, so that a plurality of flip-flops 2 may receive the same clock signal, thereby enabling cost saving.

As shown in fig. 2, the ADC may further include weighting resistors R1 and R2, the weighting resistor R1 being connected between the detected device and the inverting input terminal, such that the analog signal is inputted to the inverting input terminal after being weighted by the weighting resistor R1, the weighting resistor R2 being connected between the feedback pin 1QZ of the flip-flop 2 and the inverting input terminal, and the digital signal being negatively fed back is inputted to the inverting input terminal after being weighted by the weighting resistor R2.

In a transient state, the amplitude of the digital signal can be considered as a constant, and the voltage after the weighting of the analog signal and the voltage after the weighting of the digital signal are superimposed at the inverting input. The characteristic that the two input ends can be regarded as equipotential when the analysis operational amplifier is in a linear state is called false short circuit, short-term virtual short, and the virtual short obtains the conclusion of equipotential of the positive input end and the negative input end. Based on the virtual short principle of the adder 11, the voltages at the same-directional input terminal and the opposite-directional input terminal of the adder 1 need to be equal, that is, the weighted superimposed voltage at the opposite-directional input terminal is equal to the reference voltage at the same-directional input terminal, so that the relationship between the input voltage and the output digital signal of the D flip-flop can be adjusted by adjusting the ratio of the weighted resistors and the reference voltage.

Although in the above the adder 11 and the comparator 12 are two separate components, it is also possible for a person skilled in the art to design them in a single device. That is, the same directional input of the adder 11 and the same directional input of the comparator 12 are combined into the same directional input, the output of the adder 11 serves as the internal output of the circuit, and the output of the comparator 12 serves as the final output of the individual devices.

In the case of an ADC connected to the mains, the voltage of the circuit is high and the D flip-flop 2 needs to be isolated from the following controller 4 to prevent electric shock. As shown in fig. 1B, the ADC may optionally further include a digital isolator 5, where the digital isolator 5 can isolate the higher sampling voltage from the voltage of the controller to meet the safety requirement. In case the ADC comprises a digital isolator 5, the main cost of the ADC is embodied on the digital isolator 5, but still much lower than the cost of the integrated ADC chip.

Effect of device errors on the results. The accuracy of the resistor is generally high, but the error of a common capacitor is between 10 and 20 percent, and the capacitor can be bought under 5 percent at a high price. For averaging circuits in the conventional technology and ADC circuits for transmitting analog quantities at a long distance, errors in the capacitor may have a certain influence on the circuits. In this application, however, the capacitor is used only as an integrator, so that the tolerance of the capacitor has only a negligible level of time effect on the result of the circuit, i.e. the problem of integration speed.

The temperature coefficient of the resistor is used in a wide temperature range, and both resistors are used as weighted resistors, which have the same temperature coefficient or temperature drift coefficient, and the drift caused by the temperature during the weighted calculation is offset. The weighting resistors R1 and R2 determine weights of the input analog quantity and the feedback digital quantity, and the weighting resistors R1 and R2 may have the same weight.

Table 1 below shows an analysis of the effect of errors in the main components (e.g., capacitors) on the output structure.

The input (input) represents the amplitude of the sampled analog signal. The 1 times capacitance is, for example, 1nf and the 2 times capacitance is, for example, 2nf. tp represents the total clock cycle number in a unit sampling window of the digital signal output by the 1Q pin of the D flip-flop, and for different voltage amplitudes, the total clock cycle number in the unit sampling window is different due to different responses of the output pulse signal, and the unit sampling window can reflect the average state of the whole pulse signal layout. In the following table, appropriate average states capable of representing the overall pulse signal layout are adopted. For example, for a capacitance tolerance of 1, 4.5V, about 21 clock cycles are chosen as the unit sampling window. Although the number of clock cycles of the window is different for each voltage unit, the clock cycles can be selected to accurately reflect the distribution of the entire pulse signal.

The number of pulses at a high level in the unit sampling window is denoted by t 1. The average value represents the ratio of t1/tp, i.e. the duty cycle of the resulting digital signal for this voltage amplitude, e.g. a total voltage of 5V representing a duty cycle of 100% (i.e. 1), a duty cycle of 4.5V being 0.896, approaching 90%, as shown in the table below. By combining the average value with the sampling range of the ADC, the input voltage can be back-deduced to be 5×89.6% =4.5V.

The error in the table below represents the percentage of the difference between the first average value obtained at 1 times the capacitance and the second average value obtained at 2 times the capacitance divided by the first average value, i.e. the error in the average value or duty cycle obtained in both cases, for example (0.896915-0.89600)/0.89600 =0.1%. By observing the tol values for different magnitudes, it can be seen that with 1 and 2 times capacitance, the effect on the duty cycle of the resulting digital signal is small, 0.1%, and essentially negligible.

TABLE 1

Fig. 3 shows the resulting average or duty cycle of the D flip-flop versus the sampled analog signal, obtained according to table 1 above. It should be noted that the specific numerical values in fig. 3 and table 1 do not limit the scope of the present disclosure. The values of tp, t1 can be arbitrarily chosen by a person skilled in the art according to the oscilloscope display, but the resulting mean or duty cycle is approximately equal to the mean or duty cycle indicated in table 1.

As illustrated in fig. 3, the horizontal axis identifies the amplitude of the input analog signal. The vertical axis identifies the ratio output by the digital filter in the controller, i.e., the duty cycle, i.e., the ratio of t1/tp described above. As can be seen from fig. 3, the sampled signal and the final ratio remain well linear before. Therefore, the linearity of the circuit is good, and in addition, the amplitude range can be from 0.5V to 4.5V, so that a wide sampling range can be provided.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection.

The various embodiments described above may be combined to provide further embodiments. Aspects of the embodiments can be modified if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims (10)

1. An analog-to-digital converter for converting an analog signal of a device under test into a digital signal, comprising:

an operational amplifier (1) configured to receive the analog signal and output a pulse signal having a duty cycle related to an amplitude of the analog signal;

a flip-flop (2) connected to the operational amplifier (1) and configured to receive a clock signal and the pulse signal and sample the pulse signal into a digital signal having the same frequency as the clock signal based on the clock signal;

wherein the operational amplifier (1) is connected to the detected device in the vicinity of the detected device for receiving the analog signal at a first input of the operational amplifier (1), and

the digital signal is fed back to the first input terminal in a negative feedback manner,

the operational amplifier (1) is further configured to receive a reference voltage at a second input,

the analog-to-digital converter further comprises an integrator (3) configured to integrate the analog signal received at the first input and the fed-back digital signal to obtain an average voltage around a reference voltage, an

The operational amplifier (1) is further configured to output the pulse signal based on the average voltage and the reference voltage.

2. An analog-to-digital converter according to claim 1, characterized in that the average voltage fluctuates within a certain range above and below the reference voltage.

3. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,

the operational amplifier (1) comprises an adder circuit (11) and a comparator circuit (12),

the adding circuit (11) comprises a first reverse input end, a first same-direction input end and a first output end, wherein the reverse input end is the first input end; and

the comparison circuit (12) comprises a second reverse input end, a second same-direction input end and a second output end, and the pulse signal is output from the second output end;

the first output is electrically connected to the second inverting input,

the first and second common-direction input terminals each receive the reference voltage, an

The integrator (3) comprises a capacitor connected in parallel between the first inverting input and the first output, such that the first output outputs the average voltage close to the reference voltage.

4. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,

the analog signal is a voltage signal, the amplitude of the analog signal varies within a voltage range, an

The duty cycle of the pulse signal or the duty cycle of the digital signal increases with an increase in the amplitude of the analog signal.

5. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,

the trigger (2) is a D trigger or a D trigger circuit,

outputting the digital signal by a first pin of the D flip-flop or D flip-flop circuit,

and outputting a feedback signal with the opposite level to the digital signal by a second pin of the D trigger or the D trigger circuit to be fed back to the first input terminal.

6. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,

the analog-to-digital converter comprises a sampling side close to the detected device and a transmission side remote from the detected device,

the operational amplifier (1), the trigger (2) and the integrator (3) are arranged on the sampling side,

the analog-to-digital converter further comprises a controller (4) arranged on the transmission side, and

the digital signal is transmitted from the trigger (2) to the controller (4).

7. The analog-to-digital converter according to claim 6, further comprising a digital isolator (5), the digital isolator (5) being connected between the flip-flop (2) and the controller (4).

8. The analog-to-digital converter of claim 1, further comprising

A first weighting resistor connected between the detected device and the first input terminal so that the analog signal is input to the first input terminal after being weighted by the first weighting resistor, an

A second weighting resistor connected between the flip-flop (2) and the first input terminal such that the digital signal of negative feedback is input to the first input terminal after being weighted by the second weighting resistor.

9. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,

a plurality of the analog-digital converters are used for collecting analog quantities of a plurality of detected devices,

a plurality of the flip-flops (2) in the plurality of the analog-to-digital converters share one clock signal.

10. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,

the frequency of the clock signal is in the range between 10kHz and 100 MHz.

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