CN103091561B - Device obtaining direct current signals from alternative current and direct current superposition signals and method thereof - Google Patents

Abstract

The invention discloses a device obtaining direct current signals from alternative current and direct current overlapped signals. The device obtaining the direct current signals from the alternative current and direct current overlapped signals comprises a controller which sends out control commands according to time sequence, a whole cycle sampling switch connected with the controller and being switched on and off according to the control commands outputted by the controller, an integral circuit connected with an output end of the whole cycle sampling switch, a sampling maintain switch, a sampling holder connected with the other end of the sampling maintain switch, wherein an integral capacitance on the integral circuit conducts integral sampling of inputted overlapped signals, and one end of the sampling maintain switch is connected with the output end of the integral circuit. After sampling of the integral circuit is finished, under the control of the controller, the whole cycle sampling switch is disconnected, the sampling maintain switch is closed, voltage of the integral capacitance is transferred to the sampling holder to be kept. The device obtaining the direct current signals from the alternative current and the direct current overlapped signals can eliminate power line interference of the overlapped signals, ensure test of the instrument not to be influenced by alternative current signals, and improve test speed.

Description

The device and method of direct current signal is extracted from alternating current-direct current superposed signal

Technical field

The present invention relates to a kind of device and method extracting direct current signal from alternating current-direct current superposed signal.

Background technology

Megger test allows a DC voltage be connected to detected element two ends, carrys out computing element insulation resistance by the electric current at element two ends and voltage.During test, measured piece is in high resistant shape substantially close to open circuit.Test sample input impedance is very high, very responsive to the electromagnetic interference (EMI) of environment.The DC voltage relevant due to tested electric current is 0.1-10mVDC, and found by the measurement of side circuit, the interference of circuit is mainly two parts, and major part is Hz noise (20mVp), and a part is white noise (5mVp) in addition.And the amplitude of white noise is far smaller than Hz noise.White noise undesired signal can be removed by simple filtering circuit, does not affect test speed.Interference when therefore testing mainly Hz noise, Hz noise common frequency is 50Hz, 60Hz.During current employing Insulation Resistance Tester test, be adopt multi-stage filter circuit to realize filtering power frequency interference signals.There is following problem in multi-stage filter circuit:

Multiple-stage filtering certainly exists the problem of low pass flex point and attenuation degree.Due to the accuracy requirement of signal, need the filtering circuit adopting characteristic flat.And this kind of circuit 10 frequency doubling attenuation coefficients comparison is little, need employing multi-stage superimposed.The flex point of the low pass-3DB of 10 frequencys multiplication is calculated just at 5Hz, 6Hz by power frequency, multi-stage superimposed just poorer.Consider that response speed just can not adopt the decay of too many level.After decay deficiency causes the interference attenuation of data, amplitude is comparatively large, and still can flood test data when small area analysis is sampled, the lower limit of measuring current cannot improve.General test electric current is all in 10E-10 magnitude, and response speed is greater than 500 milliseconds (with reference to Fig. 2).Therefore, adopt the removal undesired signal of multi-stage filter circuit, time delay is very large, makes the slow and data stability of test speed form antagonistic relations, cannot realize response fast and high stable measurement.This structure can pass through under so that proof to be described:

With reference to being when not gathering electric current in Fig. 1, figure, the interference waveform that test lead is unsettled, actual test interference may be larger.Appliance requires by this signal compression to the size not affecting test signal.The circuit of figure is used for gathering that maximum current is 1nA electric current, sampling resistor is 10M, instrument internal is enlarged into 100 times.That is the most great talent 10mVDC of sampled value, is 1V after amplifying.Circuit sampling precision is 1%, needs the electric current of steady testing 10pA, and namely sampled signal amplitude is 0.1mV.And AC noise has 20mVp, larger than the stable sampled value of actual needs 200 times.If this signal together amplified analog digital conversion circuit will be exceeded the test signal upper limit cannot work.Will by 20mVp interference attenuation to below 0.1mV, AC influence probably needs decay 60DB just can meet design requirement.Interference wave is power frequency environmental radiation, and frequency is lower.The problem that filtering must bring response speed slack-off.Instrument in the past adopts two-stage Butterworth filter, makes the response speed of sample circuit need hundreds of millisecond, cannot meet quick test request.

In addition, because test signal is extremely weak, foregoing circuit magnification ratio is very high, and while amplification test signal, undesired signal is amplified simultaneously, so that block the work of AD sample circuit.

Summary of the invention

For above-mentioned technical matters, the object of the present invention is to provide a kind of device and method extracting direct current signal from alternating current-direct current superposed signal, the present invention not only can remove the Hz noise in superposed signal, ensures that the test of instrument does not affect by AC signal, makes test speed also obtain raising.

Realize technical scheme of the present invention as follows:

From alternating current-direct current superposed signal, extract a device for direct current signal, comprise the controller sending steering order according to sequential; And

The integer-period sampled switch be connected with controller, carry out closing or disconnecting according to the steering order that controller exports, the closure time of this integer-period sampled switch equals the cycle of undesired signal; And

The integrating circuit be connected with integer-period sampled output switching terminal, at integer-period sampled switch period of contact, the superposed signal of the integrating capacitor on this integrating circuit to input carries out integration sampling; And

The sample-hold switch that one end is connected with integrating circuit output terminal, sample-hold switch carries out closing or disconnecting according to the steering order that controller exports; And

The sampling holder be connected with the sample-hold switch other end, after integrating circuit sampling, under the control of the controller, integer-period sampled switch is disconnected, sample-hold switch closes, and preserves on the voltage transfer in described integrating capacitor to sampling holder.

Further, also comprise a discharge switch be connected with controller, the two ends of this discharge switch are in parallel with the integrating capacitor of integrating circuit, under the control of the controller, sample-hold switch is disconnected, discharge switch closes, and before upper once integration period, ensures that the electric charge in described integrating capacitor is zero.

Further, described controller is CPU or sequential logical circuit.

Further, described sampling holder comprises sampling capacitance and operational amplifier, one end of sampling capacitance is connected with the in-phase input end of operational amplifier, and the other end ground connection of sampling capacitance, the inverting input of operational amplifier is connected with the output terminal of this operational amplifier.

Further, described operational amplifier is the operational amplifier of high input impedance, low output impedance.

From alternating current-direct current superposed signal, extract a method for direct current signal, comprise the following steps:

Step 1, first controller sends steering order according to sequential makes integer-period sampled switch close, the closure time of integer-period sampled switch equals the cycle of undesired signal, and at integer-period sampled switch period of contact, the superposed signal of the integrating capacitor on integrating circuit to input samples;

Step 2, after integrating capacitor sampling, controller controls integer-period sampled switch and disconnects, and controls sample-hold switch simultaneously and closes, export after the voltage transfer in integrating capacitor to sampling holder is preserved again.

Further, also comprise step 3, under the Control timing sequence of controller, after voltage transfer in integrating capacitor completes to sampling holder, controller makes sample-hold switch disconnect, and the discharge switch being parallel to integrating capacitor two ends closes, and makes integrating capacitor is discharged, before upper once integration period, ensure that the electric charge in described integrating capacitor is zero.

Further, after step 2 completes, calculated from the output voltage of sampling holder by following formula:

$\frac{\mathrm{Vo}}{V1}=\frac{1}{\mathrm{RC}}*{\∫}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In above formula, 1/RC is oversampling ratio coefficient, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the DC voltage that tested electric current is relevant, A*sin(ω t+r) be integration power frequency component, T/RC is oversampling ratio coefficient, and A*sin (r) * Kt is the ripple size exported.

Have employed such scheme, first integer-period sampled maintained switch is made to close by controller, integration sampling is carried out by the superposed signal of integrating circuit to input, closure time due to integer-period sampled switch equals the cycle of undesired signal, therefore, in sampled signal, the AC signal in superposed signal is zero just, and the voltage in integrating capacitor is the direct-flow signal voltage of sampling.When the time of integration sampling is a complete cycle of power frequency interference signals, controller makes integer-period sampled maintained switch disconnect, and makes sample-hold switch close simultaneously, exports after the voltage transfer in integrating capacitor to sampling holder is preserved again.By the device extracting direct current signal from alternating current-direct current superposed signal of the present invention, 100mS is not more than to the time delay of sampled signal.And the time delay of circuit was greater than 500mS in the past, greatly accelerated the test rate of instrument when testing apparatus is applied, met the requirement of high speed megger test.Measuring stability also improves a lot and meets the performance requirement of new instrument.

Accompanying drawing explanation

Sampling when Fig. 1 is Insulation Resistance Tester test in prior art, amplification High frequency filter signal comparison diagram;

Fig. 2 is Insulation Resistance Tester test disturbance response figure in prior art: (introducing sign mutation with hand touching test lead);

Fig. 3 is the circuit theory diagrams extracting the device of direct current signal from alternating current-direct current superposed signal of the present invention;

Fig. 4 is the sequential chart of each switch of control of controller;

Fig. 5 is that the employing device extracting direct current signal from alternating current-direct current superposed signal of the present invention is sampled to signal and after integration, signal keeps and output signal comparison figure;

Fig. 6 be this employing invention the device collection of extracting direct current signal from alternating current-direct current superposed signal and integration after signal disturbing response diagram (with hand touching test lead introduce sign mutation);

Embodiment

With reference to Fig. 3 to Fig. 4, a kind of device extracting direct current signal from alternating current-direct current superposed signal of the present invention, comprises the controller sending steering order according to sequential, and this controller is CPU or sequential logical circuit.And

The integer-period sampled K switch 1 be connected with controller, carry out closing or disconnecting according to the steering order that controller exports, the closure time of this integer-period sampled switch equals the cycle of undesired signal.And

The integrating circuit be connected with integer-period sampled output switching terminal, at integer-period sampled switch period of contact, the superposed signal of the integrating capacitor on integrating circuit to input carries out integration sampling.Closure time due to integer-period sampled switch equals the cycle of undesired signal, and therefore, in sampled signal, the AC signal in superposed signal is zero just, and the voltage in integrating capacitor is the direct-flow signal voltage of sampling.Integrating circuit is made up of operational amplifier UA, integrating capacitor C1 and resistance R, one end of resistance R is connected with integer-period sampled K switch 1, the other end of resistance R is connected to the inverting input of operational amplifier UA, the in-phase input end ground connection of operational amplifier UA, the two ends of electric capacity C1 are connected with the inverting input of operational amplifier UA and output terminal respectively.And

The sample-hold switch K3 that one end is connected with integrating circuit output terminal, sample-hold switch K3 carries out closing or disconnecting according to the steering order that controller exports; And

The sampling holder be connected with the sample-hold switch K3 other end, after integrating circuit sampling, under the control of the controller, integer-period sampled K switch 1 is disconnected, sample-hold switch K3 closes, and preserves on the voltage transfer in described integrating capacitor to sampling holder.Sampling holder comprises sampling capacitance C2 and operational amplifier UB, one end of sampling capacitance C2 is connected with the in-phase input end of operational amplifier UB, the other end ground connection of sampling capacitance C2, the inverting input of operational amplifier UB is connected with the output terminal of this operational amplifier.Operational amplifier UB is the operational amplifier of high input impedance, low output impedance, and the carrying out sent in this operational amplifier can effectively be amplified by operational amplifier effectively.And

The discharge switch K2 be connected with controller, the two ends of this discharge switch K2 are in parallel with the integrating capacitor C1 of integrating circuit, under the control of the controller, sample-hold switch K3 is disconnected, discharge switch closes, and before upper once integration period, ensures that the electric charge in described integrating capacitor is zero.

With reference to Fig. 3 to Fig. 4, from alternating current-direct current superposed signal, extract the method for direct current signal, comprise the following steps:

Step 1, first controller sends steering order according to sequential makes integer-period sampled switch close, the closure time of integer-period sampled switch equals the cycle of undesired signal, and at integer-period sampled switch period of contact, the superposed signal of the integrating capacitor on integrating circuit to input samples;

Step 2, after integrating capacitor sampling, controller controls integer-period sampled switch and disconnects, and controls sample-hold switch simultaneously and closes, export after the voltage transfer in integrating capacitor to sampling holder is preserved again.

After step 2 completes, calculated from the output voltage of sampling holder by following formula:

$\frac{\mathrm{Vo}}{V1}=\frac{1}{\mathrm{RC}}*{\∫}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In above formula, 1/RC is oversampling ratio coefficient, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the DC voltage that tested electric current is relevant, A*sin(ω t+r) be integration power frequency component, T/RC is oversampling ratio coefficient, and A*sin (r) * Kt is the ripple size exported.

Above formula (2) is a calculating formula simplifying step and obtain, and principle of the present invention is integration, is calculated as follows with concrete mathematical derivation:

The Hz noise cycle: T

Hz noise angular velocity: ω=T/ (2* π)

Hz noise amplitude: A

Power frequency interference signals is: A*sin(ω t)

Integration start-up phase parallactic angle: r

Integration power frequency component is: A*sin(ω t+r)

The deviation of integration period and interference period: Kt

The actual integration cycle is: T (1+Kt)

Formula is as follows:

$\frac{\mathrm{Vo}}{V1}=\frac{1}{\mathrm{RC}}*{\∫}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}$

$=\frac{1}{\mathrm{RC}}*T(1+\mathrm{Kt})*\mathrm{Vx}+\frac{1}{\mathrm{RC}}*\frac{A}{\mathrm{\ω}}*(\cos \left(r\right)-\cos (2*\mathrm{\π}*\mathrm{Kt}+r)$

Because circuit is actual when realizing: Kt myopia is zero

Cso (r)-cos (2* π * Kt+r) can think that waveform is at cos(r) Tiny increment dt at place, above formula can be written as

$=\frac{T}{\mathrm{RC}}*(1+\mathrm{Kt})*\mathrm{Vx}-\frac{1}{\mathrm{RC}}*\frac{A}{\mathrm{\ω}}*\sin \left(r\right)*(2*\mathrm{\π}*\mathrm{Kt})$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})$

T/RC can think oversampling ratio coefficient, is fixed constant, easily can be compensated by stoichiometric coefficient after circuit is determined.

The ripple size exported is: A*sin (r) * Kt, Kt directly determines ripple amplitude.If need the decay (1000 times) of 60DB, Kt<0.1%, and base was tens nanoseconds during instrumentation control system, if do not consider the stability of power frequency supply, the time order error of instrument generally can be less than 0.01%.

And in (1+Kt) * Vx: introducing deviation during Kt<0.1% is less than 0.1%, does not affect 1% measuring accuracy.

Therefore, through concrete calculation procedure above, the calculating formula of above formula (2) is finally obtained.

Step 3, under the Control timing sequence of controller, after voltage transfer in integrating capacitor completes to sampling holder, controller makes sample-hold switch disconnect, the discharge switch being parallel to integrating capacitor two ends closes, make integrating capacitor is discharged, before upper once integration period, ensure that the electric charge in described integrating capacitor is zero.

With reference to Fig. 5 and Fig. 6, by the device extracting direct current signal from alternating current-direct current superposed signal of the present invention, 100mS is not more than to the time delay of sampled signal.And before the time delay of circuit be greater than 500mS(by Fig. 5 and Fig. 1 and contrast, Fig. 6 and Fig. 2 is contrasted), greatly accelerate the test rate of instrument when testing apparatus is applied, meet the requirement of high speed megger test.Measuring stability also improves a lot and meets the performance requirement of new instrument.

Claims (2)

1. from alternating current-direct current superposed signal, extract a method for direct current signal, it is characterized in that, comprise the following steps:

Step 1, first controller sends steering order according to sequential makes integer-period sampled switch close, the closure time of integer-period sampled switch equals the cycle of undesired signal, and at integer-period sampled switch period of contact, the superposed signal of the integrating capacitor on integrating circuit to input samples;

Step 2, after integrating capacitor sampling, controller controls integer-period sampled switch and disconnects, and controls sample-hold switch simultaneously and closes, export after the voltage transfer in integrating capacitor to sampling holder is preserved again;

After step 2 completes, calculated from the output voltage of sampling holder by following formula:

$\frac{\mathrm{Vo}}{\mathrm{Vi}}=\frac{1}{\mathrm{RC}}*{\&Integral;}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\&omega;t}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In above formula, Vo is output voltage, Vi is input voltage, 1/RC is oversampling ratio coefficient, and Kt is the deviation of integration period and interference period, and T (1+Kt) is the actual integration cycle, Vx is the DC voltage that tested electric current is relevant, A*sin (ω t+r) is integration power frequency component, and T is the Hz noise cycle, and A*sin (r) * Kt is the ripple size exported.

2. the method extracting direct current signal from alternating current-direct current superposed signal according to claim 1, it is characterized in that, also comprise step 3, under the Control timing sequence of controller, after the voltage transfer in integrating capacitor completes to sampling holder, controller makes sample-hold switch disconnect, the discharge switch being parallel to integrating capacitor two ends closes, make integrating capacitor is discharged, before upper once integration period, ensure that the electric charge in described integrating capacitor is zero.