CN203054092U - Apparatus for extracting DC (direct current) signal from AC-DC (alternating current-direct current) superposed signal - Google Patents

Abstract

The utility model discloses an apparatus for extracting DC (direct current) signals from AC-DC (alternating current-direct current) superposed signals. The apparatus comprises a controller, a full-period sampling switch, an integrating circuit, a sampling maintenance switch and a sampling maintainer, wherein the controller issues control instructions according to time sequence; the full-period sampling switch is connected with the controller and is closed or get disconnected according to the control instructions output by the controller; the integrating circuit is connected with an output end of the full-period sampling circuit, and during the closing period of the full-period sampling switch, an integrating capacitor on the integrating circuit performs integration sampling on the input superposed signals; one end of the sampling maintenance switch is connected with an output end of the integrating circuit; and the sampling maintainer is connected with the other end of the sampling maintenance switch, and when the integrating circuit completes the sampling and under the control of the controller, the full-period sampling switch is enabled to be disconnected, the sampling maintenance switch is closed, so that the voltage on the integrating capacitor is transferred to the sampling retainer and thus is stored. The apparatus not only can remove power frequency interference in the superposed signals but also guarantees the test of the instrument to be free from the alternating-current signals, and thus test speed is improved.

Description

From the alternating current-direct current superposed signal, extract the device of direct current signal

Technical field

The utility model relates to a kind of device that extracts direct current signal from the alternating current-direct current superposed signal.

Background technology

Megger test is to allow a DC voltage be connected to the detected element two ends, and electric current and voltage by the element two ends come the computing element insulation resistance.During test, measured piece is in the high resistant shape substantially and approaches open circuit.Test sample input impedance is very high, and is very responsive to the electromagnetic interference (EMI) of environment.Because the DC voltage that tested electric current is relevant is 0.1-10mVDC, find that by the measurement of side circuit the interference of circuit is mainly two parts, major part is that power frequency is disturbed (20mVp), a part is white noise (5mVp) in addition.And the amplitude of white noise is far smaller than the power frequency interference.The white noise undesired signal can be removed by simple filtering circuit, to not influence of test speed.Interference when therefore testing mainly is that power frequency is disturbed, and it is 50Hz, 60Hz that power frequency is disturbed common frequency.When adopting the Insulation Resistance Tester test at present, be to adopt multi-stage filter circuit to realize the filtering power frequency interference signals.There is following problem in multi-stage filter circuit:

Multiple-stage filtering certainly exists the problem of low pass flex point and attenuation degree.Because the accuracy requirement of signal needs to adopt the smooth filtering circuit of characteristic.And these class circuit 10 frequency doubling attenuation coefficient ratio are less, need to adopt multi-stage superimposed.Calculate the flex point of low pass-3DB of 10 frequencys multiplication by power frequency just at 5Hz, 6Hz, multi-stage superimposed just poorer.Consider that response speed just can not adopt the decay of too many level.Decay is not enough cause the interference attenuation of data after amplitude bigger, when little current sample, still can flood test data, the lower limit of measuring current can't improve.The general test electric current is all in the 10E-10 magnitude, and response speed is greater than 500 milliseconds (with reference to Fig. 2).Therefore, the removal undesired signal of employing multi-stage filter circuit, time delay is very big, makes the slow and data stability formation antagonistic relations of test speed, can't realize response fast and high stable measurement.This structure can be passed through down with the explanation proof:

With reference to Fig. 1, among the figure when not gathering electric current, the interference waveform that test lead is unsettled, actual test is disturbed may be bigger.Appliance requires with this signal compression to the size that does not influence test signal.It is that 1nA electric current, sampling resistor are that 10M, instrument internal are enlarged into 100 times that the circuit of figure is used for gathering maximum current.That is to say the great talent 10mVDC of sampled value, amplifying the back is 1V.The circuit sampling precision is 1%, needs the electric current of steady testing 10pA, and namely the sampled signal amplitude is 0.1mV.And AC noise has 20mVp, and is bigger 200 times than the stable sampled value of actual needs.If this signal is amplified analog-to-digital conversion circuit together will can't work above the test signal upper limit.Will be with the 20mVp interference attenuation below 0.1mV, exchanging to disturb probably needs decay 60DB just can meet design requirement.Interference wave is the power frequency environmental radiation, and frequency ratio is lower.Filtering must bring the slack-off problem of response speed.Instrument in the past adopts the two-stage Butterworth filter, makes the response speed of sample circuit need the hundreds of millisecond, can't satisfy quick test request.

In addition and since test signal extremely a little less than, the foregoing circuit magnification ratio is very high, when amplifying test signal, undesired signal is amplified simultaneously, so that block the work of AD sample circuit.

Summary of the invention

At above-mentioned technical matters, the purpose of this utility model is to provide a kind of device that extracts direct current signal from the alternating current-direct current superposed signal, the power frequency that the utility model not only can be removed in the superposed signal is disturbed, the test that guarantees instrument is not influenced by AC signal, makes test speed obtain raising yet.

The realization the technical solution of the utility model is as follows:

A kind of device that extracts direct current signal from the alternating current-direct current superposed signal comprises the controller that sends steering order according to sequential; And

The integer-period sampled switch that is connected with controller carries out closure or disconnection according to the steering order of controller output, and the closure time of this integer-period sampled switch equals the cycle of undesired signal; And

The integrating circuit that is connected with integer-period sampled output switching terminal, during integer-period sampled switch closure, the integrating capacitor on this integrating circuit is carried out the integration sampling to the superposed signal of input; And

The sampling maintained switch that one end is connected with the integrating circuit output terminal, the sampling maintained switch carries out closure or disconnection according to the steering order of controller output; And

The sampling holder that is connected with the sampling maintained switch other end, after the integrating circuit sampling finishes, under the control of controller, integer-period sampled switch is disconnected, sampling maintained switch closure is transferred to the voltage on the described integrating capacitor on the sampling holder and to be preserved.

Further, also comprise a discharge switch that is connected with controller, the two ends of this discharge switch are in parallel with the integrating capacitor of integrating circuit, under the control of controller, the sampling maintained switch is disconnected, the discharge switch closure before integration period next time, guarantees that the electric charge on the described integrating capacitor is zero.

Further, described controller is CPU or sequential logical circuit.

Further, described sampling holder comprises sampling capacitance and operational amplifier, one end of sampling capacitance is connected with the in-phase input end of operational amplifier, the other end ground connection of sampling capacitance, and the inverting input of operational amplifier is connected with the output terminal of this operational amplifier.

Further, described operational amplifier is the operational amplifier of high input impedance, low output impedance.

A kind of method of extracting direct current signal from the alternating current-direct current superposed signal may further comprise the steps:

Step 1, controller sends steering order according to sequential and at first makes integer-period sampled switch closure, the closure time of integer-period sampled switch equals the cycle of undesired signal, and during integer-period sampled switch closure, the integrating capacitor on the integrating circuit is taken a sample to the superposed signal of input;

Step 2, after the integrating capacitor sampling finished, controller was controlled integer-period sampled switch and is disconnected, and the maintained switch of control sampling simultaneously closure is transferred to output again after the preservation on the sampling holder with the voltage on the integrating capacitor.

Further, also comprise step 3, under the control sequential of controller, after voltage on the integrating capacitor is transferred to sampling holder and is finished, controller disconnects the sampling maintained switch, is parallel to the discharge switch closure at integrating capacitor two ends, makes on the integrating capacitor and discharges, before integration period next time, guarantee that the electric charge on the described integrating capacitor is zero.

Further, after step 2 is finished, calculate by following formula from the output voltage of sampling holder:

$\frac{\mathrm{Vo}}{\mathrm{Vi}}=\frac{1}{\mathrm{RC}}*{{\∫}_0}^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1-\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In the following formula, 1/RC is the sampling scale-up factor, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the relevant DC voltage of tested electric current, A*sin(ω t+r) be the integration power frequency component, T/RC is the ripple size of output for sampling scale-up factor, A*sin (r) * Kt.

Adopted such scheme, at first make integer-period sampled maintained switch closure by controller, by integrating circuit the superposed signal of input is carried out the integration sampling, because the closure time of integer-period sampled switch equals the cycle of undesired signal, therefore, in the sampled signal, the AC signal in the superposed signal is zero just, and the voltage on the integrating capacitor is the direct-flow signal voltage of sampling.When the time of integration sampling was complete cycle of power frequency interference signals, controller disconnected integer-period sampled maintained switch, made sampling maintained switch closure simultaneously, and the voltage on the integrating capacitor is transferred to output again after the preservation on the sampling holder.By the device that from the alternating current-direct current superposed signal, extracts direct current signal of the present utility model, the time delay of sampled signal is not more than 100mS.And the time delay of circuit had been accelerated the test rate of instrument when testing apparatus is used greatly greater than 500mS in the past, satisfied the requirement of high speed megger test.Stable testing also improves a lot and satisfies the performance requirement of new instrument.

Description of drawings

Fig. 1 is sampling, the amplification High frequency filter signal comparison diagram when Insulation Resistance Tester is tested in the prior art;

Fig. 2 is Insulation Resistance Tester test disturbance response figure in the prior art: (introducing sign mutation with hand touching test lead);

Fig. 3 is the circuit theory diagrams that extract the device of direct current signal from the alternating current-direct current superposed signal of the present utility model;

Fig. 4 is the sequential chart of each switch of control of controller;

Fig. 5 for adopt the device that from the alternating current-direct current superposed signal, extracts direct current signal of the present utility model signal sampled and integration after, signal keeps and output signal comparison figure;

Fig. 6 for the device collection of from the alternating current-direct current superposed signal, extracting direct current signal of this employing utility model and integration after signal disturbance response figure (introducing sign mutation with hand touching test lead);

Embodiment

With reference to Fig. 3 to Fig. 4, a kind of device that extracts direct current signal from the alternating current-direct current superposed signal of the present utility model comprises the controller that sends steering order according to sequential, and this controller is CPU or sequential logical circuit.And

The integer-period sampled K switch 1 that is connected with controller is carried out closure or disconnection according to the steering order of controller output, and the closure time of this integer-period sampled switch equals the cycle of undesired signal.And

The integrating circuit that is connected with integer-period sampled output switching terminal, during integer-period sampled switch closure, the integrating capacitor on the integrating circuit is carried out the integration sampling to the superposed signal of input.Because the closure time of integer-period sampled switch equals the cycle of undesired signal, therefore, in the sampled signal, the AC signal in the superposed signal is zero just, and the voltage on the integrating capacitor is the direct-flow signal voltage of sampling.Integrating circuit is made up of operational amplifier UA, integrating capacitor C1 and resistance R, one end of resistance R is connected with integer-period sampled K switch 1, the other end of resistance R is connected in the inverting input of operational amplifier UA, the in-phase input end ground connection of operational amplifier UA, the two ends of capacitor C 1 are connected with output terminal with the inverting input of operational amplifier UA respectively.And

The sampling maintained switch K3 that one end is connected with the integrating circuit output terminal, sampling maintained switch K3 carries out closure or disconnection according to the steering order of controller output; And

The sampling holder that is connected with the sampling maintained switch K3 other end, after the integrating circuit sampling finishes, under the control of controller, integer-period sampled K switch 1 is disconnected, sampling maintained switch K3 closure is transferred to the voltage on the described integrating capacitor on the sampling holder and to be preserved.Sampling holder comprises sampling capacitance C2 and operational amplifier UB, the end of sampling capacitance C2 is connected with the in-phase input end of operational amplifier UB, the other end ground connection of sampling capacitance C2, the inverting input of operational amplifier UB is connected with the output terminal of this operational amplifier.Operational amplifier UB is the operational amplifier of high input impedance, low output impedance, and operational amplifier can effectively amplify the carrying out of sending in this operational amplifier effectively.And

The discharge switch K2 that is connected with controller, the two ends of this discharge switch K2 are in parallel with the integrating capacitor C1 of integrating circuit, under the control of controller, sampling maintained switch K3 is disconnected, the discharge switch closure before integration period next time, guarantees that the electric charge on the described integrating capacitor is zero.

With reference to Fig. 3 to Fig. 4, from the alternating current-direct current superposed signal, extract the method for direct current signal, may further comprise the steps:

Step 1, controller sends steering order according to sequential and at first makes integer-period sampled switch closure, the closure time of integer-period sampled switch equals the cycle of undesired signal, and during integer-period sampled switch closure, the integrating capacitor on the integrating circuit is taken a sample to the superposed signal of input;

Step 2, after the integrating capacitor sampling finished, controller was controlled integer-period sampled switch and is disconnected, and the maintained switch of control sampling simultaneously closure is transferred to output again after the preservation on the sampling holder with the voltage on the integrating capacitor.

After step 2 is finished, calculate by following formula from the output voltage of sampling holder:

$\frac{\mathrm{Vo}}{\mathrm{Vi}}=\frac{1}{\mathrm{RC}}*{{\∫}_0}^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1-\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In the following formula, 1/RC is the sampling scale-up factor, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the relevant DC voltage of tested electric current, A*sin(ω t+r) be the integration power frequency component, T/RC is the ripple size of output for sampling scale-up factor, A*sin (r) * Kt.

Following formula (2) is one and simplifies the calculating formula that step obtains that principle of the present utility model is integration, is calculated as follows with concrete mathematical derivation:

Power frequency interference period: T

Power frequency disturbance angle velocity: ω=T/ (2* π)

Power frequency noise amplitudes: A

Power frequency interference signals is: A*sin(ω t)

Integration start-up phase parallactic angle: r

The integration power frequency component is: A*sin(ω t+r)

The deviation of integration period and interference period: Kt

The actual integration cycle is: T (1+Kt)

Formula is as follows:

$\frac{\mathrm{Vo}}{\mathrm{Vi}}=\frac{1}{\mathrm{RC}}*{{\∫}_0}^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}$

$=\frac{1}{\mathrm{RC}}*T(1+\mathrm{Kt})*\mathrm{Vx}+\frac{1}{\mathrm{RC}}*\frac{A}{\mathrm{\ω}}*(\cos \left(r\right)-\cos (2*\mathrm{\π}*\mathrm{Kt}+r)$

Because during the actual realization of circuit: Kt myopia is zero

Cos (r)-cos (2* π * Kt+r) can think that waveform is at cos(r) little increment of locating, following formula can be written as

$=\frac{1}{\mathrm{RC}}*(1+\mathrm{Kt})*\mathrm{Vx}-\frac{1}{\mathrm{RC}}*\frac{A}{\mathrm{\ω}}*\sin \left(r\right)*(2*\mathrm{\π}*\mathrm{Kt})$

$=\frac{T}{\mathrm{RC}}*((1-\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})$

T/RC can think the scale-up factor of sampling, and determines that at circuit the back is fixed constant, can easily compensate by stoichiometric coefficient to come.

The ripple size of output is: A*sin (r) * Kt, Kt has directly determined the ripple amplitude.The decay of 60DB if desired (1000 times), Kt＜0.1% gets final product, and base was tens nanoseconds during instrumentation control system, if do not consider the stability of power frequency supply, the time of instrument generally can be less than 0.01%.

And (1+Kt) among the * Vx: Kt＜0.1% o'clock is introduced deviation less than 0.1%, to the not influence of 1% measuring accuracy.

Therefore, through top concrete calculation procedure, finally obtain the calculating formula of following formula (2).

Step 3, under the control sequential of controller, after voltage on the integrating capacitor is transferred to sampling holder and is finished, controller disconnects the sampling maintained switch, be parallel to the discharge switch closure at integrating capacitor two ends, make on the integrating capacitor and discharge, before integration period next time, guarantee that the electric charge on the described integrating capacitor is zero.

With reference to Fig. 5 and Fig. 6, by the device that from the alternating current-direct current superposed signal, extracts direct current signal of the present utility model, the time delay of sampled signal is not more than 100mS.And the time delay of circuit compared Fig. 5 and Fig. 1 greater than 500mS(in the past, and Fig. 6 and Fig. 2 are compared), accelerated the test rate of instrument when testing apparatus is used greatly, satisfy the requirement of high speed megger test.Stable testing also improves a lot and satisfies the performance requirement of new instrument.

Claims (5)

1. a device that extracts direct current signal from the alternating current-direct current superposed signal is characterized in that, comprises the controller that sends steering order according to sequential; And

The integer-period sampled switch that is connected with controller carries out closure or disconnection according to the steering order of controller output, and the closure time of this integer-period sampled switch equals the cycle of undesired signal; And

The integrating circuit that is connected with integer-period sampled output switching terminal, during integer-period sampled switch closure, the integrating capacitor on this integrating circuit is carried out the integration sampling to the superposed signal of input; And

The sampling maintained switch that one end is connected with the integrating circuit output terminal, the sampling maintained switch carries out closure or disconnection according to the steering order of controller output; And

The sampling holder that is connected with the sampling maintained switch other end, after the integrating circuit sampling finishes, under the control of controller, integer-period sampled switch is disconnected, sampling maintained switch closure is transferred to the voltage on the described integrating capacitor on the sampling holder and to be preserved.

2. a kind of device that from the alternating current-direct current superposed signal, extracts direct current signal according to claim 1, it is characterized in that, also comprise a discharge switch that is connected with controller, the two ends of this discharge switch are in parallel with the integrating capacitor of integrating circuit, under the control of controller, make the sampling maintained switch disconnect the discharge switch closure, before integration period next time, guarantee that the electric charge on the described integrating capacitor is zero.

3. a kind of device that extracts direct current signal from the alternating current-direct current superposed signal according to claim 1 and 2 is characterized in that described controller is CPU or sequential logical circuit.

4. a kind of device that from the alternating current-direct current superposed signal, extracts direct current signal according to claim 1 and 2, it is characterized in that, described sampling holder comprises sampling capacitance and operational amplifier, one end of sampling capacitance is connected with the in-phase input end of operational amplifier, the other end ground connection of sampling capacitance, the inverting input of operational amplifier is connected with the output terminal of this operational amplifier.

5. a kind of device that extracts direct current signal from the alternating current-direct current superposed signal according to claim 4 is characterized in that described operational amplifier is the operational amplifier of high input impedance, low output impedance.

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