CN104270152A - PVT insensitive common mode charge control device for charge coupling assembly line analog-digital converter - Google Patents
PVT insensitive common mode charge control device for charge coupling assembly line analog-digital converter Download PDFInfo
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Abstract
The invention relates to a circuit device used for controlling common mode charges in a charge coupling assembly line analog-digital converter. The circuit device comprises two output common mode adjusting charge transmission circuits (BBD), a common mode detection adjusting circuit and a voltage turning-off copy circuit. According to the aim of the circuit device, a common mode charge problem caused by an existing charge transmission technology is restrained, and the purpose of adjusting common mode charges precisely is achieved through two adjusting modes. According to the first adjusting mode, the large-signal characteristic of a cascade amplifier is changed by adjusting voltage of a substrate of an input tube of the cascade amplifier, and therefore on-off point voltage of a whole BBD is changed. According to the second mode, the large-signal characteristic of the cascade amplifier is changed by changing grid voltage of a parallel-connection tube M4, and the on-off point voltage of the whole BBD can be changed. The two modes are respectively used for dealing with errors of the two common mode charges.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of circuit arrangement that can be used for controlling charge coupling assembly line analog to digital converter internal common mode electric charge.
Technical background
In charge coupling assembly line analog to digital converter, the sample charge packet that obtains of charge coupled sampling-holding circuit will be delivered in the sub-level production line circuit of subsequent stages Charged Couple and compares quantification treatment step by step.For the charge coupling assembly line analog to digital converter adopting fully differential structure to realize, signal transacting synchronously carries out, finally using the difference of two signalling channel results as final process result on the positive and negative signal transacting path of two signal conditions mutual symmetry centered by common-mode signal.First input voltage signal is converted to two charge packets of fully differential form, supplies subsequent stages fully differential Charged Couple level production line circuit quantification treatment respectively, finally obtains quantizing Output rusults.
In above-mentioned charge coupling assembly line analog to digital converter, when subsequent stages Charged Couple level production line circuit processes input charge bag, its common mode charge bag size generally keeps equal constant.Under existing CMOS technology condition, due to the existence of technological fluctuation randomness and other kinds irrational factors, the common mode charge size of the Charged Couple at different levels sub-level production line circuit realized can not be strictly equal, but there is certain common-mode error.
In the factors affecting common mode charge, the impact of the charge transfer circuit module between sub-level circuit is most important.For the realization of high efficiency charge transfer technology, existing technical implementation way typically has patent: US2007/0279507A1 enhancement mode charge transfer circuit, its exemplary circuit configuration as shown in Figure 1.The grid V of transferring charge MOSFET S
gbe connected to the output of the operational amplifier 1 be made up of metal-oxide-semiconductor M1, M2 and M3.Before the output computing transferring charge of operational amplifier 1, S is in off state, and electric charge to be transmitted is stored in C
1on.Fig. 2 is the operating voltage waveform schematic diagram of this circuit.In the t0 moment, there is the more change of negative rank in Ck1, and positive exponent more change occurs Ck1n, causes Ni voltage V
nisudden change is the voltage V of No to an electronegative potential
nosudden change is to a high potential, and operational amplifier 1 will respond this change and driven MOS FET S grid V
gvoltage is high level, makes S start conducting; Due to the cause of electrical potential difference, on Ni, institute's stored charge Electronically to No transfer, will cause V
nirise and V
nodecline, operational amplifier 1 will can respond this change and driven MOS FET S grid V equally
gvoltage reduces gradually; In the t1 moment, work as V
nirise to voltage V
rtime, V
gvoltage is reduced to cut-ff voltage V gradually
thtime, S turns off again, and charge transfer process terminates, wherein V
rdetermined by the quiescent point of cascade operational amplifier.
The quantity of electric charge Q that circuit shown in Fig. 1 transmits within a clock cycle
tc can be used
1upper electric charge variable quantity represents.
Q
T＝C
1*(ΔV
Ck1-ΔV
Ni)
(1)
＝C
1*((V
Ck1(t0)-V
Ck1(t1))-(V
Ni(t0)-V
Ni(t1))
In above formula, V
ck1(t0), V
ck1(t1), V
ni(t0) all for by the directly actuated fixed amount of reference voltage; V
ni(t0) determined by signal charge amount to be transmitted, and V
ni(t1) at the end of transferring charge, voltage V is approached
r.In whole charge transfer process, V
nito V
rthe speed of approaching and precision directly determine transferring charge speed and the precision of BCT circuit.If V
rprecise and stable, then the quantity of electric charge transmitted in transmitting procedure is the linear function of signal charge to be transmitted.But due to V
rdetermined by the quiescent point of cascade operational amplifier, V
rvery responsive for PVT (technological fluctuation, supply voltage noise, variations in temperature) fluctuation.Suppose due to PVT fluctuation V
rcreate the change of Δ V, corresponding V
ni(t1) voltage variety of Δ V will be produced.By (1) formula, we can see that Δ V can directly at Q
tupper generation Δ Q=Δ V*C
1the error quantity of electric charge.
When this circuit is used by fully differential, the common mode charge amount that can obtain transmitting is:
Q
TCM＝(C
1*(ΔV
Ck1-ΔV
NiP)+C
1*(ΔV
Ck1-ΔV
NiN))/2
(2)
＝C
1*(V
Ck1(t0)-V
Ck1(t1))-C
1*((2V
Ni(t0)-V
NiP(t1)-V
NiN(t1))/2
Can find out, V
ni(t1) error brought cannot be eliminated when common mode charge transmits, and this error is directly transferred to late-class circuit, therefore must control effectively for this error.
Summary of the invention
The object of the invention is the deficiencies in the prior art, provide a kind of external signal can the insensitive common mode charge control device of PVT of Serial regulation, the common mode charge problem that existing transferring charge technology causes is suppressed.
According to technical scheme provided by the invention, the insensitive common mode charge control device of the described PVT for charge coupling assembly line analog to digital converter comprises: two output common mode tunable charge transmission circuits, common modes detect Circuit tuning, a shutoff voltage duplicate circuit; The OUT end output signal of the first output common mode tunable charge transmission circuit and the second output common mode tunable charge transmission circuit is all input to common mode and detects Circuit tuning, common mode detect Circuit tuning according to the OUT signal of the OUT signal of the first output common mode tunable charge transmission circuit, the second output common mode tunable charge transmission circuit, control clock and reference voltage V
rEFcarry out processing and output feedback signal Vfb, feedback signal Vfb are connected respectively to two output common mode tunable charge transmission circuits P end regulate OUT end output common mode, shutoff voltage duplicate circuit is according to reference voltage V
r, 1produce the B end that substrate control voltage Vbody connects two output common mode tunable charge transmission circuits; First output common mode tunable charge transmission circuit and the second output common mode tunable charge transmission circuit produce separately according to the signal of IN end, B end and P end and export OUT signal, the OUT signal of fully differential, by while the detection of common mode detection Circuit tuning, also directly outputs to next stage common mode charge control circuit;
Described output common mode tunable charge transmission circuit comprises: the drain electrode of NMOS tube M4 and NMOS tube M1 is connected to the source electrode of NMOS tube M2 simultaneously, the source electrode of NMOS tube M4 and M1 is connected to ground simultaneously, NMOS tube M1 and the grid of M4 are connected IN end and P end respectively, and the substrate electric potential of NMOS tube M1 holds control by B; The drain electrode of NMOS tube M2 is connected to the grid of transferring charge NMOS tube Ms and the drain electrode of PMOS M3, is also connected to the drain electrode of NMOS tube Men simultaneously, and the grid of NMOS tube M2 meets bias voltage Vbn; The drain electrode of PMOS M3 is connected to NMOS tube M2 source electrode, and the grid of PMOS M3 meets bias voltage Vbp, and the drain electrode of PMOS M3 connects the drain electrode of PMOS Mep; The source electrode of PMOS Mep connects supply voltage, and the grid of PMOS Mep meets work clock Ck0; The source ground of NMOS tube Men, the grid of NMOS tube Men meets work clock Ck0; Transferring charge NMOS tube Ms source, leakage and grid end connect the drain electrode of IN end, OUT end and NMOS tube M2 respectively.
Described common mode detects the P end realization that the adjustment of Circuit tuning to the output common mode electric charge of first, second output common mode tunable charge transmission circuit is the metal-oxide-semiconductor M4 by controlling first, second output common mode tunable charge transmission circuit inside respectively.
The adjustment of described shutoff voltage duplicate circuit to the output common mode electric charge of first, second output common mode tunable charge transmission circuit is the underlayer voltage B end realization of the metal-oxide-semiconductor M1 by controlling first, second output common mode tunable charge transmission circuit inside respectively.
Described common mode detects Circuit tuning and comprises a common-mode error amplifier module and an error signal processing module, common-mode error amplifier module compares difference output charge signal and Vref signal under the control controlling clock, and result is outputted to error signal processing module; Error signal processing module is carried out process to common-mode error signal and is obtained Vfb output signal, for controlling the P end of output common mode tunable charge transmission circuit.The error signal processing module that common mode detects Circuit tuning inside adopts programmable trans-conductance amplifier circuit.
Advantage of the present invention is: the object being reached accurate adjustment common mode charge by 2 kinds of adjustment modes.The first adjustment mode changes the large signal characteristic of common source and common grid amplifier by the underlayer voltage of adjustment common source and common grid amplifier input pipe, thus changes the pass break-point voltage of whole BBD.The second way changes the large signal characteristic of common source and common grid amplifier by the grid voltage changing parallel transistor M4, thus changes the pass break-point voltage of whole BBD.These two kinds of modes are respectively with dealing with aforementioned two kinds of common mode charge errors.
Accompanying drawing explanation
Fig. 1 is charge transfer circuit schematic diagram in prior art.
Fig. 2 is transferring charge oscillogram in prior art.
Fig. 3 is PVT of the present invention insensitive common mode charge control device structure chart.
Fig. 4 is the circuit diagram of output common mode tunable charge transmission circuit of the present invention (being called for short BBD).
Fig. 5 is the structural representation of shutoff voltage duplicate circuit.
Fig. 6 is a kind of specific implementation of low-power consumption error amplifier circuit in Fig. 5.
Fig. 7 is the concrete structure block diagram that common mode detects Circuit tuning.
Fig. 8 is a kind of specific implementation of common-mode error amplifier module in Fig. 7.
Fig. 9 is the specific implementation of error signal processing module able to programme in Fig. 7.
Embodiment
Below in conjunction with accompanying drawing and example, the present invention is described in more detail.
Figure 3 shows that the structured flowchart of the insensitive common mode charge control circuit of PVT provided by the invention, it comprises 2 output common mode tunable charge transmission circuits, 31 and 32, scale and detects the dependent common mode charge control circuit that 35 in Circuit tuning 33, shutoff voltage duplicate circuit 34, figure is next stage flow line circuit.The annexation of circuit shown in Fig. 3 is as follows: the OUT of output common mode tunable charge transmission circuit 31 and 32 end output signal be common mode detect Circuit tuning 33 detect and compare and treat with Vref voltage under the control controlling clock, and the output common mode that P control end output feedback signal Vfb being connected to circuit 31 and 32 regulates OUT to hold; Shutoff voltage duplicate circuit 34 is according to voltage Vr, and 1 B producing substrate control voltage Vbody control circuit 31 and 32 holds; Output common mode tunable charge transmission circuit 31 and 32 holds the signal provided to produce output signal OUT according to IN, B and P, the OUT signal of fully differential is detected while Circuit tuning 33 detects by common mode, also directly outputs to next stage (N+1 level) common mode charge control circuit.
For charge coupling assembly line ADC, affect except common mode charge except BBD closes break-point voltage by PVT change, the change of the input signal common mode electrical level of whole ADC also can make the corresponding levels and common mode charge later at different levels produce larger error, thus affects the normal work of late-class circuit.In order to tackle this two factors, BBD circuit of the present invention provides two kinds of adjustment means to control the error of sub-level circuit output common mode electric charge.The BBD circuit of this improvement is as mistake! Do not find Reference source.Shown in.The first adjustment mode changes the large signal characteristic of common source and common grid amplifier by the underlayer voltage of adjustment common source and common grid amplifier input pipe, thus changes the pass break-point voltage of whole BBD.The second way changes the large signal characteristic of common source and common grid amplifier by the grid voltage changing parallel transistor M4, thus changes the pass break-point voltage of whole BBD.These two kinds of modes are respectively with dealing with aforementioned two kinds of common mode charge errors.
Fig. 4 is the circuit diagram of output common mode tunable charge transmission circuit of the present invention.It adds 3 metal-oxide-semiconductors and 3 control signals on the basis of the charge transfer circuit of enhancement mode shown in Fig. 1,3 metal-oxide-semiconductors are respectively: a parallel drive pipe M4 (NMOS), clock-reset Mep (PMOS) and Men pipe (NMOS); 3 control signals are B, P and work clock Ck0.The annexation of circuit shown in Fig. 4 is: the drain electrode of NMOS tube M4 and M1 is connected to the source electrode of NMOS tube M2 simultaneously, and the source electrode of M4 and M1 is connected to ground simultaneously, and the grid of M1 with M4 is connected IN end and P input respectively, and the substrate electric potential of M1 turns and controlled by B; The drain electrode of M2 is connected to the grid of NMOS tube Ms and the drain electrode of PMOS M3, is also connected to the drain electrode of Men simultaneously, and the grid of M2 meets bias voltage Vbn; The drain electrode of M3 is connected to M2 source electrode, and the grid of M3 meets bias voltage Vbp, and the drain electrode of M3 connects the drain electrode of Mep; The source electrode of Mep connects supply voltage, and grid meets work clock Ck0; The source ground of Men, grid meets work clock Ck0; Transferring charge NMOS tube Ms source, leakage and grid end connect the drain electrode of IN, OUT and M2 respectively.
Figure 5 shows that the structure of shutoff voltage duplicate circuit 34.The function of this circuit realiration is the control to M1 pipe underlayer voltage in Fig. 4, i.e. the adjustment of B point current potential and control in Fig. 3.Its structure of shutoff voltage duplicate circuit 34 shown in Fig. 5 comprises error amplifier 51 and grid bootstrapping BBD duplicate circuit 52 two circuit function modules.
In grid bootstrapping BBD duplicate circuit 52, in the size of each transistor of common-source amplifier and Fig. 4, the size of main BBD circuit respective transistor must design in strict accordance with fixed proportion.Be generally reduction circuit power consumption, in circuit 52, in circuit size and main BBD circuit, corresponding metal-oxide-semiconductor size adopts the relational design of scaled down.Duplicate circuit not containing electric capacity and clock control logic, and adds voltage source V respectively at the drain terminal of transmitting switch and source
bwith bias current sources I
b.Current source I
bvery little, be only several μ A, therefore can simulate state when main BBD circuit transferring charge closes to an end well, the voltage of its S point i.e. pass break-point voltage V of closely main BBD transmitting switch
0.Error amplifier 51 in feedback control circuit is by the voltage of S point and the reference voltage V designed
rcompare, draw error signal, after row relax of going forward side by side, produce substrate control signal V
body, regulate the substrate terminal of M1 in duplicate circuit.This negative feedback can ensure that the voltage of S point approximates V all the time
r, thus suppress the impact of PVT change on duplicate circuit S point voltage to a great extent.For realizing better flexibility, the register by arranging N-bit controls the size of point current source walked from resistance string to change the size of VR, thus realizes the control of duplicate circuit breaker in middle being closed to break-point voltage.
Figure 6 shows that a kind of specific implementation of Fig. 5 medial error amplifier 51, its circuit have employed the integrator structure of Switch capacitor structure, adopting switched capacitor technique to be to realize lower power consumption, adopting traditional continuous time integrator circuit can realize above-mentioned functions equally.Feedback control signal Vbody is connected to the B end of corresponding grid bootstrapping BBD duplicate circuit 52 by error amplifier 51, can realize the control to main BBD shutoff voltage.Because feedback control signal regulates the substrate control end of main circuit and duplicate circuit simultaneously, so the pass break-point voltage of main BBD will follow the voltage of duplicate circuit S point.Feedback loop stable S point voltage, also just makes the pass break-point voltage of winner BBD approximate V all the time
r.
Figure 7 shows that common mode of the present invention detects the specific implementation structured flowchart of Circuit tuning 33, it comprises a common-mode error amplifier module and an error signal processing module.Common-mode error amplifier module compares difference output charge signal and Vref signal under the control controlling clock, and result is outputted to error signal processing module; Error signal processing module is carried out process to common-mode error signal and is obtained Vfb output signal, and the P for control BBD circuit holds.Common mode shown in Fig. 7 detects Circuit tuning, by detecting the deviation between the output common mode level of the sub-level production line of Charged Couple and reference signal, a control signal is produced according to this deviation, change the grid voltage P of parallel transistor in BBD, thus the shutoff voltage of fine setting BBD carrys out offset input signal common mode electrical level fluctuates the common mode charge error caused.
Figure 8 shows that a kind of specific implementation of common-mode error amplifier module in Fig. 7.Its structure is basic switch electric capacity sampling holder, and wherein single tube switch is PMOS switch, and complementary switch upper end is NMOS tube lower end is PMOS.Its course of work can be divided into two-phase: sample mutually and set up phase.In sampling phase, cp1 step-down, when cp is high, threshold voltage Vp and Vn and comparator syntype bias Vset receives electric capacity sole plate and climax plate is sampled; Setting up phase, electric capacity sole plate meets defeated people's signal Vip and Vin, and the difference of defeated like this people's signal and threshold signal just appears at two input ends of voltage comparator, and then voltage comparator starts to amplify.Comparison signal process of establishing is as follows: the electric charge in sampling mutually two electric capacity is C (Vset-Vip) and C (Vset-Vin) respectively; Setting up phase, due to charge conservation, the voltage of comparator two input end will be Vset-Vip+Vp and Vset-Vin+Vn respectively, is equivalent to defeated people's voltage and comparative threshold voltage to contrast, that is:
(Vset－Vip+Vp)－(Vset－Vin+Vn)＝(Vp-Vn)－(Vip－Vin) (3)
Figure 9 shows that a kind of specific implementation of the processing module of error signal described in Fig. 7.For improving design flexibility, have employed programmable trans-conductance amplifier circuit.The concrete annexation of circuit is: PMOS M3 and M4 forms simple PMOS current mirroring circuit, the grid of PMOS M3 receives the drain terminal of M3 pipe, NMOS tube M1 and M2 forms input difference pair, the drain electrode of M1 is connected to the drain electrode of M3, the drain electrode of M2 is connected to the drain electrode of M4, the source electrode of NMOS tube M1 and M2 is connected respectively to the upper end of resistance R1 and R2, the lower end of resistance R1 with R2 connects together and is connected to the drain terminal of M5 pipe, the source electrode of M5 is connected to the drain electrode of M6, the source electrode of M6 is connected to ground, NMOS tube M5 and M8 forms simple NMOS current mirroring circuit, NMOS tube M6 and M7 forms simple NMOS current mirroring circuit, the source electrode of NMOS tube M7 and M8 meets input bias current source Ib2 and Ib1 respectively, the drain electrode of NMOS tube M6 is connected to the electric current input DAC of outside adjustment code control.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, comprise two output common mode tunable charge transmission circuits, a common mode detects Circuit tuning (33), a shutoff voltage duplicate circuit (34); The OUT end output signal of the first output common mode tunable charge transmission circuit (31) and the second output common mode tunable charge transmission circuit (32) is all input to common mode and detects Circuit tuning (33), common mode detect Circuit tuning (33) according to the OUT signal of the OUT signal of the first output common mode tunable charge transmission circuit (31), the second output common mode tunable charge transmission circuit, control clock and reference voltage V
rEFcarry out processing and output feedback signal Vfb, feedback signal Vfb are connected respectively to two output common mode tunable charge transmission circuits P end regulate OUT end output common mode, shutoff voltage duplicate circuit (34) is according to reference voltage V
r, 1produce the B end that substrate control voltage Vbody connects two output common mode tunable charge transmission circuits; First output common mode tunable charge transmission circuit (31) and the second output common mode tunable charge transmission circuit (32) produce separately according to the signal of IN end, B end and P end and export OUT signal, the OUT signal of fully differential is detected while Circuit tuning (33) detects by common mode, also directly outputs to next stage common mode charge control circuit;
Described output common mode tunable charge transmission circuit comprises: the drain electrode of NMOS tube M4 and NMOS tube M1 is connected to the source electrode of NMOS tube M2 simultaneously, the source electrode of NMOS tube M4 and M1 is connected to ground simultaneously, NMOS tube M1 and the grid of M4 are connected IN end and P end respectively, and the substrate electric potential of NMOS tube M1 holds control by B; The drain electrode of NMOS tube M2 is connected to the grid of transferring charge NMOS tube Ms and the drain electrode of PMOS M3, is also connected to the drain electrode of NMOS tube Men simultaneously, and the grid of NMOS tube M2 meets bias voltage Vbn; The drain electrode of PMOS M3 is connected to NMOS tube M2 source electrode, and the grid of PMOS M3 meets bias voltage Vbp, and the drain electrode of PMOS M3 connects the drain electrode of PMOS Mep; The source electrode of PMOS Mep connects supply voltage, and the grid of PMOS Mep meets work clock Ck0; The source ground of NMOS tube Men, the grid of NMOS tube Men meets work clock Ck0; Transferring charge NMOS tube Ms source, leakage and grid end connect the drain electrode of IN end, OUT end and NMOS tube M2 respectively.
2. according to claim 1 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, described common mode detects the P end realization that Circuit tuning (33) adjustment to the output common mode electric charge of first, second output common mode tunable charge transmission circuit is the metal-oxide-semiconductor M4 by controlling first, second output common mode tunable charge transmission circuit inside respectively.
3. according to claim 1 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, the adjustment of described shutoff voltage duplicate circuit (34) to the output common mode electric charge of first, second output common mode tunable charge transmission circuit is the underlayer voltage B end realization of the metal-oxide-semiconductor M1 by controlling first, second output common mode tunable charge transmission circuit inside respectively.
4. according to claim 1 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, described common mode detects Circuit tuning (33) and comprises a common-mode error amplifier module and an error signal processing module, common-mode error amplifier module compares difference output charge signal and Vref signal under the control controlling clock, and result is outputted to error signal processing module; Error signal processing module is carried out process to common-mode error signal and is obtained Vfb output signal, for controlling the P end of output common mode tunable charge transmission circuit.
5. according to claim 4 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, described common mode detects the inner error signal processing module of Circuit tuning (33) and adopts programmable trans-conductance amplifier circuit.
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| CN106330189A (en) * | 2016-08-24 | 2017-01-11 | 黄山学院 | Charge domain capacitance digital conversion circuit |
| CN106330189B (en) * | 2016-08-24 | 2019-05-21 | 黄山学院 | A kind of charge-domain capacitor digital conversion circuit |
| CN106656183A (en) * | 2016-12-20 | 2017-05-10 | 中国电子科技集团公司第五十八研究所 | Pipelined analog-to-digital converter input common mode error feed-forward compensation circuit |
| CN106656183B (en) * | 2016-12-20 | 2020-03-31 | 中国电子科技集团公司第五十八研究所 | Input common-mode error feedforward compensation circuit of pipeline analog-to-digital converter |
| CN107733432A (en) * | 2017-11-10 | 2018-02-23 | 中国电子科技集团公司第五十八研究所 | The charge-domain pipelined ADC common mode charges error calibration system of high accuracy |
| CN107872226A (en) * | 2017-11-10 | 2018-04-03 | 中国电子科技集团公司第五十八研究所 | The charge-domain pipelined ADC calibrated using high-precision numerical model analysis |
| CN107863962A (en) * | 2017-11-10 | 2018-03-30 | 中国电子科技集团公司第五十八研究所 | The charge-domain pipelined ADC of high accuracy electric capacity unbalance calibration system |
| CN107872226B (en) * | 2017-11-10 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | The charge-domain pipelined ADC calibrated using high-precision numerical model analysis |
| CN107733432B (en) * | 2017-11-10 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | Charge-domain pipelined ADC common mode charge error calibration system in high precision |
| CN107863964A (en) * | 2017-11-10 | 2018-03-30 | 中国电子科技集团公司第五十八研究所 | Accurately control the fully differential charge transfer circuit of common mode charge amount |
| CN109150188A (en) * | 2018-08-10 | 2019-01-04 | 上海奥令科电子科技有限公司 | A kind of current mode digital-to-analog converter output-stage circuit of adjustable output common mode level |
| CN111865307A (en) * | 2020-07-09 | 2020-10-30 | 同济大学 | Noise shaping analog-to-digital converter |
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