CN101119104A - Rail-to-rail operation amplifier with high conversion ratio - Google Patents
Rail-to-rail operation amplifier with high conversion ratio Download PDFInfo
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- CN101119104A CN101119104A CNA200610108464XA CN200610108464A CN101119104A CN 101119104 A CN101119104 A CN 101119104A CN A200610108464X A CNA200610108464X A CN A200610108464XA CN 200610108464 A CN200610108464 A CN 200610108464A CN 101119104 A CN101119104 A CN 101119104A
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Abstract
The present invention is a rail to rail operational amplifier. The rail to rail operational amplifier is provided with an upside current adjusting circuit and an underside current adjusting circuit. The upside current adjusting circuit adjusts the upside bias current according to the compare of a first input voltage and a second input voltage. When the absolute difference value of the first input voltage and the second input voltage is increased, then the upside bias current is increased by the upside current adjusting circuit under the condition that the first input voltage is less than the second input voltage. The underside current adjusting circuit adjusts the underside bias current according to the compare of a first input voltage and a second input voltage. When the absolute difference value between the first input voltage and the second input voltage increases, the underside offset current increases under effect of the underside current adjusting circuit under the condition that the first input voltage is lager than the second input voltage.
Description
Technical field
The present invention relates to a kind of rail-to-rail operation amplifier (Rail-to-Rail OperationalAmplifier), relate in particular to a kind of rail-to-rail operation amplifier with high-conversion rate.
Background technology
Fig. 1 shows the circuit diagram of known rail-to-rail operation amplifier 10.With reference to Fig. 1, rail-to-rail operation amplifier 10 has complementary differential input stage, and it is made of first and second P transistor npn npn PQ1 and PQ2 and first and second N transistor npn npn NQ1 and NQ2.The source electrode of the source electrode of the one P transistor npn npn PQ1 and the 2nd P transistor npn npn PQ2 interconnects.The drain electrode of the drain electrode of the one P transistor npn npn PQ1 and the 2nd P transistor npn npn PQ2 is connected to addition output stage 11 respectively.Fixing upside bias current sources ICH is connected between upside supply voltage VH and first and second P transistor npn npn PQ1 and the interconnective source electrode of PQ2.The first input voltage vin p is applied to the grid of a P transistor npn npn PQ1, and the second input voltage vin n then is applied to the grid of the 2nd P transistor npn npn PQ2.The potential difference that the first input voltage vin p deducts the second input voltage vin n gained may be defined to differential voltage DV, i.e. DV=(Vinp-Vinn).Under the control of differential voltage DV, fixing upside bias current sources ICH is cut apart and flow through first and second P transistor npn npn PQ1 and PQ2.
The source electrode of the source electrode of the one N transistor npn npn NQ1 and the 2nd N transistor npn npn NQ2 interconnects.The drain electrode of the drain electrode of the one N transistor npn npn NQ1 and the 2nd N transistor npn npn NQ2 is connected to addition output stage 11 respectively.Fixing downside bias current sources ICL is connected between first and second N transistor npn npn NQ1 and interconnective source electrode of NQ2 and downside supply voltage VL.The first input voltage vin p is applied to the grid of a N transistor npn npn NQ1, and the second input voltage vin n then is applied to the grid of the 2nd N transistor npn npn NQ2.Under the control of differential voltage DV, fixing downside bias current sources ICL is cut apart and flow through first and second N transistor npn npn NQ1 and NQ2.
Four current signals that addition output stage 11 is come from complementary differential input stage in order to combination, i.e. four current signals that come from the drain electrode of transistor PQ1, PQ2, NQ1 and NQ2 respectively.At last, addition output stage 11 converts this kind currents combination to output voltage V out.
The mode of operation of rail-to-rail operation amplifier 10 can be divided into three scopes according to the viewpoint of common-mode voltage VCM.In the low scope of VL＜VCM＜(VL+Vtn) (Vtn is the conducting critical voltage of N transistor npn npn herein), first and second N transistor npn npn NQ1 and NQ2 all are in not on-state, so the operation of rail-to-rail operation amplifier 10 is imported performed by the upside difference that first and second P transistor npn npn PQ1 and PQ2 are constituted separately.In the high scope of (VH-|Vtp|)＜VCM＜VH (Vtp is the conducting critical voltage of P transistor npn npn herein), first and second P transistor npn npn PQ1 and PQ2 all are in not on-state, so the operation of rail-to-rail operation amplifier 10 is imported performed by the downside difference that first and second N transistor npn npn NQ1 and NQ2 are constituted.In the intermediate range of (VL+Vtn)＜VCM＜(VH-|Vtp|), because first and second P transistor npn npn PQ1 and PQ2 and first and second N transistor npn npn NQ1 and NQ2 all can normal runnings, thus the operation of rail-to-rail operation amplifier 10 by the input of upside difference to carrying out institute is common with the input of downside difference.
The advantage of rail-to-rail operation amplifier 10 is to allow common-mode voltage VCM to be present in the gamut from VL to VH, and rail-to-rail operation amplifier 10 all can be operated effectively.In the more and more low development trend of the supply voltage of electronic product now, this advantage impels the opereating specification of rail-to-rail operation amplifier to effectively utilize limited supply voltage scope.
On the other hand, the electronic product of today also is required to improve as much as possible the transmission speed of electronic data simultaneously.Particularly, when the input voltage vin p of operational amplifier and/or Vinn changed, the output voltage V out of operational amplifier can change over another state from original state in response to this variation.Output voltage V out is along with the rate of change of time is called " transfer ratio ".Transfer ratio is higher, represents the service speed of operational amplifier faster.Yet known rail-to-rail operation amplifier 10 shown in Figure 1 is not designed to have the transfer ratio higher than other types operational amplifier especially.
Therefore, expect to have the people a kind of rail-to-rail operation amplifier with high-conversion rate can be provided.
Summary of the invention
In view of foregoing problems, the object of the present invention is to provide a kind of rail-to-rail operation amplifier with high-conversion rate.
According to an aspect of of the present present invention, a kind of rail-to-rail operation amplifier is provided, comprising: upside difference input to, downside difference input to, addition output stage, upside matrix current adjustment circuit and downside matrix current adjustment circuit.This upside difference input is to being controlled by first input voltage and second input voltage, in order to the upside bias current is partitioned into first electric current and second electric current.This downside difference input is to being controlled by this first input voltage and this second input voltage, in order to the downside bias current is partitioned into the 3rd electric current and the 4th electric current.This addition output stage produces output voltage this first to the 4th current summation and based on this summation.This upside matrix current adjustment circuit based on this first and this second input voltage between this upside bias current of relatively adjustment.Under the condition of this first input voltage less than this second input voltage, when this first and this second input voltage between the absolute value of difference when increasing, this upside matrix current adjustment circuit increases this upside bias current.This downside matrix current adjustment circuit based on this first and this second input voltage between comparison and adjust this downside bias current.Under the condition of this first input voltage greater than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, this downside matrix current adjustment circuit increases this downside bias current.
Description of drawings
Fig. 1 shows the circuit diagram of known rail-to-rail operation amplifier.
Fig. 2 shows the circuit diagram according to rail-to-rail operation amplifier of the present invention.
Fig. 3 shows the detailed circuit diagram according to first example of upside matrix current adjustment circuit of the present invention.
Fig. 4 shows the detailed circuit diagram according to first example of downside matrix current adjustment circuit of the present invention.
Fig. 5 shows the operation waveform sequential chart according to rail-to-rail operation amplifier of the present invention.
Fig. 6 shows the detailed circuit diagram according to second example of upside matrix current adjustment circuit of the present invention.
Fig. 7 shows the detailed circuit diagram according to second example of downside matrix current adjustment circuit of the present invention.
The main element symbol description
10 known rail-to-rail operation amplifiers
11 addition output stages
20 according to rail-to-rail operation amplifier of the present invention
21 addition output stages
22,22a, 22b upside matrix current adjustment circuit
23,23a, 23b downside matrix current adjustment circuit
31,32,36,37,43,44,45 P transistor npn npns
33,34,35,41,42,46,47 N transistor npn npns
51,53 according to transfer ratio of the present invention
52,54 known transfer ratios
NQ1, the input of NQ2 upside difference is right
PQ1, the input of PQ2 downside difference is right
VH upside supply voltage
VL downside supply voltage
Vinp first input voltage
Vinn second input voltage
The Vout output voltage
The DV differential voltage
The upside bias current sources that ICH is fixing
The downside bias current sources that ICL is fixing
The adjustable upside bias current of IAH
The adjustable downside bias current of IAL
IOH upside compensating current element
IOL downside compensating current element
The RSH upside is set resistance
The RSL downside is set resistance
Embodiment
Explanation hereinafter and accompanying drawing will make aforementioned and other purposes of the present invention, feature, more obvious with advantage.Here describe in detail according to the preferred embodiments of the present invention with reference to the accompanying drawings.
Fig. 2 shows the circuit diagram according to rail-to-rail operation amplifier 20 of the present invention.Be to adopt upside matrix current adjustment circuits 22 so that adjustable upside bias current IAH to be provided according to the difference of rail-to-rail operation amplifier of the present invention 20 and known rail-to-rail operation amplifier 10, and adopt downside matrix current adjustment circuit 23 so that adjustable downside bias current IAL to be provided according to rail-to-rail operation amplifier 20 of the present invention.
With reference to Fig. 2, rail-to-rail operation amplifier 20 is provided with the input of upside difference to right with the input of downside difference.The input of upside difference is to being made of first and second P transistor npn npn PQ1 and PQ2, and the downside difference is imported then being made of first and second P transistor npn npn PQ1 and PQ2.Therefore, the input of upside difference is to importing the complementary differential input stage of common formation with the downside difference.Realize by the PMOS transistor though please note P transistor npn npn shown in Figure 2, also can realize by the pnp bipolar transistor.Though please note that N transistor npn npn shown in Figure 2 is implemented by nmos pass transistor, also can realize by the npn bipolar transistor.
The source electrode of the source electrode of the one P transistor npn npn PQ1 and the 2nd P transistor npn npn PQ2 interconnects.The drain electrode of the drain electrode of the one P transistor npn npn PQ1 and the 2nd P transistor npn npn PQ2 is connected to addition output stage 21 respectively.The first input voltage vin p is applied to the grid of a P transistor npn npn PQ1, and the second input voltage vin n then is applied to the grid of the 2nd P transistor npn npn PQ2.Fixing upside bias current sources ICH is connected in upside supply voltage VH, and also is connected in first and second P transistor npn npn PQ1 and the interconnective source electrode of PQ2 via upside matrix current adjustment circuit 22.Upside matrix current adjustment circuit 22 is controlled by first and second input voltage vin p and Vinn, in order to produce adjustable upside bias current IAH.Therefore, the effect of Gu Ding upside bias current sources ICH is as the reference current that is applied to upside matrix current adjustment circuit 22.Based on the comparison between first and second input voltage vin p and Vinn, upside matrix current adjustment circuit 22 makes fixing upside bias current sources ICH be converted into adjustable upside bias current IAH.Subsequently, adjustable upside bias current IAH is applied to the interconnective source electrode of first and second P transistor npn npn PQ1 and PQ2.
The source electrode of the source electrode of the one N transistor npn npn NQ1 and the 2nd N transistor npn npn PQ2 interconnects.The drain electrode of the drain electrode of the one N transistor npn npn NQ1 and the 2nd N transistor npn npn NQ2 is connected to addition output stage 21 respectively.The first input voltage vin p is applied to the grid of a N transistor npn npn NQ1, and the second input voltage vin n then is applied to the grid of the 2nd N transistor npn npn NQ2.Fixing downside bias current sources ICL is connected in the interconnective source electrode of first and second N transistor npn npn NQ1 and NQ2 via downside matrix current adjustment circuit 23, and also is connected in downside supply voltage VL.Downside matrix current adjustment circuit 23 is controlled by first and second input voltage vin p and Vinn, in order to produce adjustable downside bias current IAL.Therefore, the effect of Gu Ding downside bias current sources ICL is as the reference current that is applied to downside matrix current adjustment circuit 23.Based on the comparison between first and second input voltage vin p and Vinn, downside matrix current adjustment circuit 23 makes fixing downside bias current sources ICL be adjusted to adjustable downside bias current IAL.Subsequently, adjustable downside bias current IAL is applied to first and second N transistor npn npn NQ1 and the interconnective source electrode of NQ2.
Fig. 3 shows the detailed circuit diagram according to the first example 22a of upside matrix current adjustment circuit 22 of the present invention.With reference to Fig. 3, P transistor npn npn 31 and 32 constitutes the difference adjustment unit.The source electrode of P transistor npn npn 31 is connected in the source electrode of P transistor npn npn 32.Fixing upside bias current sources ICH is connected in P transistor npn npn 31 and 32 interconnective source electrodes.The first input voltage vin p is applied to the grid of P transistor npn npn 31, and the second input voltage vin n then is applied to the grid of P transistor npn npn 32.
N transistor npn npn 34 self connects into a diode.The grid and the drain electrode of N transistor npn npn 34 interconnect, and are connected to the drain electrode of P transistor npn npn 32.The source electrode of N transistor npn npn 34 is connected to downside supply voltage VL.
N transistor npn npn 33 and 35 and P transistor npn npn 36 and 37 common constitute current lens unit.The grid of the grid of N transistor npn npn 33 and N transistor npn npn 35 interconnects.The grid and the drain electrode of N transistor npn npn 33 interconnect, and are connected to the drain electrode of P transistor npn npn 31.N transistor npn npn 33,34 and 35 source electrode all are connected in downside supply voltage VL.The grid of the grid of P transistor npn npn 36 and P transistor npn npn 37 interconnects.The grid and the drain electrode of P transistor npn npn 36 interconnect, and are connected to the drain electrode of N transistor npn npn 35.The source electrode of the source electrode of P transistor npn npn 36 and P transistor npn npn 37 all is connected to upside supply voltage VH.It is right that the drain electrode of P transistor npn npn 37 provides adjustable upside bias current IAH to import to the upside difference that is made of first and second P transistor npn npn PQ1 and PQ2 shown in Figure 2.
Upside matrix current adjustment circuit 22a operates according to the comparison between the first input voltage vin p and the second input voltage vin n.Consider that at first fixing upside bias current sources ICH is divided into two part electric currents, its flow through respectively P transistor npn npn 31 and 32.When the first input voltage vin p became big gradually, the current ratio regular meeting of the P transistor npn npn 31 of flowing through diminished gradually, and it is big that the current ratio of the P transistor npn npn 32 of flowing through then becomes gradually.On the contrary, when the second input voltage vin n became big gradually, the current ratio regular meeting of the P transistor npn npn 32 of flowing through diminished gradually, and it is big that the current ratio of the P transistor npn npn 31 of flowing through then becomes gradually.The image feature that provides current lens unit to provide, the current ratio of the P transistor npn npn 31 of flowing through correspondingly is sent to the drain electrode of P transistor npn npn 37, in order to as adjustable upside bias current IAH.Therefore, based on the comparison between the first input voltage vin p and the second input voltage vin n, upside matrix current adjustment circuit 22a provides adjustable upside bias current IAH effectively.
In the foundation embodiments of the invention, the breadth length ratio of P transistor npn npn 31 (W/L) P31 is designed to breadth length ratio (W/L) P32 less than P transistor npn npn 32, for example (W/L) P31: (W/L) P32=1: 5.Therefore, when the first input voltage vin p equals the second input voltage vin n, the fixing upside bias current sources ICH overwhelming majority P transistor npn npn 32 of can flowing through, and the small part P transistor npn npn 31 of flowing through is only arranged.In such cases, when if the first input voltage vin p becomes greater than the second input voltage vin n, the current ratio of P transistor npn npn 31 of flowing through only reduces a little, when if the first input voltage vin p becomes less than the second input voltage vin n on the contrary, the current ratio of the P transistor npn npn 31 of flowing through then increases significantly.
Realize by the PMOS transistor though please note P transistor npn npn shown in Figure 3, also can realize by the pnp bipolar transistor.Realize by nmos pass transistor though please note N transistor npn npn shown in Figure 3, also can realize by the npn bipolar transistor.
Fig. 4 shows the detailed circuit diagram according to the first example 23a of downside matrix current adjustment circuit 23 of the present invention.With reference to Fig. 4, N transistor npn npn 41 and 42 constitutes the difference adjustment unit.The source electrode of N transistor npn npn 41 is connected in the source electrode of N transistor npn npn 42.Fixing downside bias current sources ICL is connected in N transistor npn npn 41 and 42 interconnective source electrodes.The first input voltage vin p is applied to the grid of N transistor npn npn 41, and the second input voltage vin n then is applied to the grid of N transistor npn npn 42.
P transistor npn npn 44 self connects into a diode.The grid and the drain electrode of P transistor npn npn 44 interconnect, and are connected to the drain electrode of N transistor npn npn 42.The source electrode of P transistor npn npn 44 is connected to upside supply voltage VH.
P transistor npn npn 43 and 45 and N transistor npn npn 46 and 47 common constitute current lens unit.The grid of the grid of P transistor npn npn 43 and P transistor npn npn 45 interconnects.The grid and the drain electrode of P transistor npn npn 43 interconnect, and are connected to the drain electrode of N transistor npn npn 41.P transistor npn npn 43,44, all be connected to upside supply voltage VH with 45 source electrode.The grid of the grid of N transistor npn npn 46 and N transistor npn npn 47 interconnects.The grid and the drain electrode of N transistor npn npn 46 interconnect, and more are connected to the drain electrode of P transistor npn npn 45.The source electrode of the source electrode of N transistor npn npn 46 and N transistor npn npn 47 all is connected to downside supply voltage VL.The drain electrode of N transistor npn npn 47 supply adjustable downside bias current IAL import to the downside difference that is constituted by first and second N transistor npn npn NQ1 and NQ2 shown in Figure 2 right.
Downside matrix current adjustment circuit 23a operates according to the comparison between the first input voltage vin p and the second input voltage vin n.Consider that at first fixing downside bias current sources ICL is divided into two part electric currents, its flow through respectively N transistor npn npn 41 and 42.When the first input voltage vin p became big gradually, the current ratio regular meeting of the N transistor npn npn 41 of flowing through became greatly gradually, and the current ratio of the N transistor npn npn 42 of flowing through then diminishes gradually.On the contrary, when the second input voltage vin n became big gradually, the current ratio regular meeting of the N transistor npn npn 42 of flowing through became greatly gradually, and the current ratio of the N transistor npn npn 41 of flowing through then diminishes gradually.By the image feature that current lens unit provided, the current ratio of the N transistor npn npn 41 of flowing through is sent to the drain electrode of N transistor npn npn 47 accordingly, in order to as adjustable downside bias current IAL.Therefore, based on the comparison between the first input voltage vin p and the second input voltage vin n, downside matrix current adjustment circuit 23a provides adjustable downside bias current IAL effectively.
In the foundation embodiments of the invention, the breadth length ratio of N transistor npn npn 41 (W/L) N41 is designed to breadth length ratio (W/L) N42 less than N transistor npn npn 42, for example (W/L) N41: (W/L) N42=1: 5.Therefore, when the first input voltage vin p equals the second input voltage vin n, the overwhelming majority of the fixing downside bias current sources ICL N transistor npn npn 42 of can flowing through, and the small part N transistor npn npn 41 of flowing through is only arranged.In such cases, when if the first input voltage vin p becomes greater than the second input voltage vin n, the current ratio of N transistor npn npn 41 of flowing through increases significantly, if when the first input voltage vin p became less than the second input voltage vin n on the contrary, the current ratio of the N transistor npn npn 41 of flowing through only reduced a little.
Realize by the PMOS transistor though please note P transistor npn npn shown in Figure 4, also can realize by the pnp bipolar transistor.Realize by nmos pass transistor though please note N transistor npn npn shown in Figure 4, also can realize by the npn bipolar transistor.
Describe in detail according to the method for operation of rail-to-rail operation amplifier 20 of the present invention as follows at this with reference to Fig. 2 and 5.At first suppose to rise (or second input voltage vin n moment descend), make differential voltage DV moment become to be higher than zero a lot (are stairstepping rise change) in 1, the first input voltage vin p moment of time T.Therefore, the adjustable upside bias current IAH that is produced from upside matrix current adjustment circuit 22 diminishes, and becomes big from the adjustable downside bias current IAL that downside matrix current adjustment circuit 23 is produced.Can know from Fig. 5 and to find out and since adjustable downside bias current IAL become degree that big degree diminishes than adjustable upside bias current IAH exceed a lot of, so the still increase significantly of the formed total bias current of both additions.Under the situation that total bias current increases, the service speed of rail-to-rail operation amplifier 20 is enhanced.Therefore, during time T 1 to T2 in, the transfer ratio of the output voltage V out of rail-to-rail operation amplifier 20 is enhanced, and makes it promptly become high potential from electronegative potential, shown in the solid line among Fig. 5 51.By contrast since total the bias current of known rail-to-rail operation amplifier 10 immobilize, so the output voltage V out of known rail-to-rail operation amplifier 10 rises as shown in the pecked line among Fig. 5 52 lentamente.
Next suppose to descend (or second input voltage vin n moment rise), make differential voltage DV moment become to be lower than zero a lot (are stairstepping descend change) in 3, the first input voltage vin p moments of time T.Therefore, the adjustable upside bias current IAH that is produced from upside matrix current adjustment circuit 22 becomes big, and diminishes from the adjustable downside bias current IAL that downside matrix current adjustment circuit 23 is produced.Can know from Fig. 5 and to find out and since adjustable upside bias current IAH become degree that big degree diminishes than adjustable downside bias current IAL exceed a lot of, so the still increase significantly of the formed total bias current of both additions.Under the situation that total bias current increases, the service speed of rail-to-rail operation amplifier 20 is enhanced.Therefore, during time T 3 to T4 in, the transfer ratio of the output voltage V out of rail-to-rail operation amplifier 20 is enhanced, make its promptly from the high potential transition to electronegative potential, shown in the solid line among Fig. 5 53.By contrast since total the bias current of known rail-to-rail operation amplifier 10 immobilize, so the output voltage V out of known rail-to-rail operation amplifier 10 descends as shown in the pecked line among Fig. 5 54 lentamente.
Fig. 6 shows the detailed circuit diagram according to the second example 22b of upside matrix current adjustment circuit 22 of the present invention.The difference of second example 22b shown in Figure 6 and the first example 22a shown in Figure 3 is that the second example 22b also is provided with fixing upside compensating current element IOH.As preamble with reference to as described in Fig. 5, during time T 1 to T2 in, adjustable upside bias current IAH can reduce.If this moment, rail-to-rail operation amplifier 20 operated in the low scope of VL＜VCM＜(VL+Vtn), owing to have only the input of upside difference that PQ1 and PQ2 are activated in the complementary input stage, so the service speed of rail-to-rail operation amplifier 20 only determines according to adjustable upside bias current IAH.For fear of the minimizing of adjustable upside bias current IAH and cause harmful effect for service speed, upside matrix current adjustment circuit 22b also is provided with fixing upside compensating current element IOH in output, in order to the lower limit as adjustable upside bias current IAH.
Subsidiary one carries, and the second example 22b shown in Figure 6 must also be provided with upside and set resistance R SH, and it is connected between the source electrode of fixing upside bias current sources ICH and P transistor npn npn 31.Owing to must consider the limited potential difference dVH that electric current is caused when flowing through upside setting resistance R SH,, upside matrix current adjustment circuit 22b is transformed into (Vinp+dVH)＜Vinn so beginning to improve the operating condition of adjustable upside bias current IAH.In other words, suitably select upside to set the operating condition that resistance R SH can handle upside matrix current adjustment circuit 22b effectively.
Fig. 7 shows the detailed circuit diagram according to the second example 23b of downside matrix current adjustment circuit 23 of the present invention.The difference of second example 23b shown in Figure 7 and the first example 23a shown in Figure 4 is that the second example 23b also is provided with fixing downside compensating current element IOL.As preamble with reference to as described in Fig. 5, during time T 3 to T4 in, adjustable downside bias current IAL can diminish.If this moment, rail-to-rail operation amplifier 20 operated in the high scope of (VH-|Vtp|)＜VCM＜VH, owing to have only the input of downside difference that NQ1 and NQ2 are activated in the complementary input stage, so the service speed of rail-to-rail operation amplifier 20 only determines according to adjustable downside bias current IAL.For fear of the minimizing of adjustable downside bias current IAL and cause harmful effect for service speed, downside matrix current adjustment circuit 23b also is provided with fixing downside compensating current element IOL in output, in order to the lower limit as adjustable downside bias current IAL.
Subsidiary one carries, and the second example 23b shown in Figure 7 must also be provided with downside and set resistance R SL, and it is connected between the source electrode of fixing downside bias current sources ICL and N transistor npn npn 41.Owing to must consider the limited potential difference dVL that electric current is caused when flowing through downside setting resistance R SL,, upside matrix current adjustment circuit 22b is transformed into Vinn＜(Vinp+dVL) so beginning to improve the operating condition of adjustable downside bias current IAL.In other words, suitably select downside to set the operating condition that resistance R SL can handle downside matrix current adjustment circuit 23b effectively.
Though the present invention is illustrated as illustration by preferred embodiment, should understand: the embodiment that the invention is not restricted to disclose here.On the contrary, this invention is intended to contain conspicuous for a person skilled in the art various modifications and similar configuration.Therefore, the scope of claim should be according to the widest annotation, and this type of is revised and similar configuration to comprise all.
Claims (10)
1. rail-to-rail operation amplifier comprises:
The input of upside difference is right, is controlled by first input voltage and second input voltage, in order to the upside bias current is partitioned into two part electric currents;
The input of downside difference is right, is controlled by this first input voltage and this second input voltage, in order to the downside bias current is partitioned into two other part electric current; And
The addition output stage in order to making up these two part electric currents and this two other part electric current, and produces output voltage based on this combination,
It is characterized in that also comprising:
The upside matrix current adjustment circuit, based on this first and this second input voltage between comparison and adjust this upside bias current, make under the condition of this first input voltage less than this second input voltage, when this first and this second input voltage between the absolute value of difference when increasing, this upside bias current increases, and
The downside matrix current adjustment circuit, based on this first and this second input voltage between comparison and adjust this downside bias current, make under the condition of this first input voltage greater than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, this downside bias current increases.
2. rail-to-rail operation amplifier as claimed in claim 1, wherein:
Under the condition of this first input voltage greater than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, this upside matrix current adjustment circuit reduces this upside bias current, and
Under the condition of this first input voltage less than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, this downside matrix current adjustment circuit reduces this downside bias current.
3. rail-to-rail operation amplifier as claimed in claim 1, wherein:
This upside matrix current adjustment circuit comprises:
The difference adjustment unit, controlled by this first input voltage and this second input voltage, in order to fixing upside bias current sources is partitioned into first electric current and second electric current, make under the condition of this first input voltage less than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, this first electric current is enhanced, and
Current lens unit is in order to transmit this first electric current as this upside bias current.
4. rail-to-rail operation amplifier as claimed in claim 3, wherein:
This difference adjustment unit comprises:
The one P transistor npn npn, have source electrode, grid, with drain electrode, this source electrode is connected in this fixing upside bias current sources, this grid is controlled by this first input voltage, this drain electrode is connected in this current lens unit, and
The 2nd P transistor npn npn, have source electrode, grid, with drain electrode, this source electrode is connected in this fixing upside bias current sources, this grid is controlled by this second input voltage, this drain electrode is connected in downside and supplies voltage,
Wherein the breadth length ratio of a P transistor npn npn is designed to the breadth length ratio less than the 2nd P transistor npn npn.
5. rail-to-rail operation amplifier as claimed in claim 3, wherein:
Under the condition of this first input voltage greater than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, this first electric current is lowered.
6. rail-to-rail operation amplifier as claimed in claim 5, wherein:
This upside matrix current adjustment circuit also comprises:
The upside compensating current element is in order to the lower limit as this upside bias current.
7. rail-to-rail operation amplifier as claimed in claim 1, wherein:
This downside matrix current adjustment circuit comprises:
The difference adjustment unit, controlled by this first input voltage and this second input voltage, in order to fixing downside bias current sources is partitioned into the 3rd electric current and the 4th electric current, make under the condition of this first input voltage greater than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, the 3rd electric current is enhanced, and
Current lens unit is in order to change the 3rd electric current as this downside bias current.
8. rail-to-rail operation amplifier as claimed in claim 7, wherein:
This difference adjustment unit comprises:
The one N transistor npn npn, have source electrode, grid, with drain electrode, this source electrode is connected in this fixing downside bias current sources, this grid is controlled by this first input voltage, this drain electrode is connected in this current lens unit, and
The 2nd N transistor npn npn, have source electrode, grid, with drain electrode, this source electrode is connected in this fixing downside bias current sources, this grid is controlled by this second input voltage, this drain electrode is connected in upside and supplies voltage,
Wherein the breadth length ratio of a N transistor npn npn is designed to the breadth length ratio less than the 2nd N transistor npn npn.
9. rail-to-rail operation amplifier as claimed in claim 7, wherein:
Under the condition of this first input voltage less than this second input voltage, when this first and this second input voltage between the absolute value of this difference when increasing, the 3rd electric current is lowered.
10. rail-to-rail operation amplifier as claimed in claim 9, wherein:
This downside matrix current adjustment circuit also comprises:
The downside compensating current element is in order to the lower limit as this downside bias current.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200610108464XA CN101119104A (en) | 2006-08-04 | 2006-08-04 | Rail-to-rail operation amplifier with high conversion ratio |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200610108464XA CN101119104A (en) | 2006-08-04 | 2006-08-04 | Rail-to-rail operation amplifier with high conversion ratio |
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| CN101119104A true CN101119104A (en) | 2008-02-06 |
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| CNA200610108464XA Pending CN101119104A (en) | 2006-08-04 | 2006-08-04 | Rail-to-rail operation amplifier with high conversion ratio |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834575A (en) * | 2009-03-09 | 2010-09-15 | 成都芯源系统有限公司 | Operational amplifier |
| CN101958692A (en) * | 2010-10-19 | 2011-01-26 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
| CN102355212A (en) * | 2011-08-09 | 2012-02-15 | 复旦大学 | Rail-to-rail input stage with current compensation function |
| CN102737593A (en) * | 2011-03-31 | 2012-10-17 | 瑞鼎科技股份有限公司 | Output buffer of source driver |
| CN103560760A (en) * | 2013-11-13 | 2014-02-05 | 丹纳赫（上海）工业仪器技术研发有限公司 | Amplification circuit and measurement device |
| CN106877829A (en) * | 2015-12-10 | 2017-06-20 | 矽创电子股份有限公司 | Operational amplifier |
| CN107850911A (en) * | 2015-06-18 | 2018-03-27 | Tdk株式会社 | Low difference voltage regulator device |
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- 2006-08-04 CN CNA200610108464XA patent/CN101119104A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834575A (en) * | 2009-03-09 | 2010-09-15 | 成都芯源系统有限公司 | Operational amplifier |
| CN101834575B (en) * | 2009-03-09 | 2013-09-18 | 成都芯源系统有限公司 | Operational amplifier |
| CN101958692A (en) * | 2010-10-19 | 2011-01-26 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
| CN101958692B (en) * | 2010-10-19 | 2013-09-04 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
| CN102737593A (en) * | 2011-03-31 | 2012-10-17 | 瑞鼎科技股份有限公司 | Output buffer of source driver |
| CN102737593B (en) * | 2011-03-31 | 2014-11-19 | 瑞鼎科技股份有限公司 | Output buffer of source driver |
| CN102355212A (en) * | 2011-08-09 | 2012-02-15 | 复旦大学 | Rail-to-rail input stage with current compensation function |
| CN103560760A (en) * | 2013-11-13 | 2014-02-05 | 丹纳赫（上海）工业仪器技术研发有限公司 | Amplification circuit and measurement device |
| CN107850911A (en) * | 2015-06-18 | 2018-03-27 | Tdk株式会社 | Low difference voltage regulator device |
| US10401888B2 (en) | 2015-06-18 | 2019-09-03 | Tdk Corporation | Low-dropout voltage regulator apparatus |
| CN106877829A (en) * | 2015-12-10 | 2017-06-20 | 矽创电子股份有限公司 | Operational amplifier |
| CN106877829B (en) * | 2015-12-10 | 2019-06-21 | 矽创电子股份有限公司 | Operational amplifier |
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